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GB2541772B - Synchronous differential signaling protocol - Google Patents

Synchronous differential signaling protocol

Info

Publication number
GB2541772B
GB2541772B GB201608882A GB201608882A GB2541772B GB 2541772 B GB2541772 B GB 2541772B GB 201608882 A GB201608882 A GB 201608882A GB 201608882 A GB201608882 A GB 201608882A GB 2541772 B GB2541772 B GB 2541772B
Authority
GB
United Kingdom
Prior art keywords
signaling protocol
differential signaling
synchronous differential
synchronous
protocol
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
GB201608882A
Other versions
GB201608882D0 (en
GB2541772A (en
Inventor
Kumar Bhoodev
Ramakrishnan Muraleedharan
Oppula Vivek
Hoff Thomas
Zwart Willem
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cirrus Logic International Semiconductor Ltd
Original Assignee
Cirrus Logic International Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US15/159,760 external-priority patent/US10305671B2/en
Application filed by Cirrus Logic International Semiconductor Ltd filed Critical Cirrus Logic International Semiconductor Ltd
Publication of GB201608882D0 publication Critical patent/GB201608882D0/en
Publication of GB2541772A publication Critical patent/GB2541772A/en
Application granted granted Critical
Publication of GB2541772B publication Critical patent/GB2541772B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40019—Details regarding a bus master
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/403—Bus networks with centralised control, e.g. polling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/08—Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
    • H04L25/085—Arrangements for reducing interference in line transmission systems, e.g. by differential transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/08—Speed or phase control by synchronisation signals the synchronisation signals recurring cyclically
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/10—Arrangements for initial synchronisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Dc Digital Transmission (AREA)
GB201608882A 2015-05-21 2016-05-20 Synchronous differential signaling protocol Active GB2541772B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201562164872P 2015-05-21 2015-05-21
US15/159,760 US10305671B2 (en) 2015-05-21 2016-05-19 Synchronous differential signaling protocol

Publications (3)

Publication Number Publication Date
GB201608882D0 GB201608882D0 (en) 2016-07-06
GB2541772A GB2541772A (en) 2017-03-01
GB2541772B true GB2541772B (en) 2019-12-25

Family

ID=56369676

Family Applications (1)

Application Number Title Priority Date Filing Date
GB201608882A Active GB2541772B (en) 2015-05-21 2016-05-20 Synchronous differential signaling protocol

Country Status (1)

Country Link
GB (1) GB2541772B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050132114A1 (en) * 2003-12-15 2005-06-16 Finisar Corporation Two-wire interface having dynamically adjustable data fields depending on operation code
US20140025999A1 (en) * 2011-10-05 2014-01-23 Analog Devices, Inc. Two-wire communication system for high-speed data and power distribution
US20140101351A1 (en) * 2012-10-05 2014-04-10 Analog Devices, Inc. Two-wire communication protocol engine

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050132114A1 (en) * 2003-12-15 2005-06-16 Finisar Corporation Two-wire interface having dynamically adjustable data fields depending on operation code
US20140025999A1 (en) * 2011-10-05 2014-01-23 Analog Devices, Inc. Two-wire communication system for high-speed data and power distribution
US20140101351A1 (en) * 2012-10-05 2014-04-10 Analog Devices, Inc. Two-wire communication protocol engine

Also Published As

Publication number Publication date
GB201608882D0 (en) 2016-07-06
GB2541772A (en) 2017-03-01

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