GB2457059A - Means for sampling in analogue to digital converters - Google Patents

Abstract

A means for increasing the sampling rate of analogue to digital converters comprises using a number of clocked sampling circuits 113 in parallel, but staggering the sampling instants such that the each sampler samples the same signal 125 as the others but at a different time but before the output of the previous sampler has reached its final value. This is achieved using clocking means 124 to generate pulse streams of the same frequency but delayed with respect to each other. The sampling means may be incorporated in a sigma delta, flash or pipeline ADC.

Description

Improved Method of Sampling in Analogue to Digital Converters "Improved Method of Sampling in Analogue to Digital Converters"

Background and Prior Art

This invention relates to improved sampling comparators for use in analogue to digital converters which permit higher sampling frequencies.

All digital to analogue converters require the comparison of a signal with at least one reference signal at specified sampling instants, usually at regular timing intervals, to produce a digital signal. For example, in "Flash" converters, as illustrated in figure 1, a multiplicity of such sampling converters, 117, simultaneously compare the signal, 110, at the sampling time provided by a clock source 111 with a multiplicity of reference signals which are normally uniformly spaced over the permitted range of signal values by division of a reference signal 112 with a chain of resistors 113. Combinational logic then converts this set of digital signals to a digital binary word for subsequent digital signal processing, storage or communications.

In successive approximation converters, the input signal is sampled and held as an analogue signal in a storage means, known as a sample hold or track store, is compared repeatedly, by means of a clocked comparator or flash con verter with a reference signal obtained from a digital to analogue converter whose input derives from the output of the previous iteration of the conversion, and storing the result in a register. This may be implemented either by using the same circuit recursively, updating register during each iteration, or by using separate circuits for each stage of the iteration. This clearly has the advantage that if the residue, or remaining error between the signal being measured and the signal represented by the digital value so far measured, is held in a sample hold to use as the input to the next stage, the first stage may then start digitising the next sample. This is the basic idea behind prior art pipeline analogue to digital converters.

Delta sigma converters, also called sigma delta converters, illustrated in figure 2, usually comprise a sampling comparator, 117, producing a stream of binary pulses, at well over the Nyquist rate, whose input comes from the output of a linear loop filter, 121, whose input is the difference between the input signal, 110, and the said sampling comparator output pulse stream, 123. This forms a non-linear feedback ioop which adjusts the pulse stream so that it matches the input signal over the pass-band of the loop filter. The digital output of the converter is obtained by decimation of the sampling comparator output bit stream by a digital filter. The comparator output bit stream has conceptually been passed through a I bit digital to analogue converter, the accuracy of which, i.e. the consistency of the pulse amplitudes, limits the overall converter accuracy. Clearly also, accuracy is enhanced by increasing the loop gain over the signal bandwidth, and by maximizing the over-sampling rate.

Page 1 The quantization of all analogue to digital converters is achieved by means of implementing sampling comparators is to use some kind of high gain amplifier whose output saturates at signal levels within the voltage range accepted by logic circuits as either "1" or "0". Such a circuit must be preceded or possibly, as in Flash converters, followed by some sampling and storage means to define the sampling instant according to a sampling clock signal, and ensure that the output is held at a constant value long enough for it to have finished being used by the subsequent circuitry. The analogue accuracy required of the digital output signal depends on the type of converter. In cases of flash converters the accuracy had only to be adequate to prevent ambiguity about whether the output is a "1" or a "0". In the case of a successive approximation converter, variation in the comparator output voltage could cause some variation in the signal presented to the successive stage, resulting in errors. However these problems are small compared to that encountered in a sigma delta converter in which the output of the comparator which comprises the (digital) output bit stream is in fact also the (analogue) feedback signal compared with the input within the feedback loop. This can easily be the limiting factor in the performance of the converter, particularly at high sampling speeds. However the use of high gain multi-stage amplification required for this, causes its own problems: apart from the tendency to high frequency instability of high gain multi-stage amplifiers, the delay, silicon area and probably more importantly, power consumption increase in proportion to the number of stages.

Instead of achieving the high gain required by means of a multi-stage amplifier, positive feedback may be used as in the conventional Schmitt trigger circuit as. Such a prior art circuit to achieve this is shown in figure 3 from the classic textbook "CMOS Analogue Circuit Design" by P.E. Allen and D.R. Holberg (ISBN 0-03-006587-9). These have a transfer characteristic which displays hysteresis which, unless it is very small, this can causes errors and compromise performance. Such small amounts of hysteresis require a ioop gain which very accurately equal to -l The fact that the input signal is still connected to the bistable circuit could still have some effect on the output signal. As well as that, it would need to be followed by some digital clocked storage device to set the sampling instant and hold the digital value till required. A better solution is to combine the -action of sampling with regeneration in a clocked regenerative sampler, as illustrated in Figure 4. Clocked samplers, in fact, unlike Schmitt triggers, have no requirement to minimize the hysteresis in the interests of accuracy. In fact the larger the better as the last thing one wishes is for the state to change in the middle of being used by other circuits! Since the regenerative circuit rapidly approaches an attractor which would normally be a constant signal value (voltage or current), it would be unlikely to be affected by smaller, parasitic, feedback paths in the way that a high gain cascaded amplifier would, and would, in fact, act as a discrete time system All clocked sampler circuits, whether regenerative or not, involve some delay between the sampling instant determined by the clock pulse, and the output signal being available for use. For Page2 many applications this does not in itself matter were it not for the fact that it limits the sampling rate of many analogue to digital circuits.

One way of reducing this limitation that is used to improve the speed of successive approximation analogue to digital converters is to implement recursive processing as in line processing. This is what is done in the case of prior art pipeline converters as illustrated in Figure 5. In this the conversion of the signal is performed in a number of stages wherein a first stage samples the signal in some sample hold or track store means digitizes this sample to a certain resolution which may be from one bit upwards. The residue, that is the difference between the actual signal sample and the value given by the digital output of the first stage is then passed to a second similar stage, which performs a similar quantization of the said residue while the first stage performs quantization of a new sample. This means that a N stage pipeline will be processing N staggered samples at any one time, which is obviously N times as fast as waiting for the completion of processing of one sample before embarking on the next. The basic algorithm is similar to a successive approximation ADC, but with each iteration performed on its own hardware. Although the time to convert a particular sample is not reduced, the sampling rate is increased by a factor of N. In many cases this is more important than the delay.

Drawings Figure 1 shows a simplified block diagram of a typical flash analogue to digital converter.

Figure 2 shows a simplified block diagram of a typical delta sigma analogue to digital converter.

Figure 3 shows a prior art Schmitt trigger regenerative comparator.

Figure 4 shows a prior art clocked regenerative comparator as illustrated in US patent no: 6037890A1 by Glass, Khalil and McDaniel of Intel.

Figure 5 shows a prior art pipeline analogue to digital converter as illustrated in.

Figure 6 illustrates the principle of a clocked sampler according to the invention Figure 7 shows a flash converter according the the invention Figure 8 shows a delta sigma converter according the the invention

Description

What is taught by the invention herein is sampling substantially the same signal, 125, within the converter by a plurality of elemental saixipling comparators, 113, with the same input, each clocked by different clocking pulse streams of the same frequency but delayed with respect to each other generated by a generating means 124. In the preferred embodiments herein the pulses would be arranged so that the comparators would each sample in turn with the same time between successive samples. The samples from the comparators are then combined by a Page3 summing or combining means, 122, to produce a pulse stream 123, at a rate of the sampling rate of the individual samplers multiplied by the number of samplers. In the above description the term "substantially" is used to allow for the fact that it will normally be the case that the signal to be sampled will be buffered by some optional buffering, amplifying or other isolating, and ideally identical means, 126, before reaching each clocked sampler, to reduce any interaction between the individual elemental samplers.

In this the sampling comparators are in a pipeline to form the same function as a sampling comparator operating at N times the sampling rate. This type of pipelining is quite distinct from pipelining as referred to in prior art in which the pipelined elements, themselves sampling comparators or flash converters, sample residues from previous stages.

One design issue which must be considered when using this approach, is that since different hardware is used for each of the N samples, care must be taken to ensure that the different offsets of the different component comparators to not cause undue amounts of signal at the sample rate of the individual component comparators, in the digital output. This does not occur in single comparators as the offset error is the same for all measurements This problem is, of course mitigated by monolithic implementation of the circuit.

In a first, preferred, embodiment, the invention is applied to a flash converter as illustrated in figure 7. This is straightforward to understand, and is almost the same as N flash converters acting in parallel with staggered clocks. The difference is only that the same resistive divider network. What is achieved by it is just the increase in sampling rate, as opposed by prior art pipelining which achieves higher resolution as N is increased, but at the same sample rate.

In a second embodiment, a successive approximation converter is made by the replacing clocked comparators of a prior art pipelining ADC, as previously described, with multiple comparators with staggered clock pulses as taught by the invention.

In a third embodiment, a successive approximation converter is made by replacing a flash converters of more than one bit resolution of a prior art pipelining ADC, with flash converters comprising the first embodiment.

In a fourth embodiment illustrated in figure 8, a plurality of clocked comparators, 113, with staggered clocks according to the invention, provided by clock generating means 124, are used as the comparator in a sigma delta converter (or delta sigma converter. The terms refer to the same devices.) This would increase the sampling rate by N, as usual. However it would not decrease the delay. With conventional comparators these two are inversely related and the benefits of increasing the sampling rate are attributable to both. The stability of sigma delta loops Page4 cannot be addressed by straightforward linear analysis as the action of the grossly non-linear, and indeed discontinuous sampler is at the heart of the behaviour. The usual assumption is that the quantization noise which is the loop error signal uniform power spectral density which is then added at the output of the filter to produce the comparator output. The total power in the output pulses is obviously constant, and so for a given input signal within the converter pass band, so is the quantisation noise. This noise power spectral density is then filtered by the loop by a function proportional to 1/Ill +$H(w)e0TIi2 where H(w) is the frequency response of the filter, and l is the feedback factor, and T the delay from the sampling instant to the centroid if the pulse. For maximum duration rectangular pulses producing a staircase waveform, T must be larger than half the sampling period. This means that the noise is attenuated at frequencies at which the gain of the filter is high, but is boosted at frequencies at which the locus of $H(jw)e'°T passes close to -1.

The signal output power, by contrast, varies as IIH(jw)/1+j3H(jw)eJTII2, which remains reasonably constant if It$H(w)II exceeds unity by a reasonable amount. Note that these relations are derived solely from the linear elements in the model and exclude the comparator and do not involve the comparator. So although it may look superficially similar, 13H(jw) cannot be identified with the loop gain of a linear feedback loop and linear stability criteria are irrelevant. The system is thus designed that the quantisation noise is moved from the passband, which is usually, but not necessarily, centred at zero frequency, to other frequencies at which it can be filtered out by anti-alias and decimation filters, a technique known as noise shaping.

Clearly peaks in the noise spectral density near to the pass band are to be avoided. These are more likely to occur with larger delays, T, and so the benefits which might be expected from increasing the sampling rate of a conventional sampler may not be fully achieved using the technology of this patent, but the improvements in noise shaping are still substantial.

There is a significant extra benefits, though, lie in band pass analogue to digital conversion. The fact that the technique can enable comparators based on conventional CMOS circuits to sample at GHz rates, as has been demonstrated in detailed SPICE simulation, opens up the possibilities of direct conversion at radio frequencies without the need for high specification anti-alias filters such as SAW filters, which cannot be tuned to different frequencies. PageS

Claims (9)

1. A clocked sampling means comprising a multiplicity of elemental sampling means, each with substantially the same input, optionally amplifying, isolating or buffering means connecting said input to the said elemental sampling means, a means of generating clocking pulse streams all of the same frequency but delayed with respect to each other, each of which determines the sampling instants of one of the said elemental sampling means, and a summing or other combining means to combine the output pulses of all the said elemental combiners.

2. A clocked sampling comparator means according to claim I wherein the delays between successive said clocking pulse streams are the same.

3. An analogue to digital converter comprising at least one clocked sampling comparator means according to Claims I or 2 together with other means according to the type of converter.

4. A flash analogue to digital converter comprising means to generate multiple reference signals, a multiplicity of clocked sampling comparators according to claim 3, timing 205 pulse generator means.

5. A successive approximation pipeline analogue to digital converter comprising at least one clocked comparator means according to claims I or 2, together with timing, differencing and buffering means required for such converters.

6. A successive approximation pipeline converter according to prior art design but 210 comprising at least one flash converter according to claim 4 of more than one hit resolution, together with timing, differencing and buffering and sample hold means as required for such converters.

7. A sigma delta digital to analogue converter according to claim 3.

8. An analogue to digital converter according to claim 7 wherein the pass-band is centred at 215 some frequency apart from zero.

9. A digital to analogue converter substantially as herein described and illustrated in Figures 5, 6 or 7 of the accompanying drawings. Page6