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GB2387715A - A sub-mount for an optoelectronic device - Google Patents

A sub-mount for an optoelectronic device Download PDF

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Publication number
GB2387715A
GB2387715A GB0209015A GB0209015A GB2387715A GB 2387715 A GB2387715 A GB 2387715A GB 0209015 A GB0209015 A GB 0209015A GB 0209015 A GB0209015 A GB 0209015A GB 2387715 A GB2387715 A GB 2387715A
Authority
GB
United Kingdom
Prior art keywords
bump
submount
sub
metal pad
optoelectronic device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB0209015A
Other versions
GB0209015D0 (en
Inventor
Cher Liang Randall Cha
Kian Hin Victor Teo
Yee Loy Lam
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
DenseLight Semiconductors Pte Ltd
Original Assignee
DenseLight Semiconductors Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by DenseLight Semiconductors Pte Ltd filed Critical DenseLight Semiconductors Pte Ltd
Priority to GB0209015A priority Critical patent/GB2387715A/en
Publication of GB0209015D0 publication Critical patent/GB0209015D0/en
Publication of GB2387715A publication Critical patent/GB2387715A/en
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4256—Details of housings
    • G02B6/4257—Details of housings having a supporting carrier or a mounting substrate or a mounting plate
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4266—Thermal aspects, temperature control or temperature monitoring
    • G02B6/4268—Cooling
    • G02B6/4272—Cooling with mounting substrates of high thermal conductivity
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4266—Thermal aspects, temperature control or temperature monitoring
    • G02B6/4273—Thermal aspects, temperature control or temperature monitoring with heat insulation means to thermally decouple or restrain the heat from spreading
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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Semiconductor Lasers (AREA)

Abstract

A sub-mount having a structure for affixing one or more optoelectronic device chips, the structure comprising a plurality of bump studs on a metal pad which is located on the substrate of the sub-mount, each bump stud comprising a metal protrusion which when heated is capable of bonding to the surface of the optoelectronic device. Subarrays of bump studs may perform different functions such as local or external electrical connectivity, thermal dissipation and structural support, with routing pattens connecting together studs associated with the same function.

Description

A SUB-MOUNT FOR AN OPTOELECTRONIC DEVICE
Field of the Invention
The present invention relates to a sub-mount for an optoelectronic device, and in 5 particular a structure on the sub-mount for mounting the optoelectronic device and for enhancing heat dissipation from the device Background to the Invention
An ongoing problem in improving the performance and power scaling of many 10 optoelectronic devices is the generation of heat and its effective dissipation. During operation, many semiconductor optoelectronic devices generate substantial heat which not only raises the temperature of the device itself but, via radiative and conductive heat transfer, also raises the temperature of adjacent devices and substrates. The optoelectronic device often forms part of an integrated chip and is typically fabricated on 15 a thick substrate, which conducts heat away from the active region of the device.
Although heat dissipation may be improved by employing a thin device substrate, this approach is generally limited by fabrication constraints, therefore necessitating external heat removal mechanisms.
The thermal problem is particularly acute for high power semiconductor laser 2 0 devices, where large amounts of heat can be generated within the small active region of the device. In the case of a III-V semiconductor laser the rise in temperature can result in a change in the energy band-gap of the semiconductor leading to a undesired shift in the wavelength of the laser. Thermal expansion of the laser cavity can lead to further changes in wavelength, and in particular may lead to mode hopping of the losing 2 5 frequency in single longitudinal mode devices. Furthermore, thermally induced stress can result in optical distortion and can compromise structural integrity.
A common industry approach to tackling these problems is to use techniques whereby one side of the semiconductor optoelectronic chip is attached to a cooling mechanism, to ensure that heat generated by the semiconductor device is efficiently 3 o transported away from the active regions. In the 'm-side down" arrangement, the side of the semiconductor device in close proximity to the active region is attached to the cooling component, offering greater thermal gradient in terms of proximity of the active region to the cooling element. In a generalized optoelectronic device where multi-patterned optical tracks are integrated to the semiconductor optoelectronic emitters, the p-side down
:' configuration offers superior thermal transportation. However, better access to sections of the emitter and optical circuitry is provided by the e-side down approach, in which the other chip face, usually containing the negative electrical connection, is attached to the cooling element. This arrangement permits superior device integration.
5 Semiconductor laser chips are therefore often bonded to metallized regions, or pads, on one side of a sub-mount. Positioning of the semiconductor laser chip on the sub mount may be achieved by means of conventional flip chip technologies. The sub-mount can act as an optical bench on which other components may be located. The pads provide the necessary electrical toutings to power the semiconductor laser, and need to 10 be electrically isolated from one another as well as from the submount material.
Connection to the pads is usually achieved by a deposit of solder, which is typically drawn out into a column. The solder provides the electrical connection for laser operation and also removing heat from the operating laser by conduction and radiation.
Furthermore, the solder acts as a chip support providing a particular vertical spacing of 15 the chip from the sub-mount. Such a layout requires planned estates for solder placement, and usually a substantial area of the sub-mount is utilized.
The sub-mount may be fabricated in part from a material such as semiconducting À silicon, which in addition to its low-cost and high mechanical strength, is characterized by high thermal conductivity. However, if the sub-mount does not have a high thermal 20 conductivity and the pads need to be electrically connected to a thermal back plane (TBP), there will be only one avenue for rapid heat removal. There is therefore a need for an improved heat dissipation mechanism and also for the separation of the various roles currently performed by the single solder deposits.
In the semiconductor industry, one known method for supplying electrical power 2 5 to a semiconductor device chip is the use of a small semiconductor wafer or die with a wire bonded pad on one side and plated bumps on the other. The wafer is positioned above the semiconductor device chip so that the plated bumps are brought into electrical contact with it. Electrical power can then be delivered to the upperwire bonded pad from an external connection and thence via the plated bumps to the chip itself. This approach 3 0 avoids the need for a single large piece of solder to provide the electrical contact to the device chip.
Summary of the Invention
According to a first aspect of the present invention, there is provided a sub-mount having a structure for affixing an optoelectronic device chip to a sub-mount, the structure comprising a plurality of bump studs on a metal pad, the metal pad being located on a 5 substrate of the sub-mount, each bump stud comprising a metal protrusion which when heated is capable of bonding to a surface of the optoelectronic device.
In order to facilitate conduction of heat, it is preferred that one or more bump studs on the metal pad have a high thermal conductivity.
Preferably, the metal pad has a high thermal conductivity.
10 Preferably, the metal pad is connected to a thermally conducting routing pattern.
In order to facilitate conduction of electrical energy to power the optoelectronic device, it is preferred that one or more bump studs on the metal pad have a high electrical conductivity. Preferably, the metal pad has a high electrical conductivity.
15 Preferably, the metal pad is connected to an electrically conducting routing pattem. Preferably, the individual bump studs are fabricated from gold.
Preferably, the bump studs are arranged on the metal pad in a rectangular array, although other arrangements are possible, including an array that is substantially circular 2 0 in shape.
The present invention therefore provides a means for mounting and supporting an optoelectronic chip on a sub-mount while simultaneously providing the means for delivering electrical power to the chip and removing heat from the chip. The distribution of heat in the optoelectronic chip and in the supporting structure could lead to undesirable 25 anisotropic stresses being placed on the chip. Therefore it is preferred that the bump studs are arranged in a configuration that both minimises thermally-induced stress and also ensures that any such stress is substantially uniform across the chip.
According to a second aspect of the present invention, a structure for affixing an optoelectronic device to a sub-mount comprises a plurality of metal pads located on a 3 o substrate of the sub-mount, each metal pad including a plurality of bump studs according to the first aspect of the present invention.
Preferably, at least two metal pads are in close proximity.
Preferably, the metal pads are disposed to form a regular array of bump studs beneath the optoelectronic device. Preferably, the regular array is rectangular.
Preferably, each metal pad is electrically isolated from each other metal pad.
Preferably, each metal pad is thermally isolated from each other metal pad.
Thus, the present invention provides a means for mounting an optoelectronic device chip on a sub-mount, whereby the neighbouring arrays of bump studs can perform 5 a range of functions, including structural support for the device chip, heat dissipation and electrical connectivity to both other devices located on the sub-mount and to external connections delivering electrical power via the sub-mount.
Preferably, each pad of bump studs performs a different function selected from one of following: local electrical connectivity, external electrical connectivity, thermal 10 dissipation and structural support for the optoelectronic device chip.
The sub-mount may function as an optical bench on which several devices, or device chips are located, some or all of the devices being optically coupled. Each device can be mounted on the sub-mount by means of bump stud arrays, according to the present invention. Routing patters fabricated on the sub-mount may then connect 15 together subarrays of bump studs associated with different devices butwhich perform the same function, such as the conduction of electrical or thermal energy, thereby increasing the functionality of the sub-mount or optical bench.
Brief Description of the Drawings
2 0 Examples of the present invention will now be described in detail with reference to the accompanying drawings, in which: Figure 1 shows a plan view of conventional solder bump and routing pattern for electrical connectivity; Figure 2 shows a plan view of an embodiment of a micro-bump array sectioned 2 5 to perform multiple functions; Figure 3 shows a conventional process for fabricating a gold bump; and, Figures 4A to 4E show the process steps for fabricating a micro-bump array; Detailed Description
3 0 Optoelectronic devices such as the semiconductor laser are often mounted on a sub-mount, which can act as an optical bench for the coupling of light to other components and can also provide a convenient base for the electrical toutings used to deliver electrical power to the devices mounted on the sub-mount. The optoelectronic device is typically affixed to the sub-mount by means of a solder deposit in the form of a
large bump. Flip chip technology is employed to position and hold the device chip at the correct vertical spacing while the solder solidifies to form a permanent join.
In addition to providing structural support for the chip, the solder bump often provides the route by which electrical power is delivered to the device. Figure 1 shows a 5 schematic representation of a conventional solder bump with an electrical routing to a connecting pad for external electrical connection. The solder bump will usually provide the route by which heat generated in the optoelectronic device is removed, in addition to heat generated within the solder due to the conduction of electrical power. This heating, together with the spatially non-uniform nature of its generation can lead to mechanical 10 stresses in the solder bump, which are transmitted to the device chip it supports.
The problem may be alleviated somewhat by using two or three smaller solder bumps to support and affix the device chip to the sub-mount in place of a single large solder bump. However, in the present invention, an array of micro-bumps is used to support and affix the device chip to the sub-mount, with sub-arrays of the micro-bumps 15 being assigned to perform different functions. Figure 2 shows a schematic representation of a micro-bump array which would replace the solder bump of Figure 1, while occupying substantially the same area of the sub-mount substrate. As illustrated, the micro-bumps are arranged in a rectangular m x n array, with sub-arrays of micro-bumps shaded according to the function they are to perform.
2 0 The base dimensions of these micro-bumps would typically be in the range from several tens to hundreds of microns. However, the height of the micro-bumps would only be approximately ten to twenty microns, considerably less than the height achieved with current mounting techniques. This feature may allow a more planar integration of the device chip with other components.
2 s Although the whole array of micro-bumps may be located on a common metal pad, typically the different functional sub-arrays will be fabricated on separate metal pads that are electrically and thermally isolated from each other where necessary. In the example shown in Figure 2, there are four distinct functions performed by sub-arrays of micro bumps, including local electrical connection to the device by means of electrical bumps 3 o and an electrical routing to a connection pad. Some of these electrical bump sub-arrays may be employed to connect to other devices on the sub-mount by means suitable electrical toutings. A separate sub-array and routing pattern can be used for external electrical connections.
Similarly, one or more sub-arrays of thermal bumps may be used to remove heat from the optoelectronic device chip and then conduct it away via thermally conductive toutings to an external heat removing mechanism. Ideally, these thermal bumps will be disposed in close proximity to the source of heat generation, such as the active region in 5 a semiconductor laser diode. The density of the thermal bumps and shape of the sub arrays they form can be tailored to the specific requirements of the optoelectronic device.
Finally, one or more sub-arrays of micro-bumps may be used exclusively for chip support. These micro-bumps need not exhibit high electrical or thermal conductivity and, indeed, it may not be desirable for them to do so. Although support for the device chip will 10 supplied by all the micro-bumps, those whose role is exclusively chip support can be fabricated from suitable materials and be strategically located to relieve localized mechanical stress and assist in providing uniform support across the entire area of the chip. Neighbouring arrays of micro- bumps may be used to position other devices, including photodiodes, at the correct vertical spacing from the sub-mount to ensure 15 maximum optical coupling between devices.
A further benefit of using arrays of micro-bumps is that less material is required for the bumps and so more expensive materials, including gold (Au) and gold based alloys, may be employed in order to exploit their superior properties. Figure 3 shows the steps used to fabricate gold bumps using a conventional electroplating technique. An 2 0 aluminium pad is fabricated on a silicon substrate and the edge protected and insulated by a passivation layer. A seed metal layer of TiW/Au is then deposited by sputtering. Next a thick layer of resist is deposited and patterned to define the intended location of the gold bump, the metal for which is deposited by an electroplating process. After stripping away the resist and etching away the exposed seed metal, the gold bump is finally 2 5 annealed.
The above process can be modified to generate arrays of gold micro-bumps as illustrated in Figures 4A to 4E. Each process step is shown with both a plan view of the processed region and a cross-section X)C' through this region. Initially a base stack of metal is deposited on a substrate, the base stack comprising a thin layer (150nm) of Ti 3 o or TiW and a thin layer (300nm) of Au followed by a thicker layer (1-3,um) of Au. This metal stack is patterned to define the base pad for the micro-bump array together with other toutings and connection pads. A passivation layer is then deposited and patterned to define the location of the intended microbumps and also to protect and insulate the
l underlying metal stack. A range of materials may be used for this layer including benzocyclobutene (BCB), polyimide, oxide and nitride.
In the next step a thin layer of seed metal is deposited by evaporation, the seed metal serving as a continuous conducting layerforthe electroplating process. The height, 5 and in part the lateral extent, of the micro-bumps is determined by the deposition of a thick layer of photoresist. Following the deposition of the bump material by electroplating, the photoresist is stripped and the exposed surface cleaned. At this stage the exposed seed metal may be removed by wet etching, although this step may be deferred until after further shaping and processing of the bumps.
10 For eutectic bumps, which may be formed from a solder, a reflow process is used to shape the deposited bump metal to yield a more spherical bump shape. Priorto reflow, flux maybe spun on to the bump metal and removed afterward. The flux material is usually an organic or inorganic precursor. During the bump reflow step, the flux agent melts and removes the oxide on the metallic pad surface. In addition, it wets the metal 15 pad surface, protecting it from subsequent oxidation. As the plated eutectic solder melts, it will only wick or move towards the wetted surface. If the bump material is a metal such as gold, an annealing step may be used instead, together with the application and removal of a flux agent. Finally, a region of metal adjacent to the micro- bump array is patterned and exposed to provide a pad for external connection to the array.
2 o The above process can be repeated, or performed simultaneously, to fabricate several neighbouring arrays of micro-bumps, each array essentially being a sub-array of an overall larger array. Each sub-array of micro-bumps can be fabricated for optimal performance of a particular function, such as electrical or thermal conduction. Typically each subarray will be insulated from the other sub-arrays, although two or more sub 25 arrays may be fabricated with connectivity by means of a strip of under-bump metal beneath the passivation layer. In this case it may not be necessary to pattern an external connecting pad for every sub-array, but only those near the perimeter of the overall array.
There is also no requirement to pattern external connecting pads for the sub-arrays of micro-bumps concerned exclusively with device chip support.

Claims (16)

1. A submount having a structure for affixing an optoelectronic device to the submount, the structure comprising a plurality of bump studs on a metal pad, the metal 5 pad being located on a substrate of the submount, each bump stud comprising a metal protrusion which when heated is capable of bonding to a surface of the optoelectronic device.
2. A submount according to claim 1, in which a bump stud is thermally conducting.
3. A submount according to claim 1 or 2, in which the metal pad is thermally conducting.
4. A submount according to any of claims 1 to 3, in which the metal pad is connected 15 to a thermally conducting routing pattern.
5. A submount according to any preceding claim, in which a bump stud is electrically conducting. 2 0
6. A submount according to any preceding claim, in which the metal pad is electrically conducting.
7. A submount according to any preceding claim, in which the metal pad is connected to an electrically conducting routing pattern.
8. A submount according to any preceding claim, in which a bump stud is fabricated from gold.
9. A submount according to any preceding claim, in which bump studs are arranged 3 o in a rectangular array.
10. A submount according to any preceding claim, in which bump studs are arranged to minimise thermally-induced anisotropic stresses on the optoelectronic device.
l
11. A submount having a plurality of structures for affixing an optoelectronic device to the submount, each structure comprising a plurality of bump studs on a metal pad according to any preceding claim.
5
12. A submount according to claim 11, in which a metal pad is thermally isolated from another metal pad.
13. A submount according to claim 11 or 12, in which a metal pad is electrically isolated from another metal pad.
14. A submount according to any of claims 11 to 13, in which each structure performs a function selected from one of the following: local electrical connectivity, external electrical connectivity, thermal dissipation and structural support for the optoelectronic device chip.
15. A submount according to any preceding claim, wherein the submount is an optical coupling bench.
16. An optoelectronic device affixed to a submount according to any preceding claim.
GB0209015A 2002-04-19 2002-04-19 A sub-mount for an optoelectronic device Withdrawn GB2387715A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107591475A (en) * 2017-09-29 2018-01-16 旭宇光电（深圳）股份有限公司 High power LED device and LED chip die-bonding method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020100955A1 (en) * 1999-02-22 2002-08-01 Scott G. Potter Method and apparatus for extending fatigue life of solder joints semiconductor device

Patent Citations (1)

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Publication number Priority date Publication date Assignee Title
US20020100955A1 (en) * 1999-02-22 2002-08-01 Scott G. Potter Method and apparatus for extending fatigue life of solder joints semiconductor device

Non-Patent Citations (1)

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Title
Electronic Manufacturing Technology Symposium, 1995, Proc.of 1995 International, 18th IEEE/CPMT International, 4-6 Dec 1995, Yoshida et al, pp 56-59 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107591475A (en) * 2017-09-29 2018-01-16 旭宇光电（深圳）股份有限公司 High power LED device and LED chip die-bonding method
CN107591475B (en) * 2017-09-29 2018-11-30 旭宇光电（深圳）股份有限公司 High power LED device and LED chip die-bonding method

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