GB2368753A

GB2368753A - Code group identification and frame synchronization in DS-CDMA systems

Info

Publication number: GB2368753A
Application number: GB0105872A
Authority: GB
Inventors: Hui-Ming Wang; Ju-Chun Wu; Ching-Hong Lin
Original assignee: Industrial Technology Research Institute ITRI
Current assignee: Industrial Technology Research Institute ITRI
Priority date: 2000-10-30
Filing date: 2001-03-09
Publication date: 2002-05-08
Anticipated expiration: 2021-03-09
Also published as: TW490981B; GB2368753B; DE10110708C2; FR2816142B1; GB0105872D0; FR2816142A1; DE10110708A1

Abstract

A method for code group identification and frame synchronization in a direct-sequence (DS) code division multiple access (CDMA) communication system comprising a base station which periodically transmits a specific secondary synchronization code sequence (SSCS). Each SSCS has a length of L codes and corresponds to a specific code group. The method comprises: <SL> <LI>(a) sensing and sampling the specific SSCS received from the base station to form a reference code sequence (RCS) 42 whose length is less than L codes; <LI>(b) comparing the RCS with all possible code sequences 46 to find a candidate code group and a relevant frame boundary, each of the possible code sequences is generated by sampling adjacent codes of a cyclic shifted SSCS and has a length the same as the RCS, wherein the candidate code group and the relevant frame boundary correspond to one of the possible code sequences which has the highest likelihood with the RCS; <LI>(c) appending, when the comparison shows that the candidate code group is not unique 48, the RCS by adding a received code from the base station into the RCS 50, and repeating step (b); <LI>(d) outputting, when the candidate code group is unique, the candidate code group and relevant frame boundary for synchronizing 56. </SL> The method may further comprise repeating steps (b) to (e) to obtain a plurality of candidate code groups and relevant frame boundaries and electing by majority voting 58 the most likely code group and relevant frame boundary for output.

Description

TITLE METHOD AND APPARATUS FOR CODE GROUP IDENTIFICATION AND FRAME SYNCHRONIZATION IN DS-CDMA SYSTEMS BACKGROUND OF THE INVENTION Field of the Invention The present invention generally relates to an apparatus and method for code group identification and frame synchronization

used in direct-sequence code division multiple access (DS-CDMA) communication systems, such as wide-band CDMA systems and 3rd generation partnership project (3GPP) system.

Description of the Related Art Currently, DS-CDMA cellular systems are classified as inter-cell synchronous systems with precise inter-cell synchronization and asynchronous systems without it. For inter-cell synchronous systems, an identical long code is assigned to each base station, but with a different time offset.

The initial cell search can be executed by performing timing acquisition of the long code. The search for a peripheral cell on hand-overs can be carried out quickly because the mobile station can receive the offset information of the long code for the peripheral base station from the current base station.

However, each base station requires a precise-time consistent apparatus, such as the global position system (GPS) and rubidium backup oscillators. However, it is difficult to deploy GPS in basements or other locations where RF signals cannot easily reach.

In asynchronous systems such as wide-band CDMA and 3GPP, each base station adopts two synchronization channels as shown in Fig. 1, such that a mobile terminal can establish the link and will not lose the connection on hand-offs by acquiring the synchronization codes transmitted in synchronization channels. The first synchronization channel (primary synchronization channel, hereinafter PSCH) consists of an unmodulated primary synchronization code (denoted as Cpsc) with length of 256 chips transmitted once every slot. Cpsc is the same for all base stations. This code is periodically transmitted such that it is time-aligned with the slot boundary of downlink channels as illustrated in Fig. l. The secondary synchronization channel (hereinafter SSCH) consists of a sequence of 15 unmodulated

secondary synchronization codes (Css/'o to Css/, H) repeatedly transmitted in parallel with Cpsc in the PSCH. The 15 secondary synchronization codes are sequentially transmitted once every frame. Each secondary synchronization code is chosen from a set of 16 different orthogonal codes of length 256 chips. This sequence on the SSCH corresponds to one of the 64 different code groups which the base station downlink scrambling code belongs to. The code allocation for a base station is shown in Fig. 2.

These 64 sequences are constructed such that their cyclic-shifts are unique. In other words, if the count of cyclic-shifting is 0 to 14, all 960 (=64*15) possible sequences generated by cyclic-shifting the 64 sequences are different from each other.

Base upon this property, cell search algorithms can be developed to uniquely determine both the code group and the frame timing.

During the initial cell search for the wide-band CDMA system proposed by 3GPP, a mobile station searches for the base station to which it has a lowest path loss. It then determines the

downlink scrambling code and frame synchronization of the base station. This initial cell search is typically carried out in three steps: Step 1: slot synchronization During the first step of the initial cell search procedure, the mobile station searches for the base station to which it has lowest path loss via the primary synchronization code transmitted on the PSCH. This is typically done with a single matched filter matching to the primary synchronization code.

Since the primary synchronization code is common to all the base stations, the power of the output signal of the matched filter should have peaks for each ray from each base station within a receivable range. The strongest peak corresponds to the most stable base station for linking. Detecting the position of the strongest peak yields the timing and the slot length that the strongest base station modulates. That is, this procedure causes the mobile station to acquire slot synchronization to the strongest base station.

Step 2: Frame synchronization and code-group identification During the second step of the cell search procedure, the mobile station utilizes the secondary synchronization code in the SSCH to find the frame synchronization and the code group of the cell found in the first step. Since the secondary synchronization code is transmitted in parallel with the primary synchronization code, the position of the secondary synchronization code can also be found during the first step. The received signal at the positions of the secondary synchronization code is consequently correlated with all possible secondary synchronization codes for code

identification. The 15 consecutive codes received and identified within one frame construct a received sequence. Because the cycle shifts of the 64 sequences corresponding to 64 code groups are unique, by correlating the received sequence with the 960 possible sequences, the code group for the synchronized base station as well as the frame synchronization can be determined.

Step 3: Scrambling-code identification During the last step of the cell search procedure, the mobile terminal determines the exact primary scrambling code used by the found base station. The primary scrambling code is typically identified through symbol-to-symbol correlation over the Common Pilot Channel (hereinafter CPICH) with all codes within the code group identified in the second step. After the identification of the primary scrambling code, the Primary Common Control Physical Channel (hereinafter PCCPCH) can be detected. Then the system-and cell-specific information can be read.

In sum, the main tasks of the initial cell search procedure are to (1) search for a cell with the strongest received power, (2) determine frame synchronization and code group, and (3) determine the down-link primary scrambling code.

SUMMARY OF THE INVENTION An object of the present invention is to provide a powerand cost-effective method and apparatus for frame boundary synchronization and code group identification.

The method of the present invention is used for finding a specific code group used by a base station and the frame timing synchronization with the base station. The method comprises the

following steps : (a) providing plurality of secondary synchronization code sequences (SSCSs), each SSCS having a length of L codes and corresponding to a corresponding code group; (b) sensing and sampling signals from the base station to forma reference code sequence (RCS) whose length is less than L codes; (c) comparing the RCS with all possible code sequences for finding a candidate code group and a relevant frame boundary, each of the possible code sequences generated by sampling adjacent codes of a cyclic-shifted SSCS and having a length the same with RCS's, wherein the candidate code group and the relevant frame boundary correspond to one of the possible code sequences which has the highest likelihood with the RCS; (d) appending, when the candidate code group is not unique, the RCS by adding a received code from the base station into the RCS, and repeating the step of (c); and (e) outputting, when the candidate code group is unique, the candidate code group and the relevant frame boundary for synchronizing.

The apparatus of the present invention comprises a memory, a decoder, a first sampler and plurality of processors. The memory stores plurality of secondary synchronization code sequences (SSCSs) which correspond to code groups. The decoder receives and samples signals from a base station to form an incoming sequence. The first sampler further samples several adjacent codes of the incoming sequence to form a reference code sequence. Each processor corresponds to a corresponding SSCS and comprises a second sampler and a searcher. Each processor further comprises means for cyclically shifting the corresponding SSCS to obtain cyclic-shifted code sequences. The second sampler samples adjacent codes in cyclic-shifted code sequences to form sampled code sequences, each sampled code

sequence having a code length as the first reference code sequence. The searcher compares the reference code sequence with the sampled code sequences to output likelihood values and finds the relatively-largest likelihood value and a corresponding frame boundary. The apparatus further has means for finding a candidate code group among the code groups by electing the largest likelihood value among the relativelylargest likelihood values, and outputting, when the candidate code group is unique, the candidate group code and a found frame boundary corresponding to the candidate group code, and controlling, when the candidate code group is not unique, the first sampler to sample an extra adjacent code in the incoming sequence for appending the reference code sequence.

The first advantage of the present invention is power saving. Since the reference code sequence needn't have the specific sequence length which the secondary synchronization code sequences have. For example, in 3GPP, the length of the secondary synchronization code sequence is 15. However, theoretically, the reference code sequence of length 4 is enough for frame boundary determination and code group identification by using this present invention. The operations required for correlation, comparison and calculation are consequently reduced, and the power consumption is therefore reduced.

Since the present invention is basically a parallel searcher, both the code group number identification and frame boundary determination could be achieved simultaneously. Thus, the timing required for cell search could be shortened effectively as compared to that of a sequential searcher. This is the second advantage of the present invention. The third advantage of the present invention is the ability of error

immunity. Even though several codes of the reference code sequence are not received correctly, the code group number and its relevant frame boundary can still be found exactly. It is because that the present invention utilizes likelihood characteristic instead of exactness.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention can be understood in more detail by reading the subsequent detailed description in conjunction with the examples and references made to the accompanying drawings, wherein: FIG. l illustrates the relationship of the primary and the secondary synchronization channels; FIG. 2 shows the code allocation for a base station; FIG. 3 is the generic architecture of the present invention; FIG. 4 shows the operational flow of the method of code group determination and frame synchronization according to the present invention; FIG. 5 illustrates the basic concept of algorithm for finding the most likely code sequence; FIG. 6 shows the operational flow of the searching algorithm shown in FIG. 5 ; FIG. 7 illustrates the concept of using a DSP chip to realize the searching algorithm of the present invention; FIG. 8 illustrates one possible hardware implementation using combinational logics to realize the searching algorithm for code group i ; and FIGs. 9A and 9B illustrate the implementations of the window size controllers 82 and 85, respectively, as shown in FIG. 8.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The essence of the present invention is utilizing part of the 15 consecutively-received secondary synchronization code sequence (SSCS) from a base station to correlate with all possible portions of the 64 SSCSs responding to the 64 code groups. Thus, a most-likely code group and a most-likely frame boundary can be found.

As shown in FIG. 2, the 64 SSCSs, each has a length of 15 codes, corresponding to 64 code groups are unique, as well as their cyclic-shifts. Which is the key point as the 64 SSCSs are designed. Nevertheless, after carefully observing, any consecutive secondary synchronization code sequence with a length longer than 3 codes is also unique in the table of FIG. 2.

For example, the code sequence of (1,1, 2,8) only can be found by combining the first four secondary synchronization codes of Code Group 1, and any other four consecutive codes in FIG. 2 can't construct (1,1, 2,8). Therefore, if a mobile terminal receives a consecutive code sequence of (1,1, 2, 8), it can immediately figure out the code group utilized by the base station is Code Group 1 and the frame boundary is slot #1. In other words, code group and frame boundary can be determined by a portion, not full, of the SSCS transmitted from a base station within a time frame. The present invention just utilizes this feature for code group identification and frame synchronization.

FIG. 3 is the generic architecture of the present invention. Since in 3GPP the SSC consists of 16 different code words, a correlator bank, constructed of 16 correlators 3101-3116, are used for identifying the correlation between the current input s ignal s R1 (m) and (m) with the 16 orthogonal code words CS,

CS (, ,..., CS16 slot-by-slot, wherein m denotes the sequence slot number of the received SSCs, i means in-phase, and q means quadrature-phase. Each correlator 31n (n=1-16) was followed by a correlation level bank 32n for storing the 15 correlation levels outputted by the correlator 31n during a time frame. The correlation level bank 32n further accumulates the correlation levels at the same time slot of different time frames for noise immunity. Maximum finder 34 finds the maximum output among the 16 outputs from the 16 correlation level banks 3201-3216 to output a current code number, which should be transmitted by the base station in the current time slot. After a period of N time slots, N code numbers are stored in a recorder 36 to form an incoming sequence. According to the incoming sequence, a searcher 38 can determine the code group number and the frame boundary utilized by the synchronized base station.

FIG. 4 shows the operational flow of the method of code group determination and frame synchronization according to the present invention. First of all, an incoming code sequence with a length of N codes is prepared (the symbol of 40).

Then, extract the prior N-K codes of the incoming code sequence as a reference code sequence (the symbol of 42), where in K is an integer larger than 0. In the meantime, correlators 3101-3116, correlation banks 3201-3216, maximum selector 34 and recorder still work for recognizing and recording the signals from the synchronized base station (the symbol of 44). Then, find the most likely code sequence by comparing, code-by-code, the reference code sequence with the 64 SSCSs and their cyclic shifts (the symbol of 46). If the most likely code sequence is not unique (Yes route from the symbol of 48), append the reference code sequence by extracting more P codes of the

incoming code sequence (the symbol of 50), wherein P is an integer larger than 0, and find another most likely code sequence according to the extended reference code sequence (the symbol of 52). This loop consists of appending and finding continues until the most likely code sequence is unique (No route from the symbol of 48). For avoiding an endless loop due to a low single-to-noisy ratio (SIN) environment, a limitation of loop count is inserted into the loop for jumping out of the loop. When the loop count is over a predetermined integer number A (Yes of the symbol 54), the current incoming code sequence will be abandoned and the incoming code sequence for code group identification and frame synchronization will be newly collected. Nevertheless, if the most likely code sequence is unique (No route from the symbol of 48), do L times of collecting an incoming code sequence and finding the most likely code sequence. L most likely code sequences as L candidates are generated (Yes of the symbol 56) and, by majority voting among them, a final code group and frame boundary can be determined.

FIG. 5 illustrates the basic concept of algorithm for finding the most likely code sequence. For convenience, a sliding window for each code group is used to search the most likely code sequence. The size of the sliding window is equal to that of the reference code sequence. Only the elements outlined by the sliding window are used to compare with the elements in the reference code sequence, when the window slides from slot number 0 to slot number 14 with step of one slot number.

Each step will come out with one matching result, e. g. V (i, m) indicates the match result for code group i at sliding step m. For example, set the reference code sequence being {10,15, 9, 10, 10, 2}, therefore the size of the sliding window is

6 codes. The first step for the sliding window for Code Group 1 is to enclose the first 6 secondary codes of Code Group 1 and generate a sampled code sequence of (1,1, 2,8, 9,10). The elements in the reference code sequence are all different with the corresponding elements in the sampled code sequence, thus V (1, 1) is equal to 0. The second step shifts the sliding window by one slot and generates another sampled code sequence of {1,2, 8,9, 10, 15}. There is only one element (the fifth element) in the reference code sequence the same as the element in the sampled code sequence at the same location, therefore V (1, 2) is equal to 1. And so on. There is a total of 15 results for each code group. Among these results, the maximum one, in the described example, V (l, 6), is selected, and uses the corresponding sampled code sequence as one candidate of the most likely code sequence. Every code group utilizes the same searching algorithm, and all the 64 searching algorithms execute simultaneously. Therefore, there are 64 candidates for the most likely sequence. Among them, the sampled sequence corresponding to the maximum V (k, m) is selected as the most likely code sequence. This means that the synchronized base station uses Code Group k and the frame boundary offset between the synchronized base station and the mobile station is m slots.

FIG. 6 shows the operational flow of the searching algorithm described in the previous paragraph. Since all the 64 code groups use the same searching algorithm, for convenience, Code Group i is used as an example to describe how the searching algorithm executes. When the algorithm starts, it executes the following steps: 1. Setting the value of m, which indicates the m-th sliding step (i. e. the m-th window), to be one.

2. Comparing the sampled code sequence with the reference one element-by-element until all elements are compared.

The value of V (i, m) increases by one whenever there is an element match.

3. Increasing, if m is less then 15, the value of m by one and going back to step 2.

4. If m is equal to 15, finding the maximum one among these obtained V (i, m), where m=1-15, and using the corresponding sampled code sequence as the candidate of the most likely code sequence for Code Group i.

5. Among the 64 candidates obtained from 64 code groups, again, retrieving the maximum V (k, m) and using the corresponding sampled code sequence as the most likely code sequence.

6. Stopping the algorithm.

The searching algorithm of the present invention can be realized by using techniques of digital signal processing (DSP) chip or combinational logics. FIG. 7 illustrates the concept of using a DSP chip to realize the searching algorithm of the present invention. The incoming code sequence obtained from maximum selector 34 is first recorded by using a first-infirst-out (FIFO) memory 71, and the 64 secondary synchronization code sequences corresponding to 64 code groups are recorded in a look-up table (LUT) 73. When the system is initialed, the searching algorithm program (in C or Assembly Language), the 64 SSCSs and the incoming code sequence are down-loaded into the DSP 72 simultaneously. The searching algorithm program mainly consists of 64 similar subroutines, within which every subroutine is responsible for finding the most likely code sequence of one code group. All these 64 subroutines are

executed in parallel in the DSP chip 73. According to the searching algorithm described in the previous paragraph, the DSP chip 73 will identify the desired code-group number and the desired frame boundary.

FIG. 8 illustrates one possible hardware implementation using combinational logics to realize the searching algorithm for code group i. The content of the secondary synchronization code sequence of code group i would be down-loaded from a LUT to a shift register bank 86, which is dedicated to this code group i. After maximum selector 34 outputs N code numbers to form an incoming code sequence stored in a shift register bank 81, several elements of the incoming code sequence and the secondary synchronization code sequence of code group i are sent in parallel to the shift register banks, 83 and 84, via window size controllers, 82 and 85. The window size controllers 82 and 85, are used to control the number of elements written into the shift register banks 82 and 84.

Each shift register bank (81,83, 84 and 86) consists of SN shift registers of size Be bits, where Be and SN represents the minimum number of bits for representing one element and slot number per time frame, respectively. For example, in 3GPP, SN is equal to 15 and Be is equal to 4 due to there are total 16 secondary synchronization codes. The outputs of the shift register banks 83 and 84 are sent in parallel to the element comparator 87 for comparing element-by-element. Moreover, the shift register bank 83 shifts circularly element-by-element.

Certainly, each shift register bank (81,83, 84 and 86) can be replaced by a shift register of size Be*SN bits. For such an implementation, the output bits of shift registers 83 and 84 are serially sent to the element comparator 87, and are compared for

every Be bits. When the two elements compared are equal, the output of the element comparator 87 becomes 1. The following "integrate and dump"circuits 8a are used to calculate the number of equal elements.

With the help of using the counter-SN 88, the operation of sliding window comparison as illustrating in FIG. 5 can be realized. The counter-SN 88 is used to count the number of elements that had been compared in shift register bank 84. When all the SN elements are compared, the counter-SN 88 will output a pulse to reset itself and to circularly shift one element of the shift register bank 86. Moreover, this pulse signal is also

used to trigger the"integrate and dump"circuits 8a to output the calculated likelihood value to the shift register 8b and then reset the value of the"integrate and dump"circuit 8a. At the same time, the shift register 83 also circulates back to its initial status. Next, the shifted SSCS of code group i is written into the shift register bank 84 with the same size controlled by the window size controller 85, and the sliding window comparison proceeds to the next sliding window.

Each windowed secondary synchronization code sequence has a likelihood value when it had been compared. As illustrated in shift register 8b, V (1), V (2) and V (SN) corresponding to the likelihood value of the first-, second-and SNth-sliding window, respectively. From these obtained likelihood values, maximum selection circuits select the maximum one as the candidate of the most likely code sequence for code group i. The counter-SN 89 is used to count the number of sliding windows that have been already compared. When all the SN sliding windows have been compared, it will generate a pulse to reset itself and to trigger the maximum selection circuits 8c output the selected value.

FIGs. 9A and 9B illustrate the implementations of the window size controllers 82 and 85, respectively. As shown in FIG. 8, these two components are controlled by the window size control word. The window size control word consists of SN*Be control bits, which are used to control the selection of input signals or the pre-memorized value. Different pre-memorized values are used in window size controllers 82 and 85:"1"for 82 and"0"for 85. In such a way, those output elements switched to the pre-memorized value have no contribution on the output of element comparator 87. Therefore, the sizes of the reference code sequence and the sampled code sequence are controlled.

As to the problem of which size of the reference code sequence is proper at the beginning of the system according to the invention, it depends on the experimental results.

Theoretically, the size of 4 codes is enough for code group identification. However, the larger the size of the reference code sequence at beginning, the higher the noise immunity of this invention that will be obtained.

The advantages of this invention include: 1. Power efficient : Only portions of the incoming code sequence are taken for comparison, thus the operation switches during comparison between the reference code sequence and the sampled code sequences are reduced consequently, so that the power consumption for the mobile terminal is also reduced. It is very important to reduce the power consumption during operation in a mobile terminal.

2. Error immunity: The most likely code group, not exactly the same code group, is found. Thus, in an environment of high noise, even though the reference code sequence

includes some error codes, the most likely code group and the relevant frame boundary still can be found. For example, if the reference code sequence is {1, 1,4, 8, 9}, the most likely code group and the relevant frame boundary will be found as code group 1 and slot #1, respectively, even though the 3rd element of the reference code sequence is a wrong code of"4"instead of a correct code of"2".

3. Simultaneity : The most likely code group and the relevant frame boundary are found simultaneously, not sequentially. Thus, the timing required for both code group number identification and frame boundary determination can be shortened efficiently.

Finally, while the invention has been described by way of examples and in terms of the preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims

What Is Claimed Is: 1. A method for searching a specific code group used by a base station and synchronizing with the base station, comprising the following steps: (a) providing plurality of secondary synchronization code sequences (SSCSs), each SSCS having a length of L codes and corresponding to a specific code group; (b) sensing and sampling signals from the base station to form a reference code sequence (RCS) whose length is less than L codes; (c) comparing the RCS with all possible code sequences for finding a candidate code group and a relevant frame boundary, each of the possible code sequences generated by sampling adjacent codes of a cyclic-shifted SSCS and having a length the same with RCS's, wherein the candidate code group and the relevant frame boundary correspond to one of the possible code sequences which has the highest likelihood with the RCS; (d) appending, when the candidate code group is not unique, the RCS by adding a received code from the base station into the RCS, and repeating the step of (c); and (e) outputting, when the candidate code group is unique, the candidate code group and the relevant frame boundary for synchronizing.
2. The method as claimed in claim 1, wherein cyclic-shifts of the SSCSs are unique.
3. The method as claimed in claim 1, wherein the method further comprising the following steps : (f) repeating the steps (b) to (e) for obtaining plurality of candidate code groups and plurality of relevant frame boundaries; and (g) electing, by majority voting, and outputting one of the candidate code groups as a most likely code group and one of the relevant frame boundaries as a most likely frame boundary.
4. The method as claimed in claim 1, wherein the method is executed in a digital signal processor (DSP) chip.
5. A apparatus for code group finding and frame synchronizing, comprising : a memory for storing plurality of secondary synchronization code sequences (SSCSs) which correspond to code groups; a decoder for receiving and sampling signals from a base station to form an incoming sequence; a first sampler for sampling adjacent codes of the incoming sequence to form a reference code sequence; plurality of processors, each processor corresponding to a specific SSCS and comprising: means for cyclically shifting the corresponding SSCS to obtain cyclic-shifted code sequences; a second sampler for sampling adjacent codes in cyclic shifted code sequences to form sampled code sequences, each sampled code sequence having a code length the same as the first reference code sequence; and

a searcher for comparing the reference code sequence with the sampled code sequences to output likelihood values and finding the relatively-highest likelihood value and a corresponding frame boundary ; and means for finding a candidate code group among the code groups by electing the highest likelihood value among the relatively-highest likelihood values, and outputting, when the candidate code group is unique, the candidate group code and a found frame boundary corresponding to the candidate code group, and controlling, when the candidate code group is not unique, the first sampler to sample an extra adjacent code in the incoming sequence for appending the reference code sequence.
6. The apparatus as claimed in claim 5, further comprising a selector for restarting the decoder, the first sampler and the processors, repeatedly storing the outputted most likely code groups and found frame boundaries, and outputting a final code group elected by majority voting among the outputted most likely code groups and a final frame boundary elected corresponding to the final code group.
7. The apparatus as claimed in claim 5, wherein the decoder comprises plurality of correlators, each correlator being used for correlating received signals from the base station with one of the predetermined orthogonal codes to output a correlative level per time slot.
8. The apparatus as claimed in claim 7, wherein the decoder further comprises plurality of frame-wise accumulators, each

frame-wise accumulator corresponding to a specific correlator and adding up the correlative level with a previous correlative level a time frame before to output an accumulated result.
9. The apparatus as claimed in claim 8, wherein the decoder further comprising a shift register bank constructed by plurality of shift registers, each shift register storing the accumulated result corresponding to a time slot in a time frame.
10. The apparatus as claimed in claim 8 wherein the decoder further comprises a maximum finder for finding the maximum accumulated result among the accumulated results outputted by the frame-wise accumulators to generate a corresponding code number for every time slot.
11. The apparatus as claimed in claim 10, wherein the decoder further comprises a recorder for consecutively storing outputted code numbers from the maximum finder.
12. The apparatus as claimed in claim 5, wherein the sampled code sequences are generated one by one.
13. The apparatus as claimed in claim 8, wherein the searcher comprises: a similarity comparator for comparing the reference code sequence with one of the sampled code sequences and outputting a likelihood value; and

a shift register bank for storing the likelihood value and triggering the second sampler to generate another one of the sampled code sequences.
14. The apparatus as claimed in claim 13, wherein the similarity comparator comprises: a comparator for code-by-code comparing codes at the same locations in the reference code sequence and a compared and sampled code sequence and outputting an equivalent signal if the codes are the same; and a summation unit for counting happening times of the equivalent signal.
15. A method for frame synchronization in a direct-sequence (DS) code division multi-access (CDMA) communication system, the DS-CDMA system comprising a base station periodically transmitting a specific secondary synchronization code sequence, the specific secondary synchronization code sequence belonging to one of secondary synchronization code sequences, each secondary synchronization code sequence having a length of L codes and corresponding to a code group, the method comprising: (a) sensing and sampling the specific secondary synchronization code sequence received from the base station to forma reference code sequence (RCS) whose length is less than L codes; (b) comparing the RCS with all possible code sequences for finding a candidate code group and a relevant frame boundary, each of the possible code sequences generated by sampling adjacent codes of a cyclic-shifted SSCS and having

a length the same with RCS's, wherein the candidate code group and the relevant frame boundary correspond to one of the possible code sequences which has the highest likelihood with the RCS; (c) appending, when the candidate code group is not unique, the RCS by adding a received code from the base station into the RCS, and repeating the step of (b); and (d) outputting, when the candidate code group is unique, the candidate code group and the relevant frame boundary for synchronizing.
16. The method as claimed in claim 15, wherein, the secondary synchronization code sequences are constructed such that their cyclic-shifts are unique.
17. The method as claimed in claim 15, wherein the method further comprising the following steps: (e) repeating the steps (a) to (d) for obtaining plurality of candidate code groups and plurality of relevant frame boundaries; and (f) electing, by majority voting, and outputting one of the candidate code groups as a most likely code group and one of the relevant frame boundaries as a most likely frame boundary.
18. The method as claimed in claim 15, wherein the method is executed in a digital signal processor (DSP) chip.
19. A computer readable medium or signal embodying instruction code executable to perform all steps of the method defined in any one of claims 1 to 4,15 to 17.