GB2359223A - Clock recovery where the clock is synchronised to its own output transitions when there are no input data transitions - Google Patents

Abstract

A clock recovery circuit (10) is used in synchronising a locally generated clock signal with a received data signal (BIP). The received signal conveys encoded information and timing information by changing state over a succession of regular timing periods, each state change lasting for one of plural permitted durations in terms of the timing periods. The clock recovery circuit is arranged to generate a reference signal (REF), which is used to control a local oscillator (30) via a phase-locked loop. A sequence detector identifies transitions in the local timing signal which correspond to the absence of transitions in the encoded data signal. A signal generator generates the timing reference signal REF thereby generating transitions at intervals which are more regular than in the encoded data signal itself. The circuit operates without relying on greatly over-sampling the received waveform and using digital counters. Accordingly the size and noise-emissions of the circuit are reduced compared with the prior art.

Description

2359223 DATA RECEIVING CIRCUIT AND CLOCK RECOVERY THEREIN This invention

relates to local communications networks and apparatus for clock signal recovery therein.

In local communications networks digital data may be transmitted using many different schemes. For example, one type of network is the D2B Optical system, using the CONAN C transceiver OCC 8001-1 available from Communication & Control Electronics Limited, UK, mentioned in WO 99/11024. This known example uses a bi-phase coding scheme common also to the AES/EBU 958 digital audio standard. Other alternative data coding schemes are possible for communication networks, for example various forms of Manchester coding and 413/513 coding used in ATM networks. The invention is applicable to these and other runlength limited redundant codes, with or without modification of the detailed embodiment described.

In order to decode the received data correctly, the receiver of such signals must be provided with a clock signal whose frequency and phase are synchronised with the original transmitter clock. In the coding schemes described, this clock can be extracted from the received encoded data, without sending separate clock signals. However, this clock recovery task is complex, because to convey actual data a coding scheme such as bi-phase coding includes transitions at some clock edges and not at others.

Various techniques for clock recovery are known, including digital techniques using variations on phase locked loops (PLLs). For example, one solution to the problem of performing clock recovery is to use a circuit which utilises counters to determine the current position in the waveform. The circuit first predicts where it is in the signal waveform and then detects edges and measures errors between the observed and expected timing of individual transitions. The timing information thus extracted is used to synthesise the up and down instructions for the receiver local oscillator, typically a voltage controlled oscillator (VCO), with digital frequency synthesis.

2 A known network transceiver implementing such a scheme is the CONAN 0 network transceiver for D2B Optical networks, available from Communication & Control Electronics in the UK. This system uses bi-phase encoded serial data to convey audio and control data streams via optical fibres. The same protocols may be carried on electrical twisted pair cables, as described in our co-pending application WO-A-99111024. The clock recovery circuit operates by first recognising synchronisation patterns marking a largescale frame structure, and then subdividing the frame interval into the appropriate number of clock periods. The synchronisation patterns are usually pre-arranged violations of the data coding rules, such as a long run of no transitions. The frame typically will comprise hundreds of data bits. This function of counting and predicting is performed by the use of digital counter circuits which over-samples the received waveform by a factor of ten or more.

Similarly, a known method of decoding a Manchester coded signal is discussed by Lester Sanders in an article "For Data-Comm Links, Manchester Chip Could Be Best", Electronic Design Vol. 30, pp201 - 212, August 1982. This describes a two-part approach to synchronisation, using a synchroniser operating at twelve times the clock frequency detecting signal edges and a synchronisation-pulse detector which recognises specific patterns of data.

Another method of Manchester decoding is disclosed in US 5 726 650. This uses a phaselocked loop in conjunction with an adjustable digital delay line. The delay line delays the coded signal in order to synchronise it with the local clock of the decoding apparatus.

Such schemes as described necessitate the use of large numbers of components, resulting in a large "footprint" for the circuit on chip. Such implementations will also contribute considerable noise to the receiver system and produce spurious electromagnetic radiation, especially where high clock frequencies or multiples of the base data clock rate are used.

Such problems have deleterious effects on system performance and should be minimised.

Large component numbers and high circuit frequencies also increases power consumption.

Other problems with such schemes include being specific to one particular data format. To cope with multiple formats, duplication of circuitry may be required, and/or significant design effort to adapt to other symbol tapes and frame structures.

n It is an object of the present invention to alleviate at least some of the above-mentioned problems and provide means for recovering clock signals from an encoded data stream with a smaller circuit area, and without significant oversampling. Reduced levels of cost, power consumption, noise, electromagnetic radiation contributions to the communications network and surrounding environment as a whole can be achieved.

The invention provides a method of clock recovery in a serial data communications apparatus, wherein events derived from a received encoded data stream are supplemented by events derived from a local clock signal to form a single reference signal, and wherein the phase and frequency of the local clock signal are controlled by comparing the timing of events in the reference signal with events in the local clock signal.

The invention further provides a clock recovery circuit for use in synchronising a locally generated clock signal with a received data signal, the received signal conveying encoded information and timing information by changing state over a succession of regular timing periods, each state change lasting for one of plural permitted durations in terms of said timing periods, the clock recovery circuit being arranged to generate a reference signal which incorporates both events derived from the received signal and events derived from the locally generated clock signal, the latter events being generated during states of longer duration, such that said reference signal includes events substantially at regular intervals independent of the encoded information.

The invention further provides a circuit for extracting a timing reference signal from an encoded data signal of variable run length, the circuit comprising means responsive to both a local timing signal and the encoded data signal for judging whether transitions in the local timing signal are matched within a certain tolerance by substantially simultaneous transitions in the encoded data signal, means for generating said timing reference signal so as to include first transitions generated directly in response to transitions present in the encoded data signal and second transitions generated in response to transitions in the local clock signal which are judged as unmatched, thereby to generate transitions at intervals which are more regular than in the encoded data signal itself.

4 In one embodiment, said detecting means is responsive to said local timing signal and encoded data signal in versions where the local timing signal is delayed relative to the encoded data signal, while said first and second transitions in the timing reference signal are generated in response to versions of the local timing signal and encoded data signals delayed substantially equally. This simplifies the task of detecting the unmatched events in the local timing signal, when the magnitude of the relative delay defines the window or tolerance within which the presence or absence of a matching event in the encoded data signal will be judged.

The detecting means may be arranged to operate with a state memory no longer than a symbol period of the encoded data symbols. The state memory may correspond in length only with a longest run length expected within a normal symbol set in the encoded data signal (disregarding for this purpose deliberate coding violations which are often used for signalling start-of-frame and like conditions).

The invention yet further provides a data receiving circuit comprising:

a signal input for receiving a serial data signal including a series of variably-spaced events which together encode data and convey timing information for use in decoding the data; - a local clock generator for generating a local clock signal with regularly spaced events; a data decoder for decoding the data encoded in the received signal by reference to the received signal and the local clock signal; a clock recovery circuit for comparing the relative timing of events in the received signal and the local clock signal and for controlling the local clock generator so as to maintain a desired phase and frequency relation between the local clock signal and the timing information encoded in the received signal, wherein said clock recovery circuit comprises:

a phase comparator for comparing the phase of said local clock signal with that of a reference signal derived from said received signal, events in the reference signal being spaced regularly irrespective of the data encoded in the received signal; a reference signal generator for generating said reference signal so as to incorporate both events present in the received signal and further incorporating, where no event is present in the received signal in accordance with the encoded data, additional events derived from the local clock signal.

Said reference signal generator may comprise a sequence detector arranged to initiate said additional events whenever a relevant event within said local clock signal is not preceded or followed by an event in the received signal within a predetermined delay.

Said reference signal generator may comprise:

a first delay circuit arranged to generate a delayed version of said local clock signal; - a sequence detector arranged to receive the received signal and a delayed version of local clock signal and to trigger said additional events whenever a succession of two relevant events within the delayed clock signal occur between events in the received signal; combining means for combining the additional events with events derived from the received signal, while delaying the events derived from the received signal to match the delay imposed by said first delay circuit.

Said sequence detector may comprise a plurality of individual sequence detectors, being of similar form to one another but adapted different combinations of states in the received signal and/or the local clock signal.

Said sequence detector may comprise separate individual sequence detectors operative to detect transitions during high and low states of the received signal.

Said sequence detector may comprise separate individual sequence detectors operative for local clock signals of opposite phases.

Each individual sequence detector may comprise a series of plural latch circuits, each latch having a data input, a data output, a clock input responsive to the local timing signal and a clearing input responsive to the encoded data signal, at least one latch in the series having its data input responsive to the data output of a previous latch. The clock inputs of said one latch may be responsive to the local timing signal in inverted form relative to the previous latch. In a second one of said sequence detectors, the clearing inputs may be of the latches may be 6 responsive to the encoded data signal in inverted form relative to a first sequence detector. The clock inputs of the latches may be edge- triggered, while the clearing inputs are asynchronously acting and level- responsive.

For bi-phase coded signals, two latches may be sufficient to form each series, but coding schemes permitting longer run lengths may require more than two latches to be connected in series.

In embodiments of the invention, the clock recovery circuit can be constructed to operate by sequential and combinational logic substantially without over-sampling and counting the intervals between events in the received signal. In particular, said clock recovery circuit can be constructed to operate by sequential and combinational logic with a state memory not substantially greater than the longest expected spacing of events in said received signal.

The spacing of events in said local clock signal may be substantially equal to the shortest spacing of events expected in said received signal.

The clock recovery circuit may be constructed to insert an additional event whenever in accordance with the data conveyed the spacing of events in the received signal is twice the spacing of said events in the local clock signal.

The clock recovery circuit may be constructed to insert two additional events whenever the spacing of events in the received signal is three times the spacing of said events in the local clock signal.

The received signal may be a binary signal while each said event in the received signal comprises any transition between binary states.

Relevant events in the local clock signal may comprise transitions in either direction between binary states of the local clock signal, or in specific directions only.

7 The local clock signal may be a square wave while the reference signal is a square wave generated by toggling the signal value in response to each event in the received signal and each additional event derived from the local clock signal.

These and other variations and modifications of the invention may be envisaged by the skilled reader, from the above introduction and from consideration of the detailed examples which follow.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

Figure 1 shows the major elements of a receiver embodying the present invention, for use in a local communications network; Figure 2 is a functional block diagram of a clock recovery circuit in the receiver featured in Figure 1; Figure 3 shows in more detail the circuit featured in figure 2; Figure 4 shows in yet more detail a sequence detector circuit in the circuit of figure 3; Figure 5 shows in yet more detail a phase comparator circuit in the receiver of figure 1; and Figure 6 is a timing diagram illustrating a delayed local clock signal, a bi-phase coded signal received from the network, and a recovered clock signal in the circuit of Fig 3.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Figure 1 is a block diagram of the major elements of a receiver for use in a local communications network. The circuit comprises a reference signal generator, a phase comparator 20, a local voltage controlled oscillator WO 30, and a signal decoder 40. The receiver input 50 receives a binary signal transmitted from another station in a local communications network, for example via optical fibre, wired links or radio. Encoded data signal BIP is received and input into both the reference signal generator and signal decoder 40. The data transmitted may be encoded using various coding schemes, for example bi-phase coding of the type mentioned in WO-A-99/11024. Local oscillator WO 30 inputs a version W01 of a local clock signal into the reference signal generator. The local clock signal is a baseband signal, meaning that it occupies the frequency band of the modulated signal, (or a very low multiple thereof), preselected to be as close to the known clock frequency signal of the incoming data as possible. Different versions of WO 1 and W02 etc. of the local clock signal are identical in frequency, but different in phase according to their purpose as will be apparent.

No separate clock signal is received with the bi-phase signal BIP from the transmitting station. However, reference signal generator is able to extract timing information from the original encoded signal BIP 50. The reference signal generator outputs a recovered timing reference signal REF, derived from signals BIP and WO 1 together, which is input into phase comparator 20. A version of the local clock signal W01 is also output as W02 from the reference signal generator and input into the phase comparator 20. Similarly, a reset signal RSTI is output from the reference signal generator and input into the phase comparator 20.

The phase comparator 20 produces the up and down instructions UP 100 and DOWN 110 respectively to control the local oscillator WO 30. The frequency of WO I will thus change to stay synchronised with the timing reference REF extracted from data signal BIP, tracking changes in the clock frequency of the transmitter of the encoded data to synchronise clock frequencies.

The local oscillator outputs a recovered clock signal Cl,KREC at 115 synchronously with the signals WO I and W02. The recovered clock signal CLKIZEC 115 and original encoded signal BIP from input 50 are input into a decoder circuit 40. Using the extracted timing information it is possible to decode the signal BIP in a conventional manner and output the 9 recovered data signal DATA at 120. An external initialisation signal INIT can be applied to the reference signal generator 10 as necessary, via input 130.

Figure 2 is a functional block diagram of the reference signal generator for use in the receiver featured in Figure 1. Like numerals depict like elements. In this embodiment, the circuit is divided schernatically into the following principal components:- first circuit delay 200-1; sequence detector 210; event generator 220; event detector 230; event combiner 240; and a waveform generator 250.

There are provided as seen also in Figure 1, for two inputs, the local oscillator signal WO I and the bi-phase coded signal BIP.

The local clock signal W01 is coupled to a short delay circuit 200-1, which also functions to clean the input waveform. The output of circuit delay 200-1 provides signal W02 to AND gate 260 and event detector 210. AND gate 260 provides a reset output RSTI for the phase comparator 20. The sequence detector 210 has plural outputs coupled to a first pulse event generator 220 which has outputs coupled to combiner 240.

The encoded signal BIP is supplied to sequence detector 210 and second delay circuit 200-2.

The output of delay circuit 200-2 is coupled to event detector 260. The output of is coupled to combining function 240. The output of combining function 240 is coupled to waveform generator 250. The waveform generator 250 outputs the signal REF containing timing information related to the signal BIP.

In operation, briefly summarised, the sequence detector 210 detects and indicates at its outputs different sequences of events (transitions) in the local clock signal W01 which correspond to absences of events in the encoded data. In response to these absences, event generator 220 generates "artificial" timing events. These are combined at 240 with "real" events detected in the encoded data BIP by circuit 230 to form a single, regular event stream. 30 This in turn is used at 250 to generate the reference waveform REF. The first delay circuit 200-1 allows the sequence detector a single "window" within which it can judge the absence of a "real" event in signal BIP. The second delay circuit 200-2 equalises the delay of the two signals before the different event streams are combined. When compared with the local clock in the phase comparator 20, the "real" events convey timing information for adjusting the role of the local WO 30, while the "artificial" events act as "placeholders", greatly simplifying the task of clock recovery. More detail of the circuit and its operation will now be given.

Figure 3 presents the circuit of figure 2 in greater detail showing the arrangement of individual components and connections in the present embodiment.

The operation of the circuit shall now be described with reference to the aforementioned figures.

The local oscillator signal VCO1 is input into first delay circuit 200-1. This stage serves two purposes, the first to delay the input signal and the second to "clean" the clock pulse. The phase delay is necessary in order to avoid errors in other stages of the circuit by providing a definite phase offset in the local clock signal which in normal circumstances may differ by a few per cent higher or lower than the transmitted clock signal. The signal VCO-1 60 is initially input into a phase difference generator 310-1 which outputs two signals PHI and PH2, identical to the input signal but with PH2 having a phase delay in relation to PHI. The phase difference between the signals is small, but is greater than the potential variation in the input signal frequency. The phase offset thus induced between the local oscillator clock signal and the incoming data signal is necessary for the circuit of figures 2 and 3 to function correctly. The delay within circuit 310-1 can be implemented by a simple RC circuit, by logic propagation times or other means, depending on the absolute accuracy required in the size of the "time window" mentioned above.

The phase lagged signal PH2 is then inverted and PHI and PH2 are coupled to an activeHIGH input S-R latch 320-1, a standard configuration of S-R latch. The latch provides a cleaned signal pulse train to give sharp edges with short rise and fall times which alleviates problems such as noise in the clock signal and clock skew.

The output VCOPD 330 of the delay circuit 200-1 is thus simply a slightly delayed version of the input signal VCOI 60 with sharp edges. Also the waveform in Figure 6, where dotted 11 lines represent the transitions in the clock signal before the delay. The signal WOP1) is coupled both to the input of the sequence detector 210 and as the signal W02 via a series of buffers, for delay equalisation.

The encoded data signal BIP is coupled into second delay circuit 200-2 with phase difference generator 310-2 and S-R latch 320-2 performing the same delaying function as 200-1. The encoded data signal BIP is also coupled into the timing event sequencer 210 without delay. This provides a definite phase relationship between the two signals.

The event detector 230 comprises logic gates 350-380 and, in this example, resistors as shown couple the phase delayed BIP signal BIP1) is applied to a first AND gate 350 and NOR gate 360. One of the inputs for each logic gate passes through a resistance such that a signal delay is incurred. The output of first AND gate 350 is coupled through an inverter 370 to second AND gate 380. The output of NOR gate 360 is also coupled to second AND gate 380. The resultant output BIP13 at 390 comprises a train of short pulses each corresponding to a leading or trailing edge in the phase delayed input data stream data BIP. This signal is coupled as one of three inputs into an event combiner circuit, implemented in this case simply by triple input NOR gate 240. The output of NOR gate 240 is coupled to waveforin generator 250 which outputs signal REF.

Figure 4 shows in detail the timing event sequence circuit featured in the previous illustrations and which acts as a pulse transition recognition circuit.

There are two inputs into the sequence detector, phase delayed local clock signal WOP1) 3)30 and the original coded input signal BIP 50.

There are four pairs 401 - 404 of gated latches (D-type flip-flops). For each flip-flop 410/420, when the data input D is high and the clock goes high, the latch will set and when the D input is low and the C input is high the latch will reset, ie. Q follows D when C goes high and remains so until cleared. The clear data input CD on the flip- flop is active low, setting Q = 0 immediately the construction of these flip-flops is conventional. Signals from 12 the second flip-flop 420-1 to 420-4 are combined in pairs by NOR gates 430-1 and 430-2, giving outputs 440-1 and 440-2 which are fed to the event generator 220 (Figure 3).

The pairs of flip-flops 410/420 are set up so as to produce a high input to their NOR gates only upon certain conditions. Each pair of positive edge triggered flip- flops is able to identify a different sequence of timing events. These sequences, when they occur, signify the absence of a transition in the encoded waveform BIP.

For example, pair 400-1 is composed of first flip-flop stage 410-1 and second flip-flop stage 420-1 where the first flip-flop stage 410-1 has a high constant D input and is clocked by inverted WOP1) signal and the second flip-flop stage 440 is clocked by non-inverted WOPI) 330. The signal BIP provides the clear data input CD.

Consider the situation where all flip-flops are reset (Qa-Qn are all low). The first stage 410-1 will output high at Qa on condition of there being a negative going clock edge. This high will be fed directly to input Db of the second stage 420-1, which will output a high at Qb only if RIP remains high while WOPI) goes high again. The output Qb of 400-1 thus remains low unless BIP remains high over a down-up transition sequence in WOPI) 330. If BIP goes low at any stage, however, both flip-flops will be immediately cleared to Qa = Qb = 0. The case for a high signal at Qb corresponds to a timing event determined by the phase delayed local oscillator signal WOP1) in the absence of any transition in BIP. This high signal will be approximately equivalent in position to an original timing transition clock signal at the transmitter of the coded signal BIP. This transition is absent from the coded signal BIP when the coding scheme delivers a low-low pulse sequence in accordance with the data content.

For the second flip-flop pair 400-2, the CD inputs receive signal BIP via an inverter. Therefore, the output Qd will be low unless BIP remains low over a down-up transition sequence in WOPI). In this case a high signal is provided corresponding to an original timing signal transition when the coding scheme has delivered a high-high pulse sequence.

13 In both the cases described above the timing event transition in WOP13 is a down-up transition sequence, indicated by a pair of arrows ( t) in the diagram.

The flip-flop pairs 400-3 and 400-4 similarly provide high signals Qf or Qh corresponding to timing transitions sequences when the coding scheme delivers either low- low (410-3) or high high (410-4) sequences, but for the case when the timing event transition in WOP1) is a up down transition ((t) in the diagram).

Thus the sequence detector 210 is able to identify where in a coded signal missing transitions should be located using the local clock signal as a reference. This is achieved without recourse to oversampling of the coded signal, or complex counting over many symbol periods. Using this method low EM component (EMC) levels are achieved since the sequencer runs at the same rate as the data. Previous counter based solutions to edge detection problems such as this must run at rates greater than the base data rate in order to calculate possible phase transition edge locations, thus exacerbating any EMC problems caused by the scale of such an implementation.

Outputs from the gate pairs are coupled into NOR gates 430-1 and 430-2 then inverted. The two signals possible from each timing transition case are combined for economy of the subsequent circuitry, but some pairs must be handled separately. The low- low sequence result for the down-up sequence transition is combined with the high-high sequence for the up down transition sequence, and vice versa. Each output produces signals 440-1 and 440-2.

Referring now back to Figure 3, the signals 440-1 and 440-2 are input into two identical event detectors 500-1 and 500-2 to produce a train of short pulses corresponding to the input signals. These pulse generators are similar to one half of the circuit 230, as they respond only to positive edges in the flip-flop outputs Qb, Qd, Qf, Qh.

The output of the event detectors 500-1 and 500-2 are thus pulse trains corresponding to timing events in the signal WOP1) which coincide (within a certain delay) with low-low and high-high sequences in the original coded signal BIP.

14 The signals from the event detectors 500-1 and 500-2 are coupled into NOR gate 240 with the 44real" event stream 390 obtained from circuits 200-2 and 230. The delay induced by circuit 200-2 matches the delay in signal VCOPD, so that the "real" events and those triggered by thesequence detector correspond exactly in place. The combined signal 5 10 is a pulse train with pulses derived from. two sources. There are pulses corresponding to the real transition edges of the original coded signal BIP, and thus the edges of the original timing signal used to encode the signal, and pulses corresponding to the transition edges of the local oscillator signalVCOI. Apart from any phase error which is to be corrected, these pulses are regularly spaced, irrespective of the absences of transitions in the signals BIP.

The combined signal 5 10 is input into a waveform generator implemented here as toggle flip flop 250. Since on this flip-flop D is tied to QN the flip-flop will always see the complement of the existing output at the time of the clock pulse, the clock pulse in this case being the combined signal 5 10. The Q output will carry a square wave REF at half the frequency of the input pulse train. The output of the flip-flop 250 is thus a square wave reference signal identical in form and frequency to a timing signal derived from the local oscillator WO and the original timing signal used to encode BIP.

The AND gate 260 generates the reset signal RSTI which suppresses outputs when both inputs from the signal WOP13 and toggle flip-flop 250 input Q are high. This has the effect of reducing errors due to noise. The external initialisation signal INIT is applied to a clear input of the flip-flop forming waveform generator 250. Signal INIT is asserted as necessary by dedicated control circuitry or a microprocessor (not shown), in order to ensure orderly start-up, and to accommodate both deliberate and erroneous code violations.

Figure 5 shows an example of the phase comparator 20. The phase comparator 20 comprises two positive edge triggered flip-flops 600, 610 and various logic gates. The reference signal REF is input into one flip-flop 600 and the phased delayed local oscillator signal W02 into the other flip-flop 610. The output of flip-flop 600 is high when REF goes high before W02, and this causes WO control signal UP to go high. Similarly, the output of flip-flop 610 goes high when WO is high, and this causes DOWN W0 control signal to go high. There will a variation in the UP and DOWN signals corresponding to the degree of lag or advance between the local timing signal VC02and the real timing signal present in REF. The signal RST1 90 will suppress outputs when both REF 70 and W02 80 are high. The inserted events (open circles in Figure 6) are neutral, in that they will arrive simultaneously with a local oscillator edge, and neither UP nor DOWN will go high for any significant time.

The signals UP and DOWN are input into local oscillator WO 30. These signals drive the local oscillator at a frequency determined by reference signal generator from the original input coded signal BIP. The aforementioned variations in UP and DOMN will cause the needed variation in WO frequency to match local oscillator to the original timing signal used to encode BIP. WO 30 outputs a recovered clock signal CLKREC into decoder 40. The timing inforination can now be used to decode the coded signal BIP in the decoder 40 and output the recovered data 120. W0 also outputs the recovered clock signal as a reference local clock signal WO 1.

Figure 6 is a timing diagram illustrating the relationships between a biphase coded signal BIP, phase delayed local clock signal WOPD, and a recovered clock reference signal REF. It can be seen that for where timing information is absent from the encoded signal, as during a high- high period 620 or a low-low period 630, then a timing event has been inserted. The solid circles indicate timing events obtained from the original signal, that is real timing events, and empty circles 650 indicate events synthesised from the local clock using the aforementioned circuits and methods. The "real" events contain the desired information on the phase of the transmitter clock, while the synthesised events act as "place holders" but carry no timing information except the phase of the local clock.

Those skilled in the art will appreciate that other different embodiments are possible, within the scope of the invention, and the specific embodiment described above is presented as one example only. For example, for other coding schemes it would be possible to incorporate more individual sequence detectors 400-1 etc. into the clock recovery circuit. For situations where there are longer sequences of zeros or ones in the received data signal, as in 4B/513 codes for example, each pair of flip-flops 400-1 etc. can be replaced or supplemented by a series of three, four etc. flip-flops. These can generate "artificial" events in response to updown-up sequences, up-down- up-down and so forth.

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Claims (23)

1 A data receiving method comprising:

receiving a serial data signal including a series of variably-spaced events which together encode data and convey timing information for use in decoding the data; generating a local clock signal with regularly spaced events; decoding the data encoded in the received signal by reference to the received signal and the local clock signal; comparing the relative timing of events in the received signal and the local clock signal and for controlling the local clock generator so as to maintain a desired phase and frequency relation between the local clock signal and the timing information encoded in the received signal, wherein the step of generating said local clock signal includes: comparing the phase of said local clock signal with that of a reference signal derived from said received signal, events in the reference signal being spaced regularly irrespective of the data encoded in the received signal; generating said reference signal so as to incorporate both events present in the received signal and further incorporating, where no event is present in the received signal in accordance with the encoded data, additional events derived from the local clock signal.

2. A data receiving circuit comprising:

a signal input for receiving a serial data signal including a series of variably-spaced events which together encode data and convey timing information for use in decoding the data; a local clock generator for generating a local clock signal with regularly spaced events; a data decoder for decoding the data encoded in the received signal by reference to the received signal and the local clock signal; a clock recovery circuit for comparing the relative timing of events in the received signal and the local clock signal and for controlling the local clock generator so as to maintain a desired phase and frequency relation between the local clock signal and the timing information encoded in the received signal, wherein said clock recovery circuit comprises:

17 a phase comparator for comparing the phase of said local clock signal with that of a reference signal derived from said received signal, events in the reference signal being spaced regularly irrespective of the data encoded in the received signal; a reference signal generator for generating said reference signal so as to incorporate both events present in the received signal and further incorporating, where no event is present in the received signal in accordance with the encoded data, additional events derived from the local clock signal.

3. A data receiving circuit as claimed in claim 2, said reference signal generator comprising a sequence detector arranged to initiate said additional events whenever a relevant event within said local clock signal is not preceded or followed by an event in the received signal within a predetermined delay.

4. A data receiving circuit as claimed in claim 2, said reference signal generator comprising:

first delay circuit arranged to generate a delayed version of said local clock signal; sequence detector arranged to receive the received signal and a delayed version of local clock signal and to trigger said additional events whenever a succession of two relevant events within the delayed clock signal occur between events in the received signal; combining means for combining the additional events with events derived ftom the received signal, while delaying the events derived from the received signal to match the delay imposed by said first delay circuit.

5. A data receiving circuit as claimed in claim 3 or 4 wherein said sequence detector comprises a plurality of individual sequence detectors, being of similar form but adapted different combinations of states in the received signal and/or the local clock signal.

6. A data receiving circuit as claimed in claim 3, 4 or 5 wherein said sequence detector comprises separate individual sequence detectors operative during high and low states of the received signal.

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7. A data receiving circuit as claimed in claim 3, 4, 5 or 6 wherein said sequence detector (further) comprises separate individual sequence detectors operative for local clock signals of opposite phases.

8. A data receiving circuit as claimed in any of claims 2 to 7 wherein said clock recovery circuit is constructed to operate by sequential and combinational logic substantially without over-sampling and counting periods between events in the received signal.

9. A data receiving circuit as claimed in any of claims 2 to 8 wherein said clock recovery circuit is constructed to operate by sequential and combinational logic with a state memory not substantially greater than the longest expected spacing of events in said received signal.

10. A data receiving circuit as claimed in any of claims 2 to 9 wherein the spacing of events in said local clock signal is substantially equal to the shortest spacing of events expected in said received signal.

11. A data receiving circuit as claimed in any of claims 2 to 10 wherein said clock recovery circuit is constructed to insert an additional event whenever in accordance with the data conveyed the spacing of events in the received signal is twice the spacing of said events in the local clock signal.

12. A data receiving circuit as claimed in any of claims 2 to 10 wherein said clock recovery circuit is constructed to insert two additional events whenever the spacing of events in the received signal is three times the spacing of said events in the local clock signal.

13. A data receiving circuit as claimed in any of claims 2 to 10 wherein said received signal is a binary signal and wherein each said event in the received signal comprises a transition in either direction between binary states.

14. A data receiving circuit as claimed in any of claims 2 to 13 wherein relevant events in the local clock signal comprise transitions in either direction between binary states of the local clock signal.

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15. A data receiving circuit as claimed in any of claims 2 to 14 wherein said local clock signal is a square wave and wherein said reference signal is a square wave generated by toggling the signal value in response to each event in the received signal and each additional 5 event derived from the local clock signal.

16. A method of clock recovery in a serial data communications apparatus, wherein events derived from a received encoded data stream are supplemented by events derived from a local clock signal to form a single reference signal, and wherein the phase and frequency of the local clock signal are controlled by comparing the timing of events in the reference signal with events in the local clock signal.

17. A method as claimed in claim 16, wherein the need for supplementary events is identified by reference to said local clock signal and encoded data signal in versions where the local clock signal is delayed relative to the encoded data signal, while said first and second transitions in the timing reference signal are generated in response to versions of the local timing signal and encoded data signals delayed substantially equally.

18. A method as claimed in claim 16 or 17, the method being performed with a state memory no longer than a symbol period of the encoded data symbols, the state memory corresponding in length only with a longest run length expected within a normal symbol set in the encoded data signal, disregarding deliberate coding violations.

19. A circuit for extracting a timing reference signal from an encoded data signal of variable run length, the circuit comprising means responsive to transitions in both a local timing signal and the encoded data signal for detecting transitions in the local timing signal which correspond to the absence of transitions in the encoded data signal and means for generating said timing reference signal so as to include first transitions generated in response to transitions present in the encoded data signal and second transitions generated in response to detection of said transitions, thereby to generate transitions at intervals which are more regular than in the encoded data signal itself.

19. A circuit as claimed in claim 18, said detecting means responsive to said local timing signal and encoded data signal in versions where the local timing signal is delayed relative to the encoded data signal, while said first and second transitions in the timing reference signal are generated in response to a version of the local timing signal and encoded data signals delayed substantially equally.

20. A method as claimed in claim 18 or 19, said detecting means arranged to operate with a state memory no longer than a symbol period of the encoded data symbols, the state memory corresponding in length only with a longest run length expected within a normal symbol set in the encoded data signal, disregarding deliberate coding.

21. A clock recovery circuit for use in synchronising a locally generated clock signal with a received data signal, the received signal conveying encoded information and timing information by changing state over a succession of regular timing periods, each state change lasting for one of plural permitted durations in terms of said timing periods, the clock recovery circuit arranged to generate a reference signal which incorporates both events derived from the received signal and events derived from the locally generated clock signal, the latter events generated during states of longer duration, such that said reference signal includes events substantially at regular intervals independent of the encoded information.

22. A method of clock recovery substantially as described herein with reference to Figures 1 to 6 of the accompanying drawings.

23. A circuit for clock recovery substantially as described herein with reference to Figures 1 to 6 of the accompanying drawings..