GB2358563A

GB2358563A - Bidirectional data transfer between ICs each possessing a self-oscillating clock distribution system

Info

Publication number: GB2358563A
Application number: GB0104312A
Authority: GB
Inventors: John Wood
Original assignee: Individual
Current assignee: Individual
Priority date: 1999-01-22
Filing date: 2000-01-24
Publication date: 2001-07-25
Anticipated expiration: 2020-01-24
Also published as: GB0104312D0; GB2358563B

Abstract

The self-oscillating clock distribution systems of two ICs are synchronised by coupling them together at selected points with links of selected electrical lengths. This allows data to be transferred synchronously and bidirectionally between the two ICs.

Description

2358563 ELECTRONIC CIRCUITRY

FIELD OF INVENTION

The invention relates to electronic circuitry concerning timing signals and their production and distribution; oscillators as sources of such as timing signals; and communications according to timing signals.

BACKGROUND TO INVENTION

Digital electronic data processing circuitry and systems require timing signals to synchronise data processing activities. Customarily, such timing signals include a master timing signal from which other timing signals can be derived. Such a master timing signal is commonly referred to as a'cIocW signal. It is often desirable to have a clock signal that is available in more than one phase.

An example of a two-phase clock signal is where available clock signals have a phase difference of 180-degrees as often used for dynamic logic and shift register circuitry.

An example of a four-phase clock signal is where available clock signals have successive phase differences of 90-degrees. Semiconductor integrated circuits (ICs or chips) are typical host environments, often very large scale (VLSI) chips as for microprocessors or memories.

Historically, modest operating clock frequencies up to about 50MHz were satisfied by use as off-chip quartz crystal clock oscillator with simple point-to- point on-chip clock signal distribution. Nowadays, at much higher operating frequencies, typically aiming for 30OMHz to -2 1GHz, inherent on-chip distribution problems associated with clock signal reflection a0c kew have become highly significant as binary signal widths/durations are no longer s) u -,h shorter than clock signal pulses. Natural progression of IC designs is for chips to ( orie physically bigger and functionally more complex which compounds these problems.

Clock signal generation is presently typically by frequency multiplication from o ct ip crystal clock oscillators using on-chip phase locked loop (PLL) control circuitry which o,-( Pil 's valuable chip area, consumes considerable power, and experiences problems witt gr al reflections, capacitive loading and power dissipation that effectively limit maximum ope ting frequency. Related clock signal distribution usually involves tree-4ike arrange 1E t)f operational circuitry with chains of clock signal boosting buffers at intervals. Eve s), variability of semiconductor process parameters, including in the buffers, leads to undes abb and unpredictable phase delays (skew) at different positions on the chip, thus can ad se y affect reliable synchronous operation and communication even for neighbouring arei of a chip. As a result, ICs often have to be rated and run at lower than maximum desigle -for clock rates. Indeed, IC manufacturers are even reversing long-standing trends by u of smaller chip sizes for latest ICs.

The development of ever more comprehensive 'systems-on-sil icon' chips is Dir g hampered by lack of viable provisions for reliably clocking large area high-density chips It s noteworthy that clock rates tend to be limited to less than about 1 GigaHertz despite su as Mosfet IC transistor features being capable of switching at 25 GigaHertz or more.

This invention arises basically from looking for some alternative approach that jit ast reduces areal and/or power demands of on-ch ip PLL provisions, if possible further ad IE sse s and to some useful extent resolves clock signal distribution problems.

SUMMARY OF INVENTION

One broad view or aspect of this invention resides in the concept and real isa 5 11 c f method and means for effectively integrating or synergistically combining distribuJc C f repeating pulse or cyclic signals with active means for producing and maintaining s signals. A composite electromagnetic/semiconductor structure is facilitatec t simultaneously generates and distributes timing signals, including a master clock. A sji bli said signal path exhibits endless electromagnetic continuity affording signal phase ine iol I -3of an electromagnetic wave type signal, conveniently with path- associated regenerative means.

A successful inventive rationale aspect hereof has been evolved in which time constant for repeating pulse or cyclic signals is related to and effectively defined by electrical length of said signal path in the signal distribution means. A travelling electromagnetic wave recirculating endlessly electromagnetically continuous said signal path is preferred, when its traverse time of the signal path determines said time constant.

Interestingly and quite surprisingly, this has been found to be conducive to particular inventive direct production of pulse-like cyclic signals inherently having fast rise and fall characteristics, i.e. already "square" as produced, rather than requiring resort to "squaring" action on a basic inherently substantially sinusoidal signal as hitherto conventional. Indeed, such inventive electrical length/signal traverse time-constant-defining rationale hereof leads conveniently and advantageously to said electrical length or one said signal traverse effectively first defining one unipolar half-cycle signal excursion and next, or at next said signal traverse, effectively completing definition of a full bipolar cycle comprising two opposite half-cycle e)cursions. Said electrical length thus corresponds to 180-degrees for each of two successive pulse excursions for such full bipolar cycle.

Specific inventive aspects hereof to achieve such rationale are viewed as involving signals of a travelling wave nature with the signal distribution path involved having a suitably propagating nature therefor, typically of endless transmission-line form, further with transposing effect and inverting action associated with re- circulations of desired signals.

In one specific inventive aspect hereof, desired repeating cyclic signals involve recirculatory travelling wave propagation means effectively affording rotation thereabout by a desired travelling wave and setting duration of each signal excursion, with active regenerative means that can be of switching and amplifying nature, conveniently bidirectional inverting amplifier, supplying energy requirements and setting relatively short rise and fall at ends of each signal excursion.

Suitable travelling wave propagation means with desired transposing effect relative to active inverting means is exemplified, as seen by the traversing travelling wave, by physical width twisted along its length to connect opposite sides to input and output of the inverting -4 means, say as though a Moebius band or ribbon. Indeed, an integrated circuit made M a flexible substrate could be of elongate form with said path following its length and its ands interconnected as a Moebius band or ribbon, even with functional circuitry blocks to eitl aror both sides of or straddling its travelling wave propagation feature. At least then, integral on f inverting and travelling wave propagating features of cyclic signal means hereof couIJ te o the extent of up to all its length being of continuous semiconductor inverter nature, at lea using CMOS technology.

However, for planar implementation of travelling wave propagation means, a t. 9)ic 11 transmission-line form uses spaced path-following conducting features, aforesaid N1c zbiL S twist effect being afforded by way of no more than a mutually insulated cross-over of hoEe spaced conducting features. An alternative would be use of a transmission- line irv, ing transformer in or associated with otherwise transmission-line form of the triv-:11ing propagation means.

An inventive aspect of exemplary implementation hereof uses spaced coriJactive features as trace formations each having substantially the same length and being transr osed on the way between output and input of at least one inverter feature connected to, pre fE rab y between, those conductive traces. In practice, at least where the inverter feature is oi E Aer it less than about 1% along the conductive features, there will preferably be plural iWewter features spaced along the conductive features or traces - unless this invention is ada)t 2d t:) operation as a standing wave oscillator.

Preferred inverter means is of bidirectional nature, such as a pair of opposite in i( iter s side-by-side or back-to-back; and such provision facilitates direct simultaneous produatim (if similar or substantially identical anti-phase cyclic signal components.

Particularly interesting and advantageous results available from this invention i1ne ud a timing signal provision with extremely low power consumption that can effectively be limit.d t) transmission-line and inverter action losses, i.e. to near-negligible topping-up via the ii iN erte r provision(s), and take-off to operational circuitry is readily made, e.g. by way of ight bidirectional connection paths of passive resistive and/or capacitive and/or induoiw cr transmission-line nature, or unidirectional say using diodes or inverters, etc as wi I b described in more detail.

-5 Another such available result is that, at least in principle and absent fabrication imperfections, cyclic signal provision hereof has no innate preference for either direction or rotation of travelling wave propagation, though either may be predisposed or imposed by such as prescribed spacings or other differences between or within inverter means.

Inventive proposals and aspects hereof as to pulse generators and oscillators as such include transmission-line structures using conductive metal and insulating dielectric layers in a manner compatible with IC production generally and particularly together with regenerative circuitry associated with the transmission-line as such, typically and conveniently formed below and connected by vias; required insulated cross-overs or spaced transmission-line transformer parts are likewise readily formed including such as via jump connections for the cross-overs; and resulting advantageously DC unstable interconnection of terminals of such as bidirectional inverters as the regenerative means; synchronous detection and bridge rectifier action of preferred bidirectional inverters; reinforcing sequential action of such bidirectional inverters including recycling electrical energy relative to supplies; etc.

Moreover, there are inventive aspects in interconnectionlintercoupling of timing signal generating and distribution circuitry hereof, whether by direct connection or by sharing magnetic and/or electrical fields; and doing so on a self-synchronising basis with e)dension to different frequencies particularly in odd-harmonic relationship. Intercoupling and coordinating between ICs as such and further with transferring data also have important innovative and inventive merit.

Claims

Other aspects and features of the present invention arise later in this

Description, and/or are as set out in independent and dependent Claims wording of wbich is to be taken as incorporated here too.

BRIEF DESCRIPTION OF DRAWINGS Specific exemplary implementation for the invention is now described and shown by reference to the accompanying diagrammatic dravAngs, in which Figure 1 is an outline diagram for a transmission-line structure hereof; Figure 2 shows a Moebius strip; Figure 3 is an outline circuit diagram for a travelling wave oscillator hereof, Figure 4 is another outline circuit diagram for a travelling wave oscillator hereof-, -6Figures Sa and 5b are equivalent circuits for distributed electrical models of a portior of a transmission-line hereof; Figure 6a shows idealised graphs for respective differential output waveforms hereof, 1 Figure 6b illustrates relationship between propagation delay, electrical length and ph ill 3ic A length of a transmissionA ine hereof; Figures 7(i)-7(ix) are idealised graphs illustrating the phase of signal waveforms hereof Figures 8a-8c illustrate instantaneous phasing of one waveform in a transmiss i-lina oscillator hereof; Figure 9 is a cross sectional view of part of a transmission-line on an]C; Figures 10a and 10b are outline circuit and idealised graphs fora standing wave versi(n Figure 11 is a scrap outline of a transmission-line with inverting transformer; Figure 12 shows a pair of back-to-back inverters connected across part of a transmissid inT, Figures 13a and 13b are outline and equivalent circuit diagrams of CMOS back-lc>tack inverters; Figure 14a details capacitive elements of a transmission-line together With CMOS trans s ors Figure 14b is on an equivalent circuit diagram for Figure 14a; Figure 15 shows capacitive stub connections to a transmission-line; Figure 16 shows one connection for self-synchronising transmission-line oscillators; Figures 17a-17c show other connections for self-synchronising transmissionA ine oscillatc m; Figure 18 is a diagrammatic equivalent representation for Figure 13a; Figures 1 ga and 19b show connection of four transmission-1 ine oscillators; Figure 20 and 21 show magnetically coupled self-synchronised transmission- line oscilla tc f s; Figure 22 shows three magnetically couple self-synchronised transmission- line oscillatorE; Figure 23 shows connection of self-synchronising transmission-lines oscillators of dIff. t frequencies; Figure 24 shows an example of a clock distribution network for a monolithic IQ Figure 25 shows 3D implementation for timing systems hereof, Figure 26a and 26b show examples of dual phase tap-off points; Figure 27 shows three concentrically arranged transmission-line oscillators; Figure 28a and 28b show a transmission-line having a cross-loop connection; -7Figure 29a shows a transmission-line configuration for four-phase signals; Figure 29b shows idealised resulting four-phase signal waveforms; Figure 30 shows an open-ended transmission-line connection; Figure 31 concerns co-ordinating frequency and phase for two IC's; Figure 32a concerns data transfer for frequency and phase co-ordinated IC's; Figures 32b-32e concern data latches for the system of Figure 32a; Figure 33 shows digitally selectable shunt capacitors of Mosfet type; and Figure 34 shows capacitive loading and routing data andlor power across a transmission-line. DETAILED DESCRIPTION FOR ILLUSTRATED EMBODIMENTS Known transmission-lines broadly fall into two categories in that they are either open- ended or specifically terminated either partially or fully. Transmission- lines as proposed herein are different in being neither terminated nor open-ended. They are not even unterminated as such term might be understood hitherto; and, as unterminated herein, are seen as constituting a structural aspect of invention, including by reason of affording a signal path exhibiting endless electromagnetic continuity.

Figure 1 shows such a transmission-] ine 15 as a structure that is further seen as physically endless, specifically comprising a single continuous "originating" conductor formation 17 shown forming two appropriately spaced generally parallel traces as loops 15a, 15b with a cross-over at 19 that does not involve any local electrical connection of the conductor 17. Herein, the length of the originating conductor 17 is taken as S, and corresponds to two 'laps of the transmission-] ine 15 as defined between the spaced loop traces 15a, 15b and through the cross- over 19.

This structure of the transmission-line 15 has a planar equivalence to a Moebius strip, see Figure 2, where an endless strip with a single tMst through 1800 has the remarkable topology of effectively converting a two-sided and two-edged, but twisted and ends-joined, originating strip to have only one side and one edge, see arrows endlessly tracking the centre line of the strip. From any position along the strip, return YAII be with originally left- and righthand edges reversed, inverted or transposed. The same would be true for any odd number of such twists along the length of the strip. Such a strip of conductive material would perform as required for signal paths of embodiments of this invention, and constitutes another structural aspect of invention- A fle)dble substrate would allow implementing a true Mobitis strp transmission-line structure, i.e. with graduality of twist that could be advantageous coin)arEd with planar equivalent cross-over 19. A fle)dble printed circuit board so formed and w th i:s lCs mounted is seen as a feasible proposition.

Figure 3 is a circuit diagram for a pulse generator, actually an oscillator, us n,. It e transmission-line 15 of Figure 1, specifically further having plural spaced regenerative i itth e means conveniently as bi-directional inverting switch ing/am plifying circuitry 21 corn.2.2ct between the conductive loop traces 15a, 15b. The circuitry 21 is further illustrated in ths particular embodiment as comprising two inverters 23a, 23b that are connected back-totack.

Alternatives regenerative means that rely on negative resistance, negative capacitance (it ate otherwise suitably non-linear, and regenerative (such as Gunn diodes) or are of transrr ic, E ior i line nature. It is preferred that the circuitry 21 is plural and distributed along the transit iE ioi i line 15, further preferably evenly, or substantially evenly; also in largenumberssayupt 103 or more, further preferably as many and each as small as reasonably practical.

Inverters 23a, 23b of each switching amplifier 21 will have the usual ope ativ- connections to relatively positive and negative supply rails, usually V+ and GND, respe,-t vely. Respective input/output terminals of each circuit 21 are shown connected to the transrr is sJor line 15 between the loops 15a, 15b at substantially ma)dmum spacing apart alon ft effectively single conductor 17, thus each at substantially halfway around the transrnis i ior - line 15 relative to the other.

Figure 4 is another circuit diagram for an oscillator using a transmission-line st,u Aur. hereof, but with three cross-overs 19a, 19b and 19c, thus the same Moebius stril Oike reversing/inverting/transposing property as applies in Figure 3.

The rectangular and circular shapes shown for the transmission-line 15 art fcr convenience of illustration. They can be any shape, including geometrically irregular, io long as they have a length appropriate to the desired operating frequency, i.e. so that a s onc I leaving an amplifier 21 arrives back inverted after a full 'lap' of the transmission-line, E, LE. effectively the spacing between the loops 15a,b plus the crossover 19, traversed in a tirre T) effectively defining a pulse width or half-cycle oscillation time of the operating firequenc.

-9 Advantages of evenly distributing the amplifiers 21 along the transmission-line 15 are twofold. Firstly, spreading stray capacitance effectively lumped at associated amplifiers 21 for better and easier absorbing into the transmission-line characteristic impedance Zo thus reducing and signal reflection effects and improving poor waveshape definition. Secondly, the signal amplitude determined by the supply voltages V+ and GNID VOll be more substantially constant over the entire transmission-line 15 better to compensate for losses associated with the transmission-lines dielectric and conductor materials. A continuous closed-loop transmission-line 15 with regenerative switching means 21 substantially evenly distributed and connected can closely resemble a substantially uniform structure that appears the same at any point. A good rule is for elementary capacitance and inductance (Ce and Le) associated with each regenerative switching means and forming a resonant shunt tank LC circuit to have a resonant frequency of 112piroot(LeCe) that is greater than the self sustaining oscillating frequency F (F3, F5 etc.) of the transmission-line 15.

Figure 5a is a distributed electrical equivalent circuit or model of a portion of a transmission-line 15 hereof. It shows alternate distributed resistive (R) and inductive (L) elements connected in series, i.e. Ro connected in series with IL, in turn connected in series with R2 and so on for a portion of loop 15a, and registering LO connected in series vAth R, in turn connected in series with L2 and so on for the adjacent portion of loop 15b; and distributed capacitive elements CO and Cl shown connected in parallel across the transmission-line 15 thus to the loops 15a and 15b between the resistivelinductive elements ROIL, and the inductivelresistive elements Lo/R1, respectively for Co, and between the inductivelresistive elements L,/R2 and the resistive] inductive elements R,/L2, respectively for Cl: where the identities RO=Rl=1R2, U=U=0 and CO=Cl substantially hold and the illustrated distributed RLC model extends over the wflole length of the transmission-line 15.

Although not shown, there vAll actually be a parasitic resistive element in parallel with each capacitive element C, specifically its dielectric material.

Figure 5b is a further simplified alternative distributed electrical equivalent circuit or model that ignores resistance, see replacement of those of Figure 5a by further distribution of inductive elements in series at half (L12) their value (L) in Figure 5a. This model is useful for understanding basic principles of operation of transmission-lines embodying the invention.

10- During a 'start-up' phase, i.e- after power is first applied to the amplifar3 21, oscillation will get initiated from amplification of inherent noise within the amplifiers 21 thiis begin substantially chaotically though it will quickly settle to oscillation at a fundgnlenlal frequency F, typically within nano-seconds. For each amplifier 21, respective signals rli rn S inverters 23a and 23b arrive back inverted after experiencing a propagation delay Tp a our 1d the transmission-line 15. This propagation delay Tp is a function of the inductive arid capacitive parameters of the transmission-line 15; which, as expressed in henrys per Inete (L) and in farads per metre (C) to include all capacitive loading of the transmission-line lead to a characteristic impedance Zo = SOR (LIC) and a line traverse or propagation of 1 illace velocity Pv = 1 ISQR(UC) - Reinforcement, i.e. selective amplification, of those frequen ci m. s f)r which the delay Tp is an integer sub-divisor of a half-cycle time gives rise to the (Ion iina it lowest frequency, i.e. the fundamental frequency F = 11(2-Tp), for which the sub -c i is r condition is satisfied. All other integer multiples of this frequency also satisfy this sub -c Wisor condition, but gain of the amplifiers 21 'falls off, i.e. decreases, for higher frequencies, 6 tit e transmission-line 15 Will quickly settle to fundamental oscillation at the frequency F.

The transmission-[ ine 15 has endless electromagnetic continuity, which, aloi wi:h fast switching times of preferred transistors in the inverters 23a and 23b, leads to a atkingly square wave-form containing odd harmonics of the fundamental frequency F in effa-atively reinforced oscillation. At the fundamental oscillating frequency F, including the odd hQ in rion ic frequencies, the terminals of the amplifiers 21 appear substantially unloaded, duo M tte transmission-line 15 being 'closed-loop' without any form of termination, which resul tc ve y desirably in low power dissipation and low drive requirements. The inductarx.E ard capacitance per unit length of the transmission-line 15 can be altered independently, a 3 cE n also be desirable and advantageous.

0 a Figure 6a shows idealised waveforms for a switching amplifier 21 with invertA 21 and 23b. Component oscillation waveforms (D1, (D2 appear at the inputloutput term n, lls of that amplifier 21 shortly after the 'start-up' phase, and continue during normal oplarstion.

These waveforms 01 and (D2 are substantially square and differential, i.e. two-phase n wer in being 180 degrees out-of-phase. These differential waveforms 01 and (D2 pro, s substantially at the mid-point (V+12) of the maximum signal amplitude (V+ ). This mid poi it i i i 1 1 (V+12) can be considered as a 'null' point since the instant that both the waveforms (D1 and (D2 are at the same potential, there is no displacement current flow present in nor any differential voltage between the conductive loop traces 15a and 15b. For the preferred recirculating travelling wave aspect of this invention, this null point effectively sweeps round the transmission line 15 with very fast rise and fall times and a very 'clean' square-wave form definition. This null point is also effectively a reference voltage for opposite excursions of a full cycle bipolar clock signal.

For the transmission-line 15, R is convenient to consider complete laps as traversed by a travelling wave, and also total length S of the originating conductive trace 17, both in terms of 'electrical length'. Figure 6b shows relationships between the propagation delay or traverse time (Tp), electrical length in degrees, and physical length (S) of originating conductive lineJtrace 17. For each of the out-of-phase waveforms 01 and (D2, and as seen by a travelling wave repeatedly traversing the transmission-line 15, each substantially square wave excursion corresponds to one complete lap, i.e. one traverse time Tp, and successive opposite wave excursions require two consecutive laps, i.e. two traverse times (2xTp). One lap of the transmission-line 15 thus has an 'electrical length'of 180 degrees, and two laps are required for a full 00 - 3600 bipolar signal cycle, i.e. corresponding to the full lengths of the originating conductor 17.

By way of example, an electrical length of 1800 corresponding to one lap and 112 wavelength at 1ISHz could be formed from a SOmm transmission-line having a phase velocity (Pv) that is 30% that of the speed of light (c), i.e. Pv=0.3c, or 5mm where Pv=0.03c, or 166mm in free space, i.e. where Pv-- 1 c.

Figures 7(i) - 7(ix) show waveforms (D1, (D2 through a full cycle to start of the ne)d cycle, specifically at eight equal electrical-length spacings of 45 degrees between sample positions along the conductor line or trace 17. Phase labellings are relative to Fig 7(i) which can be anywhere along the trace 17, i.e. twice round the transmission line 15, as such, and 01360-degrees for riselfall of the (D1, (D2 waveforms 15 is arbitrarily marked. Taking Figure 7(i) as time tO, Figure 7(ii) shows the waveforms (D1, (D2 at time W+(0.25Tp) after one-eighth (0.125S) traverse of total length S of the line 17, thus traverse of one-quarter of the transmission line 15, and 45-degrees of electrical length. Times W+(0. 5Tp), W+(0.75Tp), -12 W+(0.75Tp) W+(2Tp); traverses 0.25S, 0.375S, 0.5S 1.OS and 90, 135, 360-degrees should readily be seen self-evidently to apply to Figures 7(iii) 1 (b), respectively.

Figures 8a and 8b show snap-shots of excursion polarity (shown cir 1 ed), displacement current flow (shown by light on-trace arrows), and instantaneous phasir g roi n an arbitrary 01360-degree position on the electromagnetically endless transmission if 15 covering two laps thereof (thus the full length the continuous originating conductor 17). nly one differential travelling electromagnetic (EM) waveform (say (D1) of Figure 7 is shoivr, but for rotation propagation around the transmission-line 15 in either of opposite directioi, Le.

clockwise or counter-dockwise. The other waveform (02) will, of course be 1800 t & phase with the illustrated waveform (01). The actual direction of rotation of the EM w A wi 1 be given by Poyntings' vector, i.e. the cross product of the electric and magnetic vectof s Th crossover region 19 produces no significant perturbation of the signals (D1 or (D2 as tid C4 wave traverses this region 19. In effect, the fast riselfall transitions travel rourd th? transmission-] ine at phase velocity Pv, the switching amplifiers 21 serving to amp] f th transitions during first switching between supply voltage levels.

The phases of the waveforms (D1 and (1Q can, for a transmission-line 15 her(C b, accurately determined from any arbitrary reference point on the transmissionline l,',, US have strong coherence and stability of phasing.

Suitable (indeed preferred in relation to present IC manufacturing technology rid practice) switching amplifiers 21 for bidirectional operation are based on back-to-back 1A6 fet inverters 23a,b, for which up to well over 1,000 switching inverting amplifier pairs c+ tx provided along typical lengths of transmission-line structures hereof.

The bidirectional inverting action of the switching amplifiers 21 is of synctir:)[u rectification nature. The rise and fall times of the waveforms (D1 and (D2 are very fast l i( compared with hitherto conventional timing signals, being based on electron-transit-tirr o U preferred Mosfet transistors of the inverters 23a,b. Moreover, reinforcement is related tc E 0 transmission-line 15 having lower impedance than any'on' transistor in inverters of prefE ec bidirectional switching amplifiers 21, though total paralleled is usefully of the same oi er Switching of such inverters means that each amplifier 21 contributes to the resulting v vE 1 1 1 1 - 13 polarity by way of a small energy pulse which, by symmetry, must propagate in both directions, the forwardly directed EM wave pulse thus contributing as desired. The reverse EM wave pulse that travels back to the previously switched amplifier 21 is of the same polarity as already exists there, thus reinforces the pre-existing switched state. Ohmic paths between power supply rails and the transmission line 15 through 'on' transistors of the preferred inverters of amplifiers 21 ensure that energy of such reverse EM wave pulses is absorbed into those power supply rails V+,GND, i.e. there is useful power conservation.

It should be appreciated that implementation could be by other than CMOS, e.g. by using N-channel pull-ups, P-channel pull-downs, bipolar transistors, negative resistance devices such as Gunn diodes, Mesfet, etc Regarding the transmission-lines 15 as such, a suitable medium readily applicable to ICs and PCBs and interconnects generally is as commonly referred to as microstrip or coplanar waveguide or stripline, and well known to be formable lithographically, i.e. by patterning of resists and etching. Practical dielectrics for an on-IC transmission-line include silicon dioxide (Si02) often referred to as field oxide, inter-metal dielectrics, and substrate dielectrics (which can be used at least for semi-insulating structures, e. g. of silicon-on insulator type).

Figure 9 is a cross-section through a portion of one exemplary on-IC transmission line formation comprising three metal layers 56, 58 and 60 and two dielectric layers 62 and 64. Middle metal layer 58 is illustrated as comprising the two transmission-line loop conductive traces 15a and 15b that are at least nominally parallel. Upper metal layer 60 could be used as an AC 'ground' plane and could be connected to the positive supply voltage V+, lower metal 56 being a 'ground' plane that could be connected to the negative supply voltage GND. The dielectric layers 62 and 64 between the metal transmission-line traces at 58 and 'ground' planes 56 and 58 are typically formed using silicon dioxide (SiO2). The full illustrated structure is seen as preferable, though maybe not essential in practice, i.e. as to inclusion of either or both of the'ground' planes and the dielectric layers 62, 64. The physical spacing 66 between the conductive traces 15a, 15b affects the differential and common modes of signal propagation, which should preferably have equal, or substantially equal, velocities in order to achieve minimum dispersion of the electromagnetic field from the -14 spacing 66. Screening properties improve with use of 'ground planes', as does the abi ily f)r the structure to drive non-sym metrical, i.e. unbalanced, loads applied to the conductive racks 15a, 15b. 1 Inter-metal dielectric layers on a.typical IC CMOS process are thin, typically boit 0.7pm, so microstrip transmission-line features with low signal losses must have 1 kw characteristic impedance Zo (as hitherto for unterminated, partially terminated ot aries terminated lines acting to reduce signal reflections to a manageable level). Self-sustAllin g, non-terminated, closed-loop transmission-lines 15 hereof inherently have very low) r consumption for maintained travelling EM wave oscillation as the dielectric and cox uctor losses to be overcome are typically low. From Figure 5b, it will be appreciated that, W thei e were no resistive losses associated with the transmissionA ine 15 and amplifiers 7, tte transmission-line 15 would require no more energy than required initially to 'charge- u) tl e transmission-lines inductive Le and capacitive Ce elements. The EM wave would corth via y travel around the transmission-line with all energy in the transmission- line 1,15 E impy transferred, or recycled between its electric and magnetic fields, thus capacitive CE ard inductive Le elements. Whilst there must be some resistive losses associated wit 1 tte transmissionA ine 15 and amplifiers 21, see transmission-line resistive elements RD- R2 n Figure 5a, the resistance is typically low and associated resistive losses will be a& low.

There is no penalty herein from for using low-impedance transmissionlines 15, evEn advantage from being less affected by capacitive loading, thus resulting in 'stiffer dri we 1 o logic gates. i A crossover 19 can be implemented on an IC using Vas' between the metal IC rer preferably with each via only a small fraction of total length S of the transmissionA ine 1 5.

A variant is available where a transmission-line 15 hereof has only one amplifi:r 1 connected to the transmission-line, and the EM wave no longer travels aroux tte transmission-line 15 so that a standing wave oscillation results, see Figure 10a for, ing amplifier 21 and Figure 1 Ob for differential waveforms. Such amplifier should not e)d(,.i c wer more than approArnately 50 of the electrical length of the transmission- line 15. If the, ing e amplifier 21 never goes fully 'on' or 'off a standing sine wave oscillation will result i th e - 15transmission-line 15, which will have varying amplitude with the same phases at the same positions including two stationary, two'null regions.

It follows that travelling wave operation will be available using a few spaced or just one lengthy CIVIOS bidirectional inverter formation, though plural small inverters will produce smoother faster results. Offsetting formations of the amplifiers 21, even just its inputtoutput terminals, can predispose a travelling EM wave to one direction of transmission-line traversal, as could specific starter circuit such as based on forcing first and slightly later second pulses onto the transmission-line at different positions, or incorporation of some known microwave directional coupler.

Inverting transmission-line transformers can be used instead of the crossovers (19) and still yield a transmission line having endless electromagnetic continuity, see Figure 11 for scrap detail at 21 T.

Figure 12 shows a pair of back-to-back inverters 23a, 23b with supply line connectors and indications of distributed inductive (L/2) and capacitive (C) elements of a transmission line as per Figure 5b. Figure 13a shows N-channel and P-channel Mosfet implementation of the back-to-back inverters 14a and 14b, see out of NMOS and PMOS transistors.

Figure 13b shows an equivalent circuit diagram for NMOS (N1, N2) and PMOS (P1, P2) transistors, together with their parasitic capacitances. The gate terminals of transistors P1 and NI are connected to the conductive trace 15a and to the drain terminals of transistors P2 and N2. Similarly, the gate terminals of transistors P2 and N2 are connected to the conductive trace 15b and to the drain terminals of transistors P2 and N2. The PMOS gate-source capacitances CgsP1 and CgsP2, the PMOS gate-drain capacitances CgdP1 and CgdP2, and the PMOS drain-source and substrate capacitances CdbP1 and CdbP2, also the NMOS gate source capacitances CgsN1 and CgsN2, the NIVIOS gate-drain capacitances CgdN1 and CgdN2, and the NIVIOS drain-source and substrate capacitances CdbN1 and CdbN2 are effectively absorbed into the characteristic impedance Zo of the transmission-line, so have much less effect upon transit times of the individual NMOS and PMOS transistors. The rise and fall times of the waveforms 01 and 02 are thus much faster than for prior circuits.

For clarity Figures 12-14 omit related resistive (R) elements. Figure 23a shows only the capacitive elements (as per Figures 12 and 13b) of the transmission- line 15 together with 16those of the N/PMOS transistors. Figure 14b illustrates another equivalent circuit diagrE m f)r Figure 14a including the transmission- line distributed inductive (U2) elements arif fte effective capacitance Ceff given by:

Ceff = C + CgdN + CgdP + [(CgsN + CdbN + CgsP + CdbP)! 4; Where: CgdN= CgdN1+ CgdN2; CgdP= CgdPI+ CgdP2; CgsN = CgsN1 + CgsN2; CdbN= CdbN1+ CdbN2; CgsP = CgsP1 + CgsP2; and CdbP= CdbP1+ CdbP2.

Capacitance loading due to gate, drain, source and substrate junction capacitancL-,, ar a preferably distributed as mentioned previously.

An advantage of having a differential- and common-mode, transmission-line, ic that Oparasitic' capacitances inherent within mosfet transistors can be absorbed intc thD transmission-line impedance Zo, as illustrated in Figures 14a and 14b, and can thereloi e b D used for energy transfer and storage. The gate-source capacitances (Cgs) of the NMCX,I and PMOS transistors appear between the signal conductor traces 15a, 15b and their resl >E C tiv, supply voltage rails and can be compensated for by removing the appropriate amou It respective capacitance from connections of the transmission-line 15 to the supply vo tagi rails, say by thinning the conductor traces 15a, 15b by an appropriate amount. The! 1 late - drain capacitance (Cgd) of the NMOS and PMOS transistors appear betvieen the con(lu",tiva traces 15a and 1 5b and can be compensated for by proportionally increasing the spac in J 615 between the conductive traces 15a, 15b at connections to the NMOS and PMOS transinors of the inverters 23a/b.

By way of a non-restrictive example, on a 0.35 micron CMOS process, a utable 5GHz non-overlapping clock signal should result with transmission-line loop length (VE) of 9mm for a phase velocity of 30% of speed-of-light, as determined by capacitive shunt 1()z C in distribution and dielectric constants, the total length (S), of the conductor 17 thus It e inc 18mm.

i I -17 The substrate junction capacitances (Cdb) of the NMOS and PMOS transistor could be dramatically reduced by using semi-insulating or silicon-on-insulator type process technologies.

There is a continuous DC path that directly connects the terminals of each of the amplifiers 21, i.e. the respective inputloutput terminals of each and all of the inverters 23a, 23b, but this path is characterised by having no stable DC operating point. This DC instability is advantageous in relation to the regenerative action of each of the respective amplifiers 21 214 and their positive feedback action. Transmission-lines 15 hereof can be routed around functional logic blocks

as closed loops that are 'tapped into' to get 'local' clock signals. CMOS inverters can be used as 'tap amplifiers' in a capacitive'stub to the transmission-line 15, which can be 'resonated out by removing an equivalent amount of 'local' capacitance from the transmission-1 ines, say by local thinning of conductor traces (15a115b) as above. Capacitive 'clock taps' can be spread substantially evenly along a transmission-line,15 hereof having due regard as a matter of design to their spacings, which, if less than the wavelength of the oscillating signal, will tend to slow the propagation of the EM wave and lower the characteristic impedance Zo of the transmission-line (15), but will still result in good signal transmission characteristics.

Within functional logic blocks that are small relative to clock signal wavelength, unterminated interconnects work adequately for local clocking with phase coherence, see Figure 15. For clarity, the pairs of connections to the transmission-line 15 are shown slightly offset though they would typically be opposite each other in practice. Alternative tap-off provisions include light bidirectional of passive resistive, inductive or transmissionA ine nature, or unidirectional or inverting connections, including much as for what will now be described for interconnecting transmission-lines 15 themselves.

Plural oscillators and transmission-lines 15 can readily be operatively connected or coupled together in an also inventive manner, including synchronising with each other both in terms of phase and frequency provided that any nominal frequency mismatch is not too great.

Resistive, capacitive, inductive or correct length direct transmissionline connections/ couplings, or any combinations thereof, can make good bidirectional signal interconnections.

Signal connection or coupling between transmission-lines can also be achieved using known coupling techniques as used for microwave micro-strip circuits, generally involving sh 3r ng Df magnetic andior electrical flux between adjacent transmission lines. Unidireffloral connections can also be advantageous. Connectors and couplings hereof are ca a Ae Df maintaining synchronicity and coherency of plural transmission-line oscillators throu!)t out a large system, whether within ICs or between IC's say on printed circuit boards (PC13s) Connection/coupling of two or more transmission-lines and cross- connecticri are similar to KirchofFs current law but based on the energy going into a junction, i.e. a connection or coupling, of any number of the transmission-lines being equal to the e ier(1 y coming out of the same junction, i.e. there is no energy accumulation at the junction. 1 MlhE n the supply voltage V+ is constant, the rule is, of curse, precisely Kirchoff s current law. B r w iy of a practical example, if there is a junction common to three transmission-lines, the si Ti p,fec t, but not the only, solution is that one of the transmission-lines has half the chara..tlh'istc impedance of the other two transmission-lines. Where there are any even number of do ipi transmission-lines, their respective characteristic impedances can all be equal. Flov eve r, there are an infinite number of combinations of impedances which will satisfy Kh ioff s current law. The cross-connection rule, within a transmission-line, is the same as the nil, xs for coupling two or more transmission-lines described above.

There will be high quality differential signal waveforms (D1 and (D2, in terms ol F haE e and amplitude, at all points around a transmission-line network 15 when the following c iter a are met:

(i) the transmission-lines have substantially matching electrical lengths (ii) above Kirchoff-like power rules are satisfied (iii) there is phase inversion.

There are, of course, an infinite number of coupled network designs and supply voltage th t will fulfil the above three criteria, such as for example: short sections of slow, low impec c-.,inc a transmission-lines that are coupled to long fast, high impedance transmissionA ines; arid one andlor three-dimensional structures etc. However, for the best waveshapes and lowest parasitic power losses, the phase velocities of the common-mode and the differential -n iode, i.e. even and odd modes, should be substantially the same. The same, or substantiiiii the _19 same, phase velocities can be designed into a system by varying the capacitances of the transmission-lines.

The supply voltage V+ does not have to be constant throughout a system, provided that above Kirchoff-like power/impedance relationships are maintained and result in an inherent voltage transformation system that, when combined with the inherent synchronous rectification of the inverters 23a and 23b, allows different parts of the system to operate at different supply voltages, and power to be passed bi-directionally between such different parts of the system.

Figure 16 shows two substantially identical transmission-line oscillators hereof that are operatively connected such that they are substantially self- synchronising with respect to frequency and phase. The transmission-lines 15, and 152 are shown 'siamesed' with the common part of their loop conductive traces meeting above Kirchoff-like powerlimpedance rule by reason of its impedance being half the impedances (20) of the remainders of the transmission-lines 15, and 152, because the common parts carry rotating wave energy of both of the two transmission-lines 15, and 152. As noted above, the originating trace length S of a transmission-line is one factor in determining the frequency of oscillation so transmission-lines 15, and 152 using the same medium and of substantially identical length S will have substantially the same frequency of oscillation F and will be substantially phase coherent. In Figure 10, respective EM waves will travel and re-circulate in opposite directions around the transmission-lines 15, and 152, see marked arrows 1L, 2L (or both opposite), in a manner analogous to cog wheels. Such siamesing connection of transmission-lines can readily be extended sequentially to any number of such 'cogged' transmission-line oscillators.

Figure 17a shows another example of two substantially identical transmission-line oscillators with their transmission lines 15, and 152 operatively connected to be substantially self-synchronising in frequency and phase by direct connections at two discrete positions 40 and 42. Figure 17b shows such direct connections via passive elements 44, 46 that could be resistive, capacitive or inductive or any viable combination thereof. Figure 17c shows such direct connections via unidirectional means 48 that can be two inverters 50, and 502. The unidirectional means 48 ensures that there is no coupling or signal reflection from one of the transmission-lines (152) back into the other (151), i.e. only the other way about. Directions of travel of re-circulating EM waves are again indicated by arrows 1L, 21--- that are s 1 bit arbitrary for transmission-line oscillator 151 and dashed for 152 in accordan E with expectations as to a 'parallel'-coupled pair of transmission-lines yielding contra-dir ( oral travelling waves. Figure 18 is a convenient simplified representation of the Nt sef synchronised transmission-iine oscillators of Figure 17a, and similar representations i H 1 e used in follovAng Figures.

Figure 19a shows four self-synchronised transmission-line oscillators 1. 151 ' 1:54 connected together basically as for Figures 17a - 17c, but so as further to afford a cen fd th effective transmission-line timing signal source of this invention affording a re-cir U to y travelling EM wave according to indicated EM wave lapping directions 1 L - 41---of t i fo ir transmission-line oscillators 15, - 154. As shown the central fifth transmission-line o i at r physically comprises parts of each of the other four, and has a lapping direction 5L t 1 t S opposite to theirs, specifically clockwise for counter-clockwise 1 L - 4L. It will be appr a i tE d that this way of connecting transmission-line oscillators together can also be extende t) ar y desired number and any desired variety of overall pattern to cover any desired area.

An alternative is shown in Figure 19b where the central fifth transmiss lin a oscillator is not of re-circulating type, but is nonetheless useful and could be advantag a S to access to desired phases of timing signals.

Figure 20 shows two self-synchronising oscillators with their transmission-li, 1 and 152 not physically connected together, rather operatively coupled magnetically; fol ic h purpose it can be advantageous to use elongated transmission-iines to achieve m a J better magnetic coupling. Figure 21 shows another example of magnetically coup] IL synchronising oscillators with transmission-lines 151 and 152 generally as for Figure, bLt with an coupling enhancing ferromagnetic strip 52 operatively placed between adjace ri S to be magnetically coupled.

Figure 22 shows three self-synchronising oscillators with their transmission-lin S 5, 152 and 153 magnetically coupled by a first ferrous strip 62 placed between transmissio - nes 151 and 152 and a second ferrous strip 54 placed between transmission-lines 152 and 51 A> a source of oscillating signals, the transmission-line 152 does not need any rege r ive provisions 21 so long as enough energy for oscillation is magnetically coupled from th hE r -21 transmission-lines 151 and 153 that are complete with provisions 21. It is considered practical for the transmission-line 152 to be longer and circumscribe a larger area but not to need or have regenerative provisions 21, nor a cross-over 19; and is then preferably an odd multiple (3S, 5S, 7S etc) of the length (S) or at least the electrical length of at least one of the transmission-lines 151 and 153. This, of course, has further implications for self-synchronising frequency- and phase-locking of oscillators (say as using transmission- lines 151 and 153), at a considerable spacing apart.

Further alternatives include use of a dielectric material (not illustrated) that spans over andlor under the portions of the conductive traces to be electromagnetically coupled.

It is feasible and practical to synchronise transmission-line oscillators operating at different frequencies. In Figure 24, transmission-lines of two self- synchronising oscillators are of different electrical lengths. Specifically, using same transmission- line structurelmaterials, first transmission-line 151 has a total conductive length S for a fundamental oscillating frequency F=Fl and is operatively connected and synchronised to a second transmission-line 152 having a total conductive length that is one third of that of the first transmission-line 151, i.e. S13, thus an oscillating frequency of 3F. The dashed lines with arrows indicate the direction of rotation of the EM waves. Operative connection is as for Figures 17a - c, though any other technique could be used. Self-synchronising is due to above- mentioned presence in the highly square first transmission-line signal of a strong third harmonic (3F). Similar results are available for higher odd harmonics, i.e. at frequencies of 5F, 717 etc.

Preferred coupling between transmission-lines of oscillators operating at such different odd harmonic related frequencies, is unidirectional so that the naturally lower frequency line (151) is not encouraged to try to synchronise to the naturally higher frequency line (152). Any number of transmission-line oscillators of different odd-harmonically related frequencies can be coupled together and synchronised as for Figure 24.

Re-circulatory transmission-line oscillators hereof can be used in and for the generation and distribution of reference, i.e. clock, timing signal(s) in and of a semiconductor integrated circuit (IC); and is also applicable to a printed-circuit- board (PCB), e.g. as serving to mount and interconnect circuitry that may include plural ICs, or indeed, any other suitable apparatusisystem where timing reference signal(s) isfare required.

For ICs as such, simulations using the industry standard SPICE techniquqs, ,,how potential for supplying clock signals of very high frequencies indeed, up -to several t( ps of GHz, depending upon the IC manufacturing process employed and projections fx their development. Generation and distribution can effectively be at, and service, all parts of an I C with predictable phases at and phase relationships between such parts, including as in Atiple clock signals that may have the same or different frequencies. Moreover, principl:! s:)f operation of transmission-line oscillators hereof and their self- synchronising inter-coi ipling extend or lead readily not only to reliable service of timing signals to operational civuit-y within any particular IC and between ICs, but further and it is believed also importar tl F ar d inventively to data transfer between ICs etc.

The entire transmission-line 15 structure and network involving regenerative c.ui:s 21 oscillates. The transmission-line 15 operates unterminated, i.e. the transmission-line)rrr s aclosed-loop. The characteristic impedance Zo of the transmission-line is low and orlitopup'energy is required to maintain oscillation.

Impedance between the two conductor traces 15a, 15b is preferably eoeny distributed, thus well balanced, which helps achieve well defined, differential cignliil waveforms (01, 02). Coherent oscillation occurs when the signals 01, 02 or the transmission-line 15 meet this 180(', or substantially a 1800, phase shift requirement f)r all inverting amplifiers 21 connected to the transmission-line 15 i.e. when all the amplif e; 21 operate in a co-ordinated manner with known phase relationship between all points alon thB transmission-line 15. Signal energy is transmitted into the transmission4 ine 15)oti inductively and capacitively, i.e. magnetically and electrically, between the signal condu',fors 15a, 15b for the differential-mode, also between each signal conductor and the gmunj reference for the two individual common-mode (not present if the upper and lower ' rounc I' planes are absent, nor for connections via unshielded twisted-pair cables).

CMOS inverters as non-linear, operative switching and amplifying circuit elert ent5 have low losses from cross-conduction current as normally lossy transistor gate 'inplit' and drain 'output' capacitances are absorbed into the characteristic impedance Zo A the transmission-line 15, along with the transistor substrate capacitances, so power consu -n)tio i is not subject to the usual 1/2.CV2 formula.

It is quite often assumed that the power dissipation due to capacitive charging and discharging of MOS transistor gates, for example, is unavoidable. However, the self sustaining oscillating nature of the transmission-line 15 is able to 'drive' the transistor gate terminals with low power loss. This is due to the fact that the required 'drive' energy is alternating between the electrostatic field, i.e. the capacitive field of the MOS gate capacitances, and the magnetic field, i.e. the inductive field elements of the transmission-line 15. Therefore, the energy contained within the transmission-line 15 is not being completely dissipated, it is in fact being recycled. Energy saving applies to all operatively connected transistor gates of the transmission-line 15.

It is envisaged that low loss efficiency of transmission-line oscillator hereof could well be used to 'clock' ICs for many previously popular logic systems that have since been overshadowed or abandoned as non-viable options for reasons attributed to problems associated with clock skew, clock distribution, power consumption etc. Non-exhaustive examples of such logic arrangements include poly-phase logic and charge recovery or adiabatic switching logic, such logic arrangements being known to those skilled in the art.

Figure 24 shows a possible clock distribution network hereof as applied to a monolithic IC 68 (not to scale, as is other Figures hereof). The IC 68 has a plural transmission-lines hereof shown as loops 1 L-1 X, of which loops 1 L-1 OL and 13L all have the same effective lengths (say as for S above) and oscillate at a frequency F, and loops 11 L and 12L each have shorter loop lengths (say as for S/3 above) and oscillate at a frequency 3F. Loops 1L-8L and 11L-13L are full transmission-line oscillator complete with regenerative means, and loops 9L and 1 OL arise as parts of four of the former transmission-lines, namely 1 L, 3L, 4L and 5L; 4L, 5L, 6L and 8L respectively.

The transmission-line (15) of the loop 13L is elongated with a long side close to the edge (i.e. scribe line) of the IC 68, so that it is possible to couple to another similarly set up separate monolithic IC for inter-coupling by such as flip-chip technology for frequency and phase locking by such as magnetic coupling, as described above. Phase and frequency locking of separate monolithic IC's can be very useful in such as hybrid systems.

Figure 25 indicates feasibility of a three-dimensional network of interconnected transmission line oscillators hereof for signal distribution, specifically for a simple pyramidal arrangement, though any other structure could be serviced as desired, no matIL-i hcw complex so long as interconnect rules hereof are met regarding electrical length, impe I nte matching, any phasing requirements for data transfer, etc.

ICs hereof can be designed to have whatever may be desired up to total freq 1 n y and phase locking, also phase coherence, including for and between two or mD-e sef sustaining transmission-line oscillators greatly to facilitate synchronous control and oge - tic n of data processing activities at and between all the various logic and processing I: I cl:s associated with such IC.

Figure 26a shows an example of dual phase tap-off using a pair of CMOS inve e -s 70, and 702 connected to the transmission-line conductive traces 15a and 15b respect v y provide local clock to and/or to be distributed about a logic block 721. Whilst the logii,, oc k 72, is shown as being 'enclosed' within the transmission-line 15 alternatives include it irg outside any area enclosed by the transmission-line 15, as for the logic block 722 ar ils associated inverters 703, 704, and/or it spanning the conductive traces 15a, 15b c th a transmission line 15. If desired, say for large logic blocks 72, and/or 722 plural pal" of inverters 70 can 'tap' into the transmission-line 15, including for any desired phasing r e e J locally in the logic block 72, see dashed line. Capability accurately to select the phase th a oscillating clock signals 01, (D2 allows complex pipeline logic and poly- phase loo Figure 29 below) to be operatively designed and controlled.

Figure 26b differs in that the logic blocks 711, 722 are replaced by respective processing elements 731, 732, though there could be more, and for which one or more transmission-lines can be used to clock one or more of the processing elements. Two r greater plurality of processing elements can operate independently and/or together, i.e. I n parallel to achieve very fast and powerftjl data processing ICS/systems.

Figure 27a shows concentrically arranged transmission-lines 151-153 of progress 11 less physical lengths. However, each of the three transmission-lines 151- 153 can be m4id s( that they all oscillate at the same frequency, whether as a matter of structure or by respei M 55, velocities of the EM viraves rotating around each of the shorter transmission-lines 152 a11C being suitably retarded by increasing their inductance and/or capacitance per unit ler th Moreover, the transmission-lines 151-153 can optionally have one or more op NE -25connections 70 and 72 that will serve to synchronise the three transmissionA ines 151-153. The advantages, apart from synchronicity, of having these connections 70, 72 are that the transmission-lines 151-153 Will or can (i) act as a single multi-filament transmission-line; (ii) have smaller conductive traces (1 5a, 15b); (iii) cover a larger clocking area; (iv) produce lower skin effect losses; and (v) produce lower crosstalk and coupling.

Figure 28a shows a transmission-line having a cross-loop connection between positions A, B, C and D, which comprises further transmission-line 15c, 15d that has, in this particular example, an electrical length of 900 to match spacing of the positions A, B and Q D.

Other cross-connection electrical length could be chosen, then operatively connected at correspondingly different spacings of the positions A, B and C, D. Cross- loop connections allow further tap-off positions within area enclosed by the transmissionA ine 15. The transmission-line part 15d is shown connected in parallel, between points A and C, and part of the transmission-line 15 represented by line 74. Likewise, the transmission-line part 15c is shown connected in parallel, between points B and D, with part of the transmission-line 15 represented by line 76. The transmission-line parts 15c, 15d, 74 and 76 will be satisfactory if they each have an impedance that is half that associated with the remainder of the transmission-line 15, as above. The transmissionA ines 15 and 15c,d will have operatively connected amplifiers 21. Figure 28b shows the cross-loop connection 15c,d and the posftions A, B, C and D set up relative to parts 78 and 80 of the transmission-line 15, i.e. instead of parts 74 and 76, respectively; but with Kirchoff-type rules applying again to result in parts 15c, 15d, 78 and 80 each having an impedance of half that associated with the remainder of the transmission-line 15. Introduction of plural additional transmission- lines such as 15c,d across a transmission-line 15 is feasible as required.

Figure 29a shows one way to produce four-phase clock signals. Effectively, a transmission-line 15 makes a double traverse of its signal carrying boundary, shown as rectangular, and further repeated traverses could produce yet more phases. In the example shown, the positions Al, A2, B1 and B2 All yield localised four-phase clock signals, as will the positions Cl, C2, D1, and D2. The repeated boundary traverses will be with i i ab e mutual spacing/separation of the transmission-line 15 to avoid inter-coupling. Fig ri Z lb shows idealised four-phase signal waveforms at points Al, A2, Bl and B2 and at Cl, C ' 1,1 1 and D2. i 1 Figure 30 shows addition of an open-ended passive transmission-line (1te Elf) connected to the closed-loop transmission-line 15 and having the characteristics, of hav' n electrical length of 180% of producing no adverse effect at the tap point, since it ac E n open-circuit oscillating stub. Amplifiers 21 will not be present along this open-ended Ii e 5a,f but inverters 23 could be far ends of each of the traces 15c and 15d to reduce risk of s t 104s oscillations. Indeed, turned oscillation in such stubs 15e,f can have useful regene ffi e effects for the transmission-line 15 and thus serve for reinforcement andlor stability pulp) 4.

Passive transmission-line connections with no particular requirement for imp 1 nae matching can be used to connect oscillating transmission-lines of the same, or sub a 1 ially the same, frequency together, at least provided that enough inter- connections are est bl hE d between two systems, at connection positions with the same relative phases in th i Wconnected networks. Such connections can assist in synchronising high speed digital S na s between IC's and systems because non-clock signals (i.e. the IC/system data lines) 'It ae similar delay characteristics if they are incorporated into the same routing (e.g. ribbo A bl, twisted pair, transmission-line) as the clock connections, thus making data and]C kir g coherent between different systems.

Figure 31 shows one example of coherent frequency and phase operation ( tWo clock distribution networks of two monolithic ICs 681, 682 each having a clock genera o i ar d distribution hereof and pairs of inter-IC connections E, F and G, H. The two ICs cor c h nE d will operate coherently, i.e. at the same frequency and with the same phase relations ip;, where each of the connections is substantially of 180-degrees electrical lengths, or a i Upe satisfying 3600.n + 18011 where n is zero or an integer.

A single pair of inter-IC connections (E, F or G, H) will result in frequency an I'aE e 'locking'. More than one pair of inter-IC connections (IE, F and G, H as shown wi 1 st It further in clock wave direction or rotation locking.

-27 Also shown in Figure 31 is a first and second 'stub' connections 82 and 83, though there could be more of either or each. The first stub connection 82 has a total electrical length of 1800 to assist in stabilising operation. The second stub connection 83 is open ended and also of 1800 electrical length and helpful for stabilisation. Such stubs 82, 83 can be particularly useful for non-IC applications of the invention where conductive trace definition may be less precise than for ICs.

Impedance of the pairs of connections E, F and G, H and connections 82, 83 can have any value since, in normal operation and once these connections are energised, there will be no net power flow therein for correct phasing thereof. It is, however, preferred that the impedance of these connections E, F and G, H and 82, 83 is greater than that of oscillator transmission-lines 15 to which they are connected. These connections will support a standing EM wave rather than a travelling EM wave.

Such Figure 31 inter-connections can be applied equally well to intra-IC, inter-IC, IC to-PC13 andlor any non-IC, i.e. PC13-to-PC13 system connections.

Figure 32a shows two interconnected monolithic IC's 681, 682 that are phase and rotation locked and that further have a plurality of bidirectional data latches 84 and links 86 between them inventively affording separate data processing system connection to act as one coherent structure as to phasing and further as to data transfer. Interconnection positions on the transmission-lines 15 concerned here substantially, a 1800 phase difference between ends J, K of each line inter-]C connection, though there is usually a tolerance of at least 10. The plurality of inter-IC connections 86 can be of 'twisted pair' nature connected between corresponding transmission- lines 15 of both IC's 681, 682. Impedances of these inter-IC connections 86 are again preferably higher than that associated with the clock generation transmission-lines 15.

It is not necessary for there to be equal numbers of clock/phase and data connections. Moreover, the data and clock transmission mediums 86 are of the same length and electrically matched, so both exhibit the same propagation delays, which is advantageous. The nominal 1800 phase difference represents a half clock cycle, i.e. Tp, so a data pulse transmitted from either]C to the other by the rising edge of the clock waveform (D 1, will be received during, or just after, the rising edge of the clock waveform (D2.

-28 Figure 32b shows the preferred inventive data latch 84 of Figure 32a as a blcxk. T e data latch 84 is edge triggered by the differential clock signals (D1 and (D2 for trans. S. n (TX) and receiving (RX); and has differential bidirectional inputloutput lines, dat3 pulte control lines labelled TX Data and RX Data, and the clock signal waveforms 01, (D2.

Techniques hereof greatly facilitate communicating data latches 84 on differer t K's 681, 682 being clocked with the same relative phasing. Moreover, Figure 32a indicates tt at respective communicating pairs of latches 84 are triggered on different phases, which r su ts in wholly advantageous multi-phase data transfer that eliminates need for simul. a wous switching of the transmission-lines 86, thus results in reduction of 'ground boun(A atid positive supply voltage dips.

In half duplex data transfer wherein, two data bits are transferred, one ea( h way, during each clock cycle. For data transfer (TX) from one IC to the other, and for loc a loc ic control where (D1=1, 02=0 and logic l=V+ and logic O=GND, the corresponding latchqs 19 t each IC both transmit a single bit of data for the period where (D1=1, one data bit goiiS fro iiIC 681 to]C 682, and another data bit going from IC 682 to]C 681 in each half cycle. '], i( da A signals pass each other on the transmission-line 86, and do not interfere in the Nfis e 1 p ir nature of the transmissionA ine 86. The last received data signal is usable in this half ccl p. When (D1 and (D2 are 1800 from going high and low, respectively, data is received ar ttie local logic states are (D1=0, 02=1. The same latches 84 at each of the two IC's nom bo:h receive a single bit of data that was sent during the previous half cycle, when 02=1.

Figure 32c shows a circuit to implement the data latch 84. Transistors P1, N 1, R5 and N5 are operatively arranged and controlled to produce the differential output signal, ar d 4 are only active, i.e. switched 'on', when 01=1. Either P1 and N5 turn on for a xtithe differential output signal, or P5 and N1 turn on for a negative differential output E&Ell. 25 Transistors N4, P4, N8 and P8 are operatively arranged and controlled to allow trams P1, N1, P5 and N5 to switch 'on' only when (D1=1, i.e. during the transmit time. Trailq.,,,to's P2, N2, P6 and N6 are operatively arranged and controlled to switch 'off the c utp it transistors P1, N1, P5 and N5 when (D2=1, i.e. during the receive time.

Transistor N3 is operatively arranged and controlled by the TX Data control sk;rii for 30 its associated differential bidirectional output to go positive, i.e. V+, via transistors N4 ar cl P 1, 1 1 i 1 i i 1 1 when the TX Data control signal is a logic 1. Transistor P3 is operatively arranged and controlled by the TX Data control signal for its associated differential bidirectional output to go negative, i.e. GND, via transistors P4 and N1, when the TX Data control signal is a logic 0. The inverter 11 is operatively arranged and controlled such that it produces the inverse logic 5 state of the TX Data control signal.

Transistor N7 is operatively arranged and controlled by the TX Data control signal for its associated differential bidirectional output to go positive, Via transistors N8 and P5, when the TX Data control signal is a logic 0. Transistor P7 is operatively arranged and controlled by the TX Data control signal for its associated differential bidirectional output to go negative, via transistors P8 and N5, when the TX Data control signal is a logic 1.

Transistor N13 is operatively arranged and controlled to terminate the differential transmission-line 86 correctly during the receipt (RX) of a data signal. Transistor T13 has an operative "on-resistance" that approAmately equals the characteristic impedance of the transmission-line 86.

Transistors N1-8 and P1-8 together with inverter 11 constitute the transmit circuitry TX1 of the bidirectional latch 84.

Transistors N9 and N10 are operatively arranged and controlled to 'sample' for a whole half cycle, onto capacitor Cl, the differential signal during the receipt (RX) of a data signal. Transistors N 11 and N 12 are operatively arranged and control led to switch the stored charge sample of capacitor Cl onto the operatively arranged and controlled differential-tosingle ended converter. This differential-to- single ended converter is made up by the operatively arranged and controlled inverters 12,13 and capacitor C2. Inverter 13 and capacitor C3 are operatively arranged as a voltage reference and inverter 12 is operatively arranged and controlled such that it acts as a single ended logic output bufferiamplifier for the sampled received (RXd) data signal.

Transistors N9M l and inverters 12 and 13 together with capacitors Cl and C2 constitute the receiving circuitry RX1 of the bidirectional latch 84.

The following is a truth table that summarises the operation of the data latch 84 during the transmit (T) and receipt (RX) of data signals.

TX Data xl)l (D2 +ve Differential Output -ve Differentio. 1 0 put 0 0 1 Hi-Z (receiving) Hi-Z (receiv rig) 0 1 0 0 1 0 1 Hi-Z (receiving) Hi-Z (receiv rig) 1 1 0 1 0 -- i It is noted that, for data link transmission-lines 86 with (3600.n + 1800) electrical length the-.e is an additional n cycle latency (delay), but subsequent data is received once pe -ycla.

Furthermore, the phasing could be slightly different from different 1800 for TX and RX,cii duh ry within the 1/0 data latch 84 circuit so as to improve the timing and therefore'hold times' I,tc an the data latches 84 and therefore compensate somewhat for swiftching delays.

The circuit diagram illustrated in Figure 32c does not include additional wave-;h - ph g circuitry that may well be required in practice, but could be of well- known nature.

With clean differential waveshapes, package inductance problems are mi iini since GND and V+ package connection currents do not arise through the output swithing action of the transmission-lines 86 since, the return currents are via the opposite signal)f the differential pair and not through the supply pins. The matching of the package impedar ce..o the transmission-lines 86 is therefore easier.

Figure 32d shows an intra-contiected IC having plural unidirectional recel ar d transmit data latches, see 85 and 87. A first pair of unidirectional transmit and receive le b,,hes 871, 85, are operatively connected to two different transmission-lines for operEtively transmitting data from one transmission-line to the other. The first receive latch 85r ps a delay correction through placement of 450: where 450 represents the electrical Imilth A respective clock signal connections to the latches 871, 851.

Two pairs of unidirectional transmittreceive latches 852, 872 and 853, 873 013i,r, i n the same manner as 87, and 85, except that their delay correction through placement s approximately 100, which represents the electrical length of their clock signal connection:.

Figure 32e shows unidirectional transmit and receive latches 85, 87 able to t -a r sn A and receive two bits of data per clock cycle if these latches 87, 85 respectively com pi is tM o -31 co-phase transmit or receive circuits respectively TX1 and RX1, as opposed to each having a transmit and receive circuitry TX1 and RXI.

Figure 33 illustrates digitally selectable shunt capacitors that are formed out of mosfet transistors.

Digitally selectable shunt capacitors illustrated in Figure 33 can be operatively connected to the transmission-line 15 and controlled for the travelling EM wave to be delayed slightly, i.e. the frequency of oscillation can be controlled. Such delays are useful for fine tuning the frequency of a transmission-line(s). As shown, eight shunt capacitors are implemented by means of mosfet transistors. The mosfets transistors M1, M2, M5 and M6 are PMOS transistors and mosfet transistors M3, M4, M7 and M8 are NMOS transistors.

The mosfets M1, M3, M5 and M7 have their drain and source terminals connected to the'innee transmission-line conductor 1 5a, for example, and the mosfets, M2, M4, M6 and M8 have their drain and source terminals connected to the 'outer' transmission-line conductor 15b. The substrate terminals of mosfets M1, M2, M5 and M6 are connected to the positive supply rail V+ and the substrate terminals of mosfets M3, M4, M7 and M8 are connected to the negative supply rail GND.

The gate terminals of mosfets MI and M2 are connected together and controlled by a control signal CSO and the gate terminals of mosfets M3 and M4 are connected together and controlled by the inverse of control signal CSO. Likewise, the gate terminals of mosfets M5 and M6 are connected together and controlled by a control signal CS1 and the gate terminals of mosfets M7 and M8 are connected together and controlled by the inverse of control signal CS1.

The following truth table illustrates which mosfet shunt capacitors (MlM8) contribute capacitance, i.e. 'Mosfets On', to the transmission-line 15.

CS0 CSI Mosfets 'On' Mosfets'Off 0 0 M11-1V18 0 1 M11-M4 M5-M8 1 0 M5-M8 M1-1V14 1 1 M11-M8 It is preferred that the respective sizes and numbers of shunt capacitors connec:ed o the 'inner" and 'outer' transmission-line conductive traces 15a, 15b are the sarld, i..

balanced. Whilst eight mosfet shunt capacitors M1 -M8 are shown, any number of n iosi et shunt capacitors having suitable sizes, and hence capacitances, can be used, provice I that the transmission-line 15 is balanced, as per Figure 33.

There are other configurations for producing digitally controllable shunt cal)z dito -s that, may or may not be formed using mosfet transistors. One known example, aga 11 Usir ig mosfets, could be the use of binary weighted mosfet capacitors for example. Nternatites 'o MOS capacitors affording variable capacitance include varactors and P/N diodes for e) a 11ple.

It can be advantageous for the 'capacitor arrays' to be replicated at regular int rvals around the transmission-line(s) so as to distribute the impedance.

Figure 34 shows how to route data and/or power across a transmission-line 1 1 ar d for altering its capacitive loading by way of. formations 88 resembling railway s e pe -s deposited, preferably at regular intervals below the conductive traces 15a, 1 5b. Alterr a i vel V, formations such as 88 could be deposited above and/or below the transmissio I lines conductive traces 15a, 15b. As can be seen from the cross sectional view, the trace. 15 a, I 5b are preferably on a metal layer that is isolated from the formation 88 e.g. by a c H icc in dioxide 92 layer. These formations 88 have the effect of increasing the transmission - inds capacitance and can therefore be used to alter the transmission-line impedance thus, de velocity of the travelling EM wave. These formations 88 can also be used to rou:e da a and/or power 99. One advantage of routing data and/or power 99, as il I ustrated, is thi it s Jnde the clock signals (D 1, 02 on the transmission-line 15 are differential, these clock sign 315 (D 1, 02 have no effect upon the routed data and/or power signals.

The bi-directional switches (21) using inverters 23a, 23b inherently a(I as synchronous rectifiers of the clock frequency as can be deduced by the ohmic pail h fro -n these inverters most negative supply rail to GND and their most positive supply rail t V i-.

Therefore, the NMOS and PMOS transistors that constitute the back-to-back inverters 2,: a and 23b (see Figure 22b) will always be switched by an incident EM wave oi i tt e transmission-line 15 to a state where the two 'on' transistors (an NMOS and FIACS -33respectively) will connect the most negative transmission-line conductive trace to the local GNID supply for an NMOS transistor and the local V+ supply for a PMOS transistor. The two NMOSIPMOS pairs of transistors alternate as the incident EM wave signal polarity reverses for oscillation in the manner of bridge rectification that is synchronous and exemplifies the bidirectionality of the DC-AC-DC conversion mode involved. The transmission-line 15 is thus able to extract and redirect power bi-directionally to supply power to the transmission-line 15 when the local supply rail voltage is greater than the transmission-line voltage and to remove power when the local supply rail voltage is less than the transmission-line voltage, and the transmission-line 15 acts as a power conductor in this mode, see following table:

Inputs PMOS on, NMOS 'on' PINMIDS'off 15a=i3ND P1 (15b connected to local W) N2 (15a connected to local GNID) N1, P2 15b--V+ 15a=V+ P2 (15a connected to local W) N1 (15b connected to local GNID) N2, P1 15b=GNID This power recycling is particularly appropriate to IC process technologies where the gate length is less than approximately 0.1 microns when the parallel 'on- resistance' will be comparable to the series DC resistance of the supply connections. Such synchronous rectification can act as the basis of power distribution in the absence or impossibility of power supply routing to certain area's of an IC, particularly can be used for 'charge pump' circuitry, i.e. DC-to-DC power conversion. There is also inherent capability for converting DC-to AC power conversion and visa versa. Nternatively, of course, known 'on-chip' transformers could be employed.

The possibility is envisaged of achieving highest possible operating frequencies consistent with disconnectable switching of logic circuitry, including as semiconductor fabrication technology is bound to develop.

Indeed, transmission-line formations themselves should scale with IC process technology, thus smaller and faster transistor formations lead naturally to shorter and faster transmission-line oscillators for yet higher clock frequencies.

Other possibilities include maintaining low power consumption; regardless of applications, which could be as to any resonating of capacitive and inductive connections to a -34transmission-line, and specifically use relative to such as shift regisbA r 1 prechargeTevaluate' logic.

Whilst there is evident advantage in not having to use external timing refereng Suah as a quartz crystal, nor PLIL techniques, there may be situations and applications wh ai 4 tt is 5 invention is applied in conjunction with such external timing crystals etc.

Whilst detailing herein has been within the context of currently dominant ( lAC S technology for ICs, it will be appreciated by those skilled in the art that principles are ii ii alved that are also applicable to other semiconductor technologies, e.g. Silicon-Germanium (S M G4), GalliumArsenide (Ga-As) etc.

Finally, highly beneficial particular utility in overcoming the problems associated with high frequency clocking, e.g. where F>IGHz, no other applicability of combined timing gn a] generation and distribution is to be excluded from intended scope hereof, say for systern 9 ai id apparatus to operate at frequencies less than 1 GHz.

CLAIMS 1. Electronic circuitry comprising operational circuits of active switching nature requiring timing signals, and conductive means for distributing said timing signals to the operational circuits, wherein the timing signal distribution means includes a signal path exhibiting endless electromagnetic continuity affording signal phase inversion and having associated regenerative active means so as to serve as source of said timing signals.
2. Electronic circuitry according to claim 1, comprising a semiconductor integrated circuit having an active area with features presenting the operational circuits and the timing signal distribution means, including the signal path and its associated regenerative active means together serving as the source of said timing signals.
3. Semiconductor integrated electronic circuit comprising operational circuitry of active switching nature requiring timing signals, and conductive means for distributing said timing signals to the operational circuitry, wherein part of the timing signal distribution means is a signal path exhibiting endless electromagnetic continuity affording signal phase inversion and having associated regenerative active means so as to serve as source of said timing signals.
4. Electronic circuit/circuitry according to any preceding claim, wherein the regenerative active means has switching action relative to two supply voltage levels.
5. Electronic circuit/circuitry according to claim 4, wherein the regenerative active means has amplifying action during said switching.
6. Electronic circuiticircuitry according to any preceding claim, wflerein the regenerative active means has inverting action relative to said timing signals in the signal path.
7. Electronic circuiticircuitry according to any preceding claim, wherein the regenerative active mean is of bidirecflonal nature so that said timing signal will have bipolar differential components available anywhere along the signal path at 1800 out-of phase.
8. Electronic circuitry arranged and adapted to operate substantially as herein des,.r with reference to and as shown in Figures 34a - 34e of the accompanying draw n

8. Electronic circuitfcircuitry according to claim 7, wherein the signal path makes more than one loop in its endless electromagnetic continuity so that said timing signal is -36 available in poly-phase components including quadrature for one additional I Op Df the same sense.

9. Electronic circuit/circuitry according to any preceding claim, wherein the rege if ratr fe active means is physically localised to one position along length of the signal p:h i;o that said timing signal will be of standing wave nature.

10. Electronic circuit/circuitry according to claim 9 with claim 7, wherein the bidirec t on al active means never reaches fully "on" or fully "off' states so that said standing ye timing signal is substantially sinusoidal.

11. Electronic circuiticircuitry according to any preceding claim, wherein the regeqE We active means is physically distributed along length of the signal path so tha sad timing signal will be of recirculating travelling wave nature.

12. Electronic circuit/circuitry according to claim 11, wherein the regenerative Ah e means comprises plural inverting amplifiers spaced along the signal path.

13. Electronic circuit/circuitry according to claim 12 with claim 7, wherein the bidirk nsl switching means reaches fully "on" and fully "off' states in relatively short Pa of time taken for said travelling wave timing signal to traverse the signal path th it such timing signal is substantially rectangular.

14. Electronic circuit/circuitry according to claim 11, 12 or 13, wherein the distril ted regenerative active means has inpuVoutput terminals connected across the, i 3n. kl path affording endless electromagnetic continuity of DC interconnection o tha terminals with no stable DC operating point.

15. Electronic pulse generator circuit comprising a signal path exhibiting qn J es a electromagnetic continuity affording signal phase inversion in setting pulse d j i tio i within time of signal traversal of the signal path which has associated regen 91 tiv active means setting relatively short pulse rise and fall times at ends of eac signal traversal.

16. Travelling wave electronic oscillator circuit comprising recirculatory travelling v propagation means affording a closed signal path itself imposing phase invers ic fc r each travelling wave circulation, and regenerative active bidirectional switchit g n i -37 amplifying means operative during each circulation so that opposite voltage excursions result for successive travelling wave circulations.

17. Electronic circuit/circuitry according to any preceding claim, wherein the signal path is of transmission-line nature and said timing signal is of transverse electromagnetic wave form.

18. Electronic circuit/circuitry according to any preceding claim, wherein the regenerative means serves to top up low energy losses from low impedance of electromagnetically endless said signal path.

19. Electronic circuit/circuitry according to any preceding claim, wherein the signal path is of transmission-line nature and includes transmission-line transformer means affording said phase inversion.

20. Electronic circuitIcircuitry according to any preceding claim, wherein the signal path is of transmission-line nature comprising spaced generally parallel conductive formations on a substrate with cross-over connection of the conductor formabons affording single endless conductive length.

21. Electronic circuiticircuitry according to claim 20, wherein the transmission-line signal path is a structure of co-planar microstrip/microstrip nature.

22. Electronic circuit/circuitry according to claim 21, wherein the transmission-line structure comprises spaced conductive traces sandwiched by dielectric layers and affording differential-mode said timing signals.

23. Electronic circuitIcircuitry according to claim 22, wherein the dielectric layers are sandwiched by conductive layers affording shielding and/or enabling common-mode said timing signals.

24. Electronic circuit/circuitry according to claim 22 or claim 23, wherein capacitive and/or inductive reactance of the transmission-line signal path is determined by particular geometry of the conductive traces and their spacing along their lengths.

25. Electronic circuiticircuitry according to claim 24, wherein the geometry is locally varied as may be required to accommodate reactance of connections to the traces.

-38 26. Electronic circuit/circuitry according to any one of claims 19 to 25, wherein the ign A path has an electrical length of substantially 180-degrees and the regerelatke means is of bidirectional inverting switching and amplifying nature.

27. Electronic circuit/circuitry according to claim 26, wherein the regenerative n ear s comprises back-to-back inverters.

28. Electronic circuit/circuitry according to claim 27, wherein the inverters are P.-C h inn, A and N-channel Mosfet circuits.

29. Electronic circuit/circuitry according to claim 28, wherein the inverters EWitch sequentially in one direction around the signal path and are connected to sipply voltage I ines for passage thereto of energy received from next inverter switcl i ii ig s o as to reinforce recirculating traversal of the signal path by said timing signal 30. Electronic circuit/circuitry according to any preceding claim, wherein the signal Dal h has an cross-connection also active for said tim ing signals and of an electrical li, igl of substantially half that of the signal path.

31. Electronic circuit/circuitry according to any preceding claim, wherein the sign 31 pal h has extent affording physical adjacency to the operational circuits and close ele( tric; il connectivity therefor directly to the signal path.

32. Electronic circuitIcircuitry according to claim 31, comprising electrical connect c is 1:) the signal path for the supply of the timing signals to the operational circuits, wh Aher of light bidirectional nature through passive resistive or capacitive or inductive I xath s or of unidirectional nature through diodes or inverters, or of transmission line 1 I urf or otherwise.

33. Electronic circuit/circuitry according to claim 32 with claim 26, wherei th a connections are by way of capacitive stubs from the transmission-line signal pa 34. Electronic circuit/circuitry according to claim 33, wherein the capacitive stub arB spaced evenly along the transmission-line signal path. 1 35. Electronic circuit/circuitry according to claim 32 with claim 28, wherei4 tha connections are by way of Mosfet inverters.

36. Electronic circuit/circuitry according to any preceding claim, comprising more thal one said signal path.

-39 37. Electronic circuit/circuitry according to claim 36, wherein at least two said signal paths are intercoupled to operate synchronously by sharing of magnetic and/or electric fields.

38. Electronic circuit/circuitry according to claim 36, wherein two said signal paths have a part that is common to both with an impedance substantially half that of remainders of the two signal paths.

39. Electronic circuit/circuitry according to claim 36, wherein at least two said signal paths are interconnected to operate synchronously.

40. Electronic circuit/circuitry according to claim 39, wherein selfsynchronising interconnection between said signal paths intended to operate at substantially the same frequency is via passive circuit means affording light bidirectional coupling.

41. Electronic circuit/circuitry according to claim 40, wherein selfsynchronising interconnection between said signal paths intended to operate at different frequencies having odd harmonic relation is Via inverter means poled against the higher frequency affecting the lower frequency.

42. Electronic circuitIcircuitry according to claim 39, 40 or 41, wherein interconnected said signal paths have impedances to assure substantial match of energy into and out of interconnection concerned.

43. Electronic circuit/circuitry according to any one of claims 39 to 42, wherein interconnection or intercoupling is to both of spaced conductors of the signal path at matching positions along electrical lengths of their loops relative to means for imposing phase inversion on said signals timing.

44. Electronic circuit/circuitry according to claim 41 or claim 42, wherein plural said signal paths are interconnected directly at mutual electrical lengths of matching multiples of 45-degrees.

45. Electronic circuit/circuitry according to claims 40 to 44, wherein the signal paths are one within another and have parameter differences to harmonise time of traverse by their said timing signals, thus their fundamental frequencies.

46. Electronic circuittcircuitry according to claim 44 or 45, wherein, considering operational circuits served as in an area corresponding to a nominally rectangular -40 grid array, signal paths correspond with areas along rows and columns o' said rectangular grid that alternate with intervening areas also serviceable for sQ p) ying the timing signals.

47. Electronic circuit/circuitry according to any one of claims 36 to 46, wherein A east one said signal path is connected to another or to an array thereof by way of al east one transmission-line connection having an electrical length nominally of 180-c e]re(!s or an odd multiple so as substantially to secure frequency end phase lock.

48. Electronic circuit/circuitry according to claim 47 with claim 11, wherein Wre sad transmission-line connections serve substantially to secure desired lock of direA on f signal path traversing by the respective timing signals.

49. Electronic circuit/circuitry according to any one of claims 11 to 48 with ck ir 1 1 wherein at least one connection made to a said signal path is of short- circuit rtuie with an electrical length of substantially 90-degrees.

50. Electronic circuit/circuitry according to any one of claims 11 to 49 with clz ir 1 1 wherein at least one connection made to a said signal path is of open- circuit n -. tur a with an electrical length of substantially 180-degrees.

51. Electronic circuitry comprising at least two semiconductor integrated circuit; ICA) each in accordance with any preceding claim for similar said timing signals, a IC - inter-connection between the signal paths of each of the ICs over an electrical 1(.,iigt i and at positions of the signal paths to coordinate frequency and phase cohert n:e (if one of the ICs with the other of the ICs.

52. Electronic circuitry according to claim 51, wherein the IC interconnection 1 t;E E a electrical length substantially the same as that of the signal length paths or, r od J multiple thereof.

53. Electronic circuitry according to claim 51 or 52, wherein the interconnected saii positions in one and the other of the ICs have a phase difference correspondi ig t) the electrical length of their said signal paths.

54. Electronic circuitry according to claim 51, 52 or 53, wherein a second different se 10, inter-connection serves further to prescribe directions of travelling said timing sil ilia] 3 along their said signal paths.

55. Electronic circuitry according to claim 54, further comprising bidirectional data transfer means at each IC further co-ordinated with the coordinated timing signals.

56. Electronic circuitry according to claim 55, wherein the data transfer means comprises bidirectional data latches controlled by two-phase differential bipolar said coordinated timing signals so as each to transmit a data bit to the other during the same half cycle of the timing signals and both to receive those data bits in the ne)d half cycle of the timing signals.

57. Electronic circuitry according to claim 56, comprising twisted pair said connections.

AI,,lC-wbf7,o CLAIMS W9V6 U-61v FfL-E-D AS 1. Electronic circuitry having two circuitry parts each having timing signal generatng ard distribution means using signal path provisions exhibiting endless electrom 3 et c continuity affording signal phase inversion with associated regenerative active rr r s so as to serve as source of said timing signals, further comprising inter- con i( tic n between the signal path provisions of each of the circuitry parts over an EAux ic; 31 length and at positions of the signal path provisions to coordinate mutual frE%li ncy and phase coherence of the circuitry parts, and bidirectional data transfer rnea c it eachcircuitry part further co-ordinated with the coordinated timing signals.

2. Electronic circuitry according to claim 1, wherein the interconnection has an ek x t ic 1 length substantially the same as those of the of the signal path provisions or. ar 1-4 multiple thereof.

3. Electronic circuitry according to claim 1 or claim 2, wherein the interconnected i 1 positions in one and the other of the circuitry parts have a phase differ c, corresponding to the electrical length of their said signal paths.

4. Electronic circuitry according to claim 1, 2 or 3, wherein a second different c itr part inter-connection serves further to prescribe directions of travelling said ti: inll signals along their said signal paths.

5. Electronic circuitry according to any preceding cJaim wherein the circuitry parts a ef different ICs.

6. Electronic circuitry according to any preceding claim, wherein the data transfer. in, n comprises bidirectional data latches controlled by two-phase differential bipoiz r ic coordinated timing signals so as each to transmit a data bit to the other clurimg N same half cycle of the timing signals and both to receive those data bits in thf ex half cycle of the timing signals.

7. Electronic circuitry according to claim 6, comprising twisted pair said connection 3.