GB2233479A

GB2233479A - Regulated DC-DC power supply

Info

Publication number: GB2233479A
Application number: GB9014431A
Authority: GB
Inventors: Gerhardt Bakker; Seamus Daly
Original assignee: Digital Equipment International Ltd
Current assignee: Compaq Computer Holding Ltd
Priority date: 1989-06-30
Filing date: 1990-06-28
Publication date: 1991-01-09
Anticipated expiration: 2010-06-28
Also published as: GB9014431D0; GB8915128D0; GB2233479B

Abstract

A supply voltage Vbulk is connected to the primary PRIM of a transformer T3 of a DC-to-DC converter via primary switches Q3-Q4-D8-D9. Primary control PWM turn on Q3 and Q4 with on pulses of constant repetition frequency and width controlled by the difference of Vref1 and the output voltage of low pass filter FLTR so as to keep the output constant. A secondary winding SEC 1 feeds rectifying and smoothing circuit L4-C50 via a magnetic amplifier L3, functioning as a saturable reactor, which is set by secondary control (Fig. 3) at the end of the on time and so blocks the secondary output as it resets at the beginning of the next on time. The secondary control sets the width of the blocking signal RESET as the time from the start of a ramp of slope determined by the supply voltage Vbulk to when the ramp exceeds a threshold level determined by a feed-back error signal ERROR from the output. Transistors Q5 and Q7 are used to prevent spurious resetting of the magnetic amplifier by ringing or diode reverse current. A detailed circuit is described (Figs 4A-4D) which includes an 5CR (D44) which shorts the output of the secondary supply as the result of a sensed malfunction. <IMAGE>

Description

Power Supply The present invention relates to power supplies, and more specifically to those of the DC-to-DC converter type.

There are many situations, including though not limited to computer systems, in which a DC power supply is available but the voltage and/or regulation of that supply make it unsuitable for using to power the system directly. It is therefore necessary to generate secondary DC power supplies. of desired voltage and regulation from the primary power supply, which we will term Bulk supply.

One common technique for performing such generation and conversion is to provide switching means controlled by a pulse generator of fixed frequency and variable duty cycle to alternately connect and disconnect the bulk supply to the primary winding of a transformer. The output AC voltage of the secondary winding thus generated may be rectified and filtered to provide a DC voltage.

The turns ratio of the transformer, along with the duty cycle of the pulse generator allows the secondary voltage to be adjusted to suit the requirements.

The main method of achieving regulation of the output voltage in such a system may be termed negative feedback from the output. In this, the DC output voltage of the secondary circuit is monitored and compared with a fixed reference voltage, the difference of these being amplified by a difference amplifier and used to control the duty cycle of the pulse generator which controls the switches. This results in the DC output voltage being controlled and held constant. The feedback loop thus includes the pulse generator, the switching means. the transformer, the rectification circuit, the filter circuit and the difference amplifier.

An alternative method of achieving regulation of the output voltage may be termed negative feedback from a sense winding. In this, the average forward voltage of a sense winding on the transformer is monitored and compared with a fixed reference voltage. the difference of these being amplified by a difference amplifier and used to control the duty cycle of the pulse generator, which controls the switching means. This results in the average forward voltage of the secondary winding being controlled and held constant. The DC output is again obtained by rectification and filtering of the transformer secondary winding voltage. This technique may be used in circumstances where as close a regulation as can be achieved by output negative feedback is not required.One advantage of its use is that it automatically provides isolation in the feedback circuit between the secondary output and the pulse generator.

The DC-to-DC conversion technique can obviously be extended readily to supply a plurality of secondary voltages if several different voltage supplies are needed in a system. This is achieved by providing several secondary windings on the transformer and associated rectification and filtering circuits.

However, certain complications can arise, since there can be interactions between the different outputs and between them and the bulk supply.

The usual method of regulation of such a multi-output system is by negative feedback control of the secondary output which needs the tightest regulation (which we can term the main secondary output). The other secondary outputs will then be largely regulated automatically against variations in the bulk supply. However, they will not be regulated against variations caused by changes in their output load. Further, they will be adversely affected by variations in the load of the main secondary output, because such variations reflect upon the duty cycle of the pulse generator controlling the switching means. If some of these other secondary outputs require better regulation, therefore, the usual procedure is to regulate them by what may be termed postregulation. In this, a post-regulator circuit is added to such secondary outputs.

The present system is concerned with a power supply in which the bulk supply is poorly regulated and several outputs of different voltages are required, some of which need close regulation. In the present system, regulation is achieved by negative feedback from a sense winding on the transformer, together with post-regulation for those secondary outputs for which better regulation is required than can be achieved by the negative feedback on the transformer by itself. Negative feedback from the sense winding on the transformer ensures that the ForwardVoltage-Time product applied to all secondary windings on the transformer is held constant, independent of output loads, thereby avoiding interaction between the secondary outputs and between the bulk supply and secondary outputs.

Those secondary outputs requiring close regulation are thus regulated by means of post-regulation.

The response time of the circuit involving negative feedback from the sense winding of the transformer can be kept low, since it does not have the constraints imposed on it normally associated with the time constant of the filter circuits used in the secondary outputs. The response time of the postregulation circuits will still be dependent on these constraints. In general the time constants of the post-regulator circuits will be greater than the time constant of the circuit involving negative feedback from the sense winding on the transformer. The time constants of the post-regulation circuits are however not inter-dependent, unlike the system which involves negative feedback from the main secondary output.

One aspect of the present system thus relates to the regulation arrangements in DC-to-DC converters, and is concerned more specifically with (a) the provision of front-end (transformer) regulation by regulating the volt-time product of the transformer pulses, and preferably (b) the provision of a plurality of separate secondary supplies. and preferably also (c) the provision of output regulation for at least some of the secondary supplies.

The present system will now be described in detail with reference to the the drawings, and various features thereof will become more apparent from this description. In the drawings: Fig. 1 is a simplified block diagram of the transformer and associated regulation control circuitry; Fig. 2 is a circuit diagram of the structure and operation of the main secondary output: Fig. 3 is a circuit diagram of the circuitry for controlling the magnetic amplifier; Figs lA to 3A are waveforms illustrating the operation of the circuitry of Figs.

1 to 3 respectively; and Figs. 4A to 4D are detailed circuit diagrams of a practical embodiment of the system.

Fig. 1 is a simplified block diagram of the MOSFET switches, transformer, pulse generator, and the negative feedback from the sense winding of the transformer. The bulk voltage is a supply Vbulk which is alternately connected to and disconnected from the primary winding PRIM of the transformer via a circuit consisting of a pair of MOSFETs Q3 and Q4 and a pair of flyback diodes D8 and D9. The MOSFETs are controlled via an isolation transformer T4 from a pulse width modulator PWM.

The voltage of a sense winding SENSE on the transformer T3 is forward rectified by a diode D18 and then filtered by a low pass filter FLTR, the output voltage of which is proportional to the ForwardVoltage-Time product applied to the sense winding. The PWM has a pair of difference inputs, one of which is fed by the filter circuit and the other with a constant and fixed reference voltage Vrefl. The PWM will adjust its duty cycle in dependence on the amplified difference of Vrefl and the output voltage of the low pass filter FLTR.

The effect of this is that the latter voltage is kept constant during variations in Vbulk and variations caused by losses associated with the MOSFETs Q3 and Q4 and the primary winding of the transformer and magnetic losses of the transformer. Thus the ForwardVoltage-Time product applied to the sense winding SENSE and all other secondary windings SEC 1 to SEC N is kept constant.

The part of the system as described and depicted in Fig. 1 may be termed the front end, with the secondary windings as its outputs and bulk voltage as its input.

Fig. 1A shows the most important waveforms associated with this operation.

Waveform PWM is the output of the pulse width modulator, which controls the MOSFET switches, a pulse signal of substantially fixed frequency, and with a duty cycle dependent on the magnitude of the amplified voltage difference between Vrefl and the output of the low pass filter FLTR. Waveform T3 is the waveform appearing across the windings of transformer T3. This waveform is much of the same shape for all windings though of course the amplitude depends on the winding ratio between the primary and any particular secondary winding.

For the primary winding, the positive part at the beginning of the period is of amplitude Vbulk. and is a result of the MOSFETs Q3 and Q4 being turned on; this period is referred to as the on-time. When the MOSFETs are turned off, the current which is flowing in the primary winding collapses through the flyback diodes D8 and D9 back into the bulk supply. The amplitude of the negative part of waveform T3, the off-time, is therefore equal and opposite to that of the positive part, and equal to Vbulk. Since the current must return to zero, the width of the negative pulse is therefore equal to that of the positive pulse for the duration of the on-time. After that the negative voltage will collapse.

The duty cycle of the PWM must always be less than 50%, so that the primary current may return to zero and the transformer be reset completely before the next cycle starts. The broken-line waveform show the effect of a reduction of Vbulk. The amplitude of the waveform T3 is reduced, the length of the pulse from PWM, corresponding to the MOSFET on-time, is increased, to keep the ForwardVoltage-Time product constant. It may be observed that the negative portion of waveform T3 has also reduced in amplitude and increased in length, within the period.

The structure and operation of a post-regulated output will now be considered.

The transformer T3 has several secondary windings, each forming part of a respective secondary supply. Some of these supplies incorporate individual output regulation, while others do not, depending on which supplies need to be closely regulated and which need only be loosely regulated. The various secondary supplies will in general be at different voltages.

Fig. 2 is a circuit diagram of a typical regulated secondary supply. The secondary winding SEC1 of transformer T3 feeds an LC filter circuit consisting of an inductor L4 and a capacitor C50 via a forward rectifying diode D33A, with being a flyback diode D33B. This is all conventional.

Post-regulation is achieved in this circuit by means of a magnetic amplifier L3.

The ForwardVoltage-Time product available at the secondary windings exceeds that required to maintain the post-regulated output voltage. The magnetic amplifier holds off the excess amount in order to obtain a constant output voltage during load variations.

The magnetic amplifier arrangement is shown in Fig. 2. The magnetic amplifier L3 consists of a toroidal core (because it is tape wound) with en eppro piste number of turns.

The magnetic amplifier operates on the principle that while the material is not saturated, the winding has a very high inductance, resulting in a virtual open circuit, whereas while the material is saturated, the winding inductance is very low, resulting in a virtual short circuit. Briefly, the magnetic amplifier acts as a saturable reactor.

At the beginning of each on-time the magnetic amplifier core is unsaturated and it passes a small current during time td. After this time the core becomes saturated, and the current in the secondary winding of the transformer T3 and in the magnetic amplifier winding L3 then rises sharply until it equals the current in the output inductor L4. At the beginning of the transformer offtime, the magnetic amplifier core must be reset by the appropriate amount, i.e.

for the appropriate time. The required reset time is equal to the time required to delay the onset of saturation at the beginning of the next cycle, since both set and reset are effected by equal (though opposite) voltages. nsmely the forward and flyback voltages of the transformer secondary winding.

The mechanism used to reset the magnetic amplifier is shown in Fig. 2, and the associated waveforms are shown in Fig. 2A. Transistor Q6 (which is protected against reverse voltages by diode D30) is turned on at the beginning of the off-time. This applies the transformer fly back voltage, with amplitude A, to the magnetic amplifier. Qfi is turned on for td seconds. Because the magnetic amplifier is reset by a Volt-Seconds product A.td, the same Volts Seconds product must be applied to the magnetic amplifier before it reaches saturation and hence turns on.

The waveform appearing at the anode of diode D33A has now a reduced duty cycle dependent on the hold off time of the magnetic amplifier. Rectification by D33A and D33B and filtering by L4 and C50 will produce a DC voltage Vout.

It will be noticed that this type of regulation is in principle non-dissipative, unlike conventional series or parallel regulators.

To compensate for output voltage variations due to load variations, the hold-off time of the magnetic amplifier must be sdjusted in a suitable manner.

The control signal for this adjustment must be proportional to the deviation of the output voltage Vout from 8 reference voltage. This must be converted into a time value, setting the hold-off time of the magnetic amplifier. This time value must be a given fraction of the on-time of the forward voltage of the secondary winding. This forward voltage on-time however is not constant, since it is varied in response to the Bulk voltage amplitude, as indicated in Fig. lA (waveform T3). Hence the holdoff time of the magnetic amplifier must depend on the difference between the output voltage Vout and a reference voltage, and the on-time as controlled by the front end.

The output of the sense winding SENSE is fed to a peak forward rectification circuit consisting of diode D17 and capacitor C16 (Fig. 3). Hence the voltage on 016 will be at a level corresponding to the peak forward amplitude of waveform T3, which is proportional to the Bulk voltage amplitude. An RC circuit consisting of capacitor C48 and resistor R27 is connected to this capacitor C16 and has a time constant such that C48 charges sufficiently linearly for the time periods involved.

Capacitor C48 is discharged and held such by the inverse of the PWM signal via a diode D13. Hence during the on-time of waveform T3, the voltage RAMP on capacitor C48 is held at zero. Upon the start of the off-time of waveform T3, the voltage across C48 starts to ramp up linearly, at a rate which is proportional to the Bulk voltage amplitude. The output voltage Vout of the secondary output is compared to a constant and fixed reference voltage Vref2 by a difference amplifier AMPl. The amplified difference signal is an error voltage ERROR (= Vout - Vref2), which is fed to a comparator COMP1. The ramp voltage RAMP is fed to the other input of comparator COMP1. This configuration generates a signal RESET, starting at the beginning of the off-time by virtue of the transformer flyback voltage and terminating at the point where the signal RAMP intersects the error voltage.

It will be evident that for a given error voltage, an increase in bulk voltage will cause the ramp voltage to ramp up faster and to intersect ERROR earlier in time, thus shortening the signal RESET which in turn controls the reset time of the magnetic amplifier and hence the hold-off time, as is evident from the waveforms in Fig. 3A. Similarly, a decrease in the bulk voltage lengthens the signal RESET.

The effect is that there is a feedforward mechanism which compensates the magnetic amplifier hold-off time for variations in bulk voltage amplitude without a change in the error voltage. So therefore there will be no need for the post-regulator negative feedback circuit (AMP 1) to respond to output voltage changes caused by Bulk voltage variations, since these are corrected by the feedforward mechanism before they can affect the secondary output voltage Vout.

The post-regulator negative feedback circuit need only compensate for output voltage changes induced by load variations.

It will be noted that in the present system the magnetic amplifier has only a single winding, which is used both for the resetting of the magnetic amplifier and to carry the current to the output filter circuit, which is proportional to the output load current. This is in contrast to many conventional systems, where the magnetic amplifier often has one or more extra windings carrying the control or reset current only, in addition to the main winding which carries the load current.

Also, it will be noted that in the present system an already available voltage is utilized for the reset purpose, namely the transformer flyback voltage; this is in contrast to the more conventional system, where a separate voltage source is required for the resetting of the magnetic amplifier. Further, it will be noted that in the present system, the means of varying the magnetic amplifier hold-off time is by controlling the reset time directly in a non-dissipative manner, while the reset voltage is not controlled, unlike many conventional systems wherein the reset voltage is controlled directly by dissipative means and for a fixed time.

Further aspects of the present system are concerned with the magnetic amplifier arrangements just discussed. These aspects concern the provision of a magnetic amplifier having only a single winding and connected in series with the secondary winding, and its control by means of a transistor switch forming a closed loop with it and the secondary winding. They also concern the manner in which the control signal is generated, by combining a signal representing the deviation of the output voltage from a reference value and a signal representing the magnitude of the input (bulk) voltage, to generate a control pulse the width of which is dependent in a multiplicative manner on both these signals.

Additional aspects of the present system are concerned with techniques for overcoming various effects which may disturb the desired performance of the magnetic amplifier. such techniques involving the provision of current bypass paths. These techniques will now be discussed.

The operation of the magnetic amplifier as so far described is subject to various disturbing effects. The current through the magnetic amplifier during reset is a small fraction of the current through it when it is fully conducting, which is also the current in diode D33A in Fig. 2. The reverse leakage current of this diode is of the same order as the magnetic amplifier reset current, thus causing spurious setting during the off-time, after the controlled and intended reset of the magnetic amplifier. Further, imperfections in transformer design and circuit layout result in the presence of parasitic capacitance in the circuit.

causing an undesired possible ringing of the magnetic amplifier voltage at the end of the reset time, thus causing an uncontrolled partial setting or resetting of the magnetic amplifier.

Referring to Fig. 2, transistor Q5, protected against reverse voltages by diode D26, and controlled by the RESET signal, effectively bypasses any possible reset currents through the magnetic amplifier at any time in the cycle other than that intended during reset. The configuration of q5 being an NPN and Q6 a PNP transistor automatically creates the necessary signal inversion. as both are driven by the same control signal RESET. When Q6 is turned on, Q5 is turned off, and vice versa.

Transistor Q7, which is protected against reverse voltages by diodes D27 and D28, is turned on by the transformer voltage during the off-time through resistors R43 and R45 (for as long as this voltage remains large enough). This bypasses any undesirable set currents through the magnetic amplifier for the entire off-time.

Since Q5, Q6 and Q7 only need to carry currents of the order of the mar netic amplifier set/reset current and as they operate either in the fully saturated or the fully off mode, these transistors need only have relatively small current ratings, compared to the output current rating of the post-regulator circuit they control.

Figs. 4A to 4D show the circuitry of the system in greater detail, incorporating a variety of practical details. The references are largely the same as in Figs. 1 to 3.

Fig. 4A shows the transformer T3 and the bridge circuit Q3-Q4-D8-D9.

The gate-source voltages to the FETs are clamped by zener diodes, and snubber resistors and capacitors are connected across them as shown. The snubber networks reduce switching losses in the FETs (at the cost of snubber network losses) and protect them from overvoltage spikes during switching. The ferrite bead reduces the rate of transfer of current from the snubber networks to the fly back diodes, so reducing overshoot on the FETs.

Fig. 4B shows the pulse width modulator PWM, which has a nominal frequency of 50 kHz and a duty cycle of between 0.2 and 0.45. This drives the bridge circuit via a driver block El, which in turn drives the transistors Q3 and Q4 via the transformer T4. The filter circuit FLTR consists largely of the circuitry from transistor 42 to the block PWM. The PWM is driven from an external clock signal.

Fig. 4C shows the main secondary supply. The output from capacitor C50 is further smoothed by bus bar assembly circuitry. An SCR D44 and its associated circuitry are used to sense malfunction and short out the output, so preventing possible damage to the load fed by the secondary supply.

Fig. 4D, along with part of Fig. 4B, shows the implementation of the circuitry of Fig. 3. The circuitry from R63 and R160 to the amplifier E5 smooths the secondary supply output voltage, and amplifier E5 corresponds broadly to comparator COMP1. Amplifier E7 corresponds broadly to comparator COMP2, and its output is fed to a driver circuit of transistors Q & and Q9 which drives the magnetic amplifier.

Claims

1 A transformer DC-to-DC converter comprising: primary switching means connecting a supply voltage to the primary of the transformer; primary control means turning on the primary switching means with on pulses of constant repetition frequency and width inversely proportional to the input voltage, a secondary winding feeding rectifying and smoothing means via secondary switching means to produce the output voltage; and secondary control means controlling the secondary switching means to block the secondary winding output for the initial part of each on pulse period, the secondary control means setting the width of the blocking signal as the time from the start of a ramp of slope determined by the supply voltage to when the ramp exceeds a threshold level determined by a feedback error signal from the output.

2 A converter according to claim 1 wherein the transformer also has a sense winding the output of which is rectified and smoothed and fed to the primary control means to control the on pulse width.

3 A converter according to claim 1 wherein the transformer also has 9 sense winding the output of which is rectified and smoothed and fed to the secondary control means to determine the slope of the ramp

4 A converter according to claim 1 wherein the transformer also has a sense winding the output of which is rectified and smoothed and fed to the primary control means to control the on pulse width. and to the secondary control means to determine the slope of the ramp.

5 A converter according to any previous claim wherein the primary switching means comprise a bridge circuit of two transistors and two diodes.

6 A converter according to any previous claim wherein the transformer has at least one further secondary winding feeding further rectifying and smoothing means to produce a further output voltage.

7 A converter according to any previous claim wherein the secondary switching means is a magnetic amplifier connected in series with the secondary winding.

8 A converter according to claim 7 wherein the secondary control means initiates the ramp at the end of the on pulse time and further includes a transistor connected across the series secondary-winding/magnetic-amplifier path and which is turned on by the blocking signal to set the magnetic amplifier, which is thereby reset at the beginning of the next on pulse time and blocks the secondary voltage during such resetting.

9 A converter according to claim 8 wherein the magnetic amplifier has connected across it switching transistor means which are turned on to prevent false setting of the magnetic amplifier.

10 A converter according to claim 9 wherein the switching transistor means includes means which are turned on on the ending of the blocking signal.

11 A converter according to either of claims 8 and 9 wherein the switching transistor means includes means which are turned on on the ending of the on pulse time to prevent reverse current flow in the magnetic amplifier during the blocking pulse time due to magnetic amplifier ringing.

12 A transformer DC-to-DC converter substantially as herein described.