GB2220273A - Peak holding circuit - Google Patents

Abstract

A peak-holding circuit in which the level of the output voltage exactly matches the peak level of input voltage comprises two diode-capacitor arrangements (10, 30) series connected between input (I) and ground (G) terminals with the capacitors (16A, 16B) back-to-back. A constant amplitude signal derived (26) from the input voltage is delivered to the inter-capacitor junction (C) and of opposite polarity to the input voltage. The output (Q) of the circuit is provided by a difference circuit (40) connected across the two capacitors (16A, 16B). The output voltage does not depend on the actual voltage across either diode (14A, 14B). Time delay devices (44A, B) may be added to the circuit. <IMAGE>

Description

PEAK HOLDING CIRCUIT This invention relates to a peak holding circuit.

Peak holding circuits are well known being adapted to receive an input electrical signal and having an output at which only the peak value of the input signal is presented. Conventional peak holding circuits consist of a series-connected diode and capacitor, the output being taken across the capacitor which has one terminal connected to earth. The sensitivity of this type of circuit is greatly limited since about 300 mv (if the diode is a Schottky diode) must be developed across the diode before the circuit conducts and consequently the output voltage of the circuit is at least 300 mv less than that of the peak input voltage to the circuit. Other forms of diodes produce upwards of 700 mv voltage drop.

Such conventional peak holding circuits are typically supplied via a pre-amplifier which limits the maximum input voltage to the circuit so that the dynamic range of the circuit, which is the ratio of the maximum input voltage to the sensitivity, is limited and typically is of the order of 10 to 50. Additionally due to current leakage in reverse flow through the diode into the output impedance of the amplifier the voltage stored in the capacitor tends to decrease over a period of time.

It is an object of the present invention to provide a new and improved peak holding circuit.

According to the present invention there is provided a peak holding circuit comprising an input terminal for receiving an input voltage, a signal-injection terminal, an earth terminal and an output terminal, first and second series-connected diode and capacitor arrangements, said arrangements being respectively connected in series between said input and earth terminals with the capacitor of each arrangement being connected to said signal-injection terminal and the diodes of said arrangements being matched and oppositely poled, signal injection means connected between said input and signal-injection terminals and arranged to inject into said signal-injection terminal a voltage of opposite polarity to the input voltage and of greater value than the voltage drop across the diode of one of the arrangements, and difference means being arranged to provide to said output terminal the difference in value between the voltages at the junctions between the diode and capacitor of each arrangement.

By virtue of the present invention the voltage provided at the output terminal is substantially equal to the peak value of the input voltage and without loss due to diode voltage drop occurring in the first arrangement since this is compensated by the presence of the second arrangement which is effectively supplied by the signal-injection means.

Conveniently the anode of the diode of the first arrangement is connected to the input terminal in which case the circuit is adapted to handle input voltages of positive polarity. Alternatively the cathode of the diode of the first arrangement is connected to the input terminal in which case the circuit is adapted to handle input voltages of negative polarity. In each case the two diodes are oppositely poled in the series connection between input and earth terminals.

Conveniently the signal injection means includes a comparator having a first input connected to the input terminal and a second input connected to a threshold voltage source which sets the threshold voltage of the comparator.

Preferably the capacitors of the first and second arrangements are matched, which is particularly desirable for input voltages in the form of low frequency pulses.

A passive time-delay means may also be provided between the input terminal and the diode of the first arrangement and between the ground terminal and the diode of the second arrangement to compensate for propagation delays through the signal injection means.

When the circuit is supplied via a pre-amplifier a resistance equal in value to the output resistance of the pre-amplifier is preferably connected between the diode of the second said arrangement and the earth terminal so that the charging characteristics of the capacitors are matched.

Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which: Fig. 1 is a circuit diagram of a prior art peak holding circuit; Fig. 2 is an embodiment of a peak holding circuit in accordance with the present invention; Fig. 3 illustrates typical voltage waveforms in the circuits of Figs. 1 and 2; and Fig. 4 illustrates a modification of the Fig. 3 circuit.

With reference to Fig. 1, a conventional peak holding circuit 10 has an input terminal I and is formed by a series connected diode 14 and capacitor 16. Plate O of capacitor 16 is grounded at terminal G and plate N, which is connected to diode 14, forms the output terminal Q of the circuit. The circuit is supplied via a pre-amplifier 12 and the diode voltage drop caused by diode 14 causes the voltage at terminal Q always to be less than the peak value of voltage at input terminal I.

In the circuit shown in Fig. 2 a first series-connected diode and capacitor arrangement 10 is connected in series with a second series-connected diode and capacitor arrangement 30 between input terminal I and ground terminal G. The capacitors 16A, 16B of the arrangements 10, 30 are interconnected at terminal C which functions as a signal injection terminal C and to which a signal is provided by signal injection means 20. Output terminal Q of the Fig. 2 circuit is supplied by a difference circuit 40 the two inputs of which are respectively connected to the junction between the diode and capacitor of arrangements 10, 30.

The diodes l4A, 14B of the arrangements 10, 30 are conveniently identical but oppositely poled Schottky Barrier diodes which generally develop a voltage drop of 300mv in forward bias. The representation of a single diode, for example 14A, is intended to embrace several similarly poled series connected diodes because, as will become evident the diode voltage drop is effectively cancelled by the present invention and therefore is not a limiting factor. The signal injection means 20 comprises a comparator 26, the first input 22 of which is connected to input terminal I, the second input 24 being connected to a variable threshold voltage source, conveniently via a resistor arrangement, which sets the threshold voltage of the comparator 26. The difference circuit 40 is a differential amplifier 42.

With the circuit in operation an input voltage A of for example -1 volt peak value is inverted to +1 volt by pre-amplifier 12 and is delivered through input terminal I to the first arrangement 10. The diode 14A gives rise to a voltage drop, (0.3 volts for a Schottky diode), so that on plate N of the first capacitor 16A there is +0.7 volts.

Additionally, the +1 volt at terminal I is delivered to comparator 26 of signal injection means 20 and, being greater than the value of the threshold voltage, (which is set only to overcome noise levels in input voltage A), a fixed comparator output level, opposite in polarity to the voltage at terminal I, of -4 volts is obtained at terminal C. The -4 volts value is disposed on plate 0 of the first capacitor 16A and also on plate R of second capacitor 16B. Plate S of capacitor 16B has -0.3 volts disposed upon it due to the voltage drop across the second Schottky diode 14B in forward bias. There exists, therefore, across capacitors 16A and 16B voltage differences of 4.7 volts and -3.7 volts respectively.

The difference circuit 40, is connected in such a manner that it will provide, at output terminal Q the voltage difference between the capacitor voltages i.e. 4.7 volts -3.7 volts, which is exactly equal at +1 volt to the peak value of the original input voltage A. The Fig. 2 circuit therefore overcomes the problem of reverse leakage from capacitor lEA through diode 14A.

The Fig. 2 circuit output at Q can be reset to Ovolts by temporarily closing switches (not shown) connected across capacitors 16A, 16B or connected from each input of comparator 42 to ground G. Of course, when the level of the input voltage A drops below the threshold voltage of comparator 26 the output voltage at Q also goes to zero.

With reference to Fig. 3 conventional peak holding circuits of the Fig. 1 type have an output waveform Z appearing at terminal Q. Waveform Z decays in amplitude with time due to reverse diode leakage. However using the Fig. 2 circuit waveforms X and Y are effectively provided by the respective arrangements 10, 30 and each decays at almost the same rate so that the output delivered to terminal Q which is the difference between waveforms X and Y, shown as Vo, is constant and equal to the peak value of input voltage A.

It will be appreciated, with further reference to Fig.

3, that a time delay of T seconds exists between the commencement of waveform Z and each of waveforms X and Y, which is caused by the inclusion of passive time delay devices 44A and 44B shown in phantom in arrangements 10 and 30 respectively to remove the practical problem introduced by propagation delays in the injection means 20. Due to devices 44A, 44B the voltage levels previously described appear synchronously at the plates of the capacitors lEA, 16B.

A resistance 46 equal in value to the output resistance of the pre-amplifier 12, may be connected between diode 14B of the second series connected arrangement 30 and ground terminal G in order to match resistances.

Fig. 4 shows a modification to the Fig. 2 circuit in which each diode 14A, 14B is one of a boot-strapped diode pair. Thus, diode 14A is associated with diode 14A', a unity gain amplifier 17A and a feedback resistor 18A which results in improved capacitor holding time.

The dynamic range of the Figs. 2 and 4 circuits can be as high as 3000 which is considerably higher than the value achieved using conventional peak holding circuits and is necessary for very short duration input voltages A.

Claims (6)

Claims

1. A peak holding circuit comprising an input terminal for receiving an input voltage, a signal-injection terminal, an earth terminal and an output terminal, first and second series-connected diode and capacitor arrangements, said arrangements being respectively connected in series between said input and earth terminals with the capacitor of each arrangement being connected to said signal-injection terminal and the diodes of said arrangements being matched and oppositely poled, signal injection means connected between said input and signal-injection terminals and arranged to inject into said signal-injection terminal a voltage of opposite polarity to the input voltage and of greater value than the voltage drop across the diode of one of the arrangements, and difference means being arranged to provide to said output terminal the difference in value between the voltages at the junctions between the diode and capacitor of each arrangement.

2. A circuit as claimed in claim 1, wherein a passive time-delay means is provided between the input terminal and the diode of the first arrangement and between the ground terminal and the diode of the second arrangement to compensate for propagation delays through the signal injection means.

3. A circuit as claimed in either preceding claim, wherein the diode of each said arrangement is one of a boot-strapped pair associated with a unity gain amplifier and feedback resistor, the output of each such amplifier forming the inputs for the difference means.

4. A circuit as claimed in any preceding claim, wherein the capacitors of the first and second arrangements are matched.

5. A circuit as claimed in any preceding claim, wherein the input terminal is fed from a pre-amplifier having an output resistance and a resistance equal in value to the output resistance of the pre-amplifier is connected between the diode of the second said arrangement and the earth terminal so that the charging characteristics of the capacitors are matched.

6. A circuit as claimed in claim 1, and substantially as hereinbefore described with reference to Fig. 2 or as modified by Fig. 4.