GB2256336A

GB2256336A - Variable gain circuit

Info

Publication number: GB2256336A
Application number: GB9111386A
Authority: GB
Inventors: Michael John Gay
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 1991-05-25
Filing date: 1991-05-25
Publication date: 1992-12-02
Also published as: GB9111386D0

Abstract

A variable gain circuit comprises first and second back-to-back coupled diode means (21, 22) coupled to differential amplifier means (23, 24), such as a differentially connected transistor pair biased by a current generator (26). The first and second diode means are also coupled between first and second input nodes (31, 32). The circuit further comprises negative feedback means (36, 37, 38, 39, 40), which, in response to a signal at a junction 35 of the first and second diode means, returns first and second signals to the first and second input nodes respectively, so that the voltage levels at the first and second input nodes and at junction 35 are substantially independent of the levels of input signals at the first and second input nodes. Preferably, the negative feedback means comprises first and second current sources, such as first (39) and second (40) transistors, and a third transistor (36) having a base electrode coupled to junction 35, and an emitter electrode coupled to the base electrodes of the first (39) and second (40) transistors. <IMAGE>

Description

Variable Gain Circuit This invention relates to variable gain circuits.

Variable gain circuits are widely used in analog signal processing systems, such as video systems. A well known technique for realising such circuits is the differential current mirror shown in Figure 1.

In this circuit arrangement, an input signal together with a bias voltage is applied to node 11. The input signal causes a signal current, I1, to circulate via two back-to-back connected diodes 1, 2 and series resistors 9, 10 to node 12 which is coupled directly to a bias voltage (e.g. ground). The back-to-back connected diodes 1, 2 are biased by current generators 5, 7, 8 and are coupled at nodes 13 and 14 to the bases of a differentially connected transistor pair 3, 4.

The transistors 3, 4 are biased by current generator 6. The differential signal voltage developed between nodes 13, 14 due to the signal current I1 flowing through the diodes causes an output current 10 to circulate through transistors 3, 4. The ratio of 1o to I1 depends on the ratio of the bias currents in the transistors 3, 4 and back-to-back diodes 1, 2 and may thus be varied by varying one or both of these currents: that is, by varying the currents generated by current generators 6 and 5 respectively.

Numerous variations of this circuit are possible. For example, a second pair of transistors may be connected in a cross-coupled arrangement with transistors 3 and 4 to produce a fully balanced circuit. Furthermore, although the above circuit has been described with reference to a single input signal at node 11, a second input signal may also be applied to node 12 together with a bias voltage.

For high frequency applications, for example for frequencies above 1 MHz, other signals in the circuit and stray capacitances can cause distortions in the output signal 1o and thus, it is desirable to maintain symmetry between the signals at nodes 13 and 14, to minimise coupling to and from the supply lines and to obtain the maximum rejection of any disturbances of the bias voltages and currents. In high frequency circuits, therefore, input signals will usually toe applied at both nodes 11 and 12 and the desired input current wilf' be determined by the difference between these signals.

Usually one input signal will be the inverse of the other. In this case, the common-mode signals of the two input signals cancel so that the signal levels at nodes 13 and 14 will be small and the signal level at the intersection of the diodes, node 15, will be zero. This makes the circuit relatively insensitive to stray capacitances.

If the input signals are other than equal but opposite phase, the common-mode signals do not cancel and the circuit is no longer insensitive to stray capacitance. The signal voltages at nodes 13, 14, 15 will be roughly the average of the input signals, causing significant currents to flow in the stray capacitances of the circuit at high frequencies. These capacitive currents degrade the frequency response of the circuit and introduce distortion since the signal currents in the back-to-back diodes 1, 2 no longer remain equal.

In order to overcome the problems of the prior art circuit at high frequencies due to common-mode signals and stray capacitance, it is desirable to have a variable gain circuit which is insensitive to stray capacitance for arbitrary input signals and which thus, behaves as a true differential input circuit at higher frequencies than has heretofore been the case.

In accordance with the present invention there is provided a variable gain circuit comprising: first and second back-to-back coupled diode means coupled to differential amplifier means and between first and second input nodes; and negative feedback means responsive to a signal at a junction of the first and second diode means for returning first and second signals to said first and second input nodes respectively so that the voltage levels at the first and second input nodes and at the junction of the first and second diode means are kept substantially close to zero whether the input signals applied to the first and second input nodes are differential or comprise a common-mode component.

Thus, it will be appreciated that at high frequencies the present invention ensures that the common-mode components cancel irrespective of whether the input signals are truly differential or not. The advantage of this is that the variable gain circuit in accordance with the invention is insensitive to stray capacitances at higher frequencies than has previously been possible.

Preferably, the negative feedback means comprises first and second current sources coupled to the junction of the first-and second diode means. The first current source supplies the first signal to the first input node in response to the signal at the junction and the second current source supplies the second signal to the second input node in response to the signal at said junction.

The first current source may comprise a first transistor having a collector electrode coupled to the first input node, an emitter electrode coupled to a first supply line and a base electrode. The second current source may comprise a second transistor having a collector electrode coupled to the second input node, an emitter electrode coupled to the first supply line and a base electrode: the base electrodes of the first and second transistors being coupled together to the junction of the first and second diode means for receiving the signal thereat.

In a preferred arrangement, the negative feedback circuit further comprises a third transistor having a base electrode coupled to the junction, a collector electrode coupled to a second supply line and an emitter electrode coupled to the base electrodes of the first and second transistors. The third transistors shifts the level of the signal at the junction of the first and second diode means.

A variable gain circuit in accordance with the invention will now be described, by way of example only, with reference to the accompanying drawings in which: Figure 1 shows a prior art differential current mirror; and Figure 2 shows a variable gain circuit in accordance with the present invention.

Figure 2 shows a preferred embodiment of the present invention. The variable gain circuit 20 is similar to that shown in Figure 1 in that it comprises first 31 and second 32 input nodes coupled to the first terminals of two back-to-back coupled diodes 21 and 22 respectively via series resistors 29 and 30. The first terminals of the two back-to-back diodes 21 and 22 are also coupled to the bases of a differentially connected transistor pair comprising two NPN transistors 23 and 24. Like components to those of Figure 1 are referenced by the same reference numeral plus twenty.

However, the variable gain circuit 20 further comprises a negative feedback arrangement comprising elements 36, 37, 38, 39 and 40.

The structure and function of the negative feedback arrangement will be described in more detail below.

The emitter electrodes of the transistor pair 23 and 24 are connected together to a current generator 26 which provides the bias for the transistor pair 23 and 24. The collector electrodes of the transistor pair 23 and 24 form the output of the variable gain circuit.

The second terminals of the back-to-back coupled diodes are coupled to a current generator 25 and to a base electrode of a NPN transistor 36. Transistor 36 ensures that the negative feedback arrangement does not sink any current provided by current generator 25 and that the level of the signal at the junction of the back-to-back diodes 21 and 22, node 35 is shifted. The collector electrode of transistor 36 is coupled to a first supply line and the emitter electrode of transistor 36 is coupled to a first terminal of a third diode 37 which is coupled in series with a fourth diode 38.

The second terminal of the fourth diode 38 is coupled to a second supply line (for example, ground). Both the second terminal of the third diode 37 and the first terminal of the fourth diode 38 are coupled to the base of a fourth NPN transistor 39 which is also interconnected to the base of a fifth NPN transistor 40. The emitter electrodes of the fourth and fifth transistors 39 and 40 are coupled to the second supply line. The collector electrodes of the fourth and fifth transistors 39 and 40 are respectively coupled to the bases of the transistors 24 and 23 which form the differential transistor pair.

The back-to-back coupled diodes 21 and 22 are biased by current generator 25 and fourth 39 and fifth 40 transistors.

The DC conditions (i.e. for zero input signals) of the variable gain circuit 20 are established as follows.

The current supplied by current generator 25 divides between the back-to-back diodes 21 and 22. The voltage at node 35 establishes itself at 3Vbe such that transistor 36 is in conduction.

The negative feedback ensures that transistors 39 and 40, which are assumed to be matched, sink the currents flowing in back-to-back diodes 21 and 22, together with any DC flowing in resistors 29 and 30 due to any difference between the bias voltages applied to nodes 31 and 32 and the voltage (2Vbe) established by the feedback at nodes 33 and 34. Since signal currents flow in transistors 39 and 40, the circuit must be so dimensioned that their bias currents exceed the peak signal current at the inputs 31 and 32 to ensure that they are maintained in conduction.

The current flow in the circuit 20 for an input signal I1 applied to the input node 31 is shown in Figure 2. For simplicity, it is assumed that the base current of transistor 36 is negligible and that the fourth diode 38 and fourth 39 and fifth 40 transistors are all matched. Since no significant current can enter the base of transistor 36, the negative feedback loop will cause any current arriving via back-to-back diode 21 to be sunk by fourth transistor 39 via back-to-back diode 22. Any current flow in the fourth transistor 39 will, however, be mirrored in fifth transistor 40 and thus, will be subtracted from the input current. The result is that the signal current flow in resistor 29 is split into equal parts flowing in back-to-back diode 21 and fifth transistor 40.

The part of the current flowing in back-to-back diode 21 then flows also in back-to-back diode 22 to be sunk by fourth transistor 39. Thus, the signal current flow is equal in the back-to-back diodes 21 and 22 as is required to maintain symmetry. No signal current flows in resistor 30 in this case. Consequently, assuming that the resistors 29 and 30 are much larger than the impedance of the back-to-back diodes 21 and 22 for the same input voltage, the input current I1 will be twice as high in the variable gain circuit 20 as that of the prior art shown in Figure 1.If the current generators 25 and 26 are the same as the current generators 5 and 6 of Figure 1, the bias currents through back-to-back diodes 21 and 22 will be the same as for Figure 1, as are also the signal currents, and thus, the circulating current in the transistors 33 and 34 will also be the same.

In summary, the feedback action of the variable gain circuit 20 in accordance with the invention forces the signal voltage at node 35 to be substantially close to zero so that the stray capacitance currents are minimised. This ensures that the circuit is insensitive to stray capacitances at high frequencies.

It will be appreciated that the variable gain circuit 20 in accordance with the invention has been described with reference to an input signal applied to one of the input nodes 31. However, it will be obvious from the symmetry of the circuit that the operation will be substantially the same for a signal applied at node 32, except that the polarity of the output will be inverted.

The variable gain circuit in accordance with the invention therefore acts as a true differential amplifier rejecting any commonmode signal applied to the inputs. The common-mode rejection will be maintained to high frequencies because the signal voltages at nodes 33, 34, and 35 are always kept low (close to zero) by the feedback action.

It will be appreciated that the third diode 37 serves only to raise the voltage at the node 35 so that the voltages at nodes 33 and 34 are adequate to produce an output at the collectors of the transistor 23 and 24. The fourth diode 38 serves to reduce the loop gain of the negative feedback loop and to ensure that transistor 36 is adequately biassed to guarantee stability. Many other means for realising the coupling from node 35 to the bases of transistors 39 and 40 will be apparent to those skilled in the art: for example, third 37 and fourth 38 diodes could be omitted, in which case the current generator 26 must be returned to a source of negative potential. It will also be obvious that the circuit could be made asymmetric if desired with different value resistors and back-to-back diodes.

Furthermore, although the preferred embodiment has been described with respect to bipolar technology, it will be appreciated that the invention is not limited thereto and that a realisation of the invention in MOS technology will be apparent to a person skilled in the art.

Claims

1. A variable gain circuit comprising: first and second back-to-back coupled diode means coupled to differential amplifier means and between first and second input nodes; and negative feedback means responsive to a signal at a junction of the first and second diode means for returning first and second signals to said first and second input nodes respectively so that the voltage levels at the first and second input nodes and at the junction of the first and second diode means are substantially independent of the levels of input signals at the first and second input nodes.

2. A variable gain circuit according to claim 1 wherein said negative feedback means comprises first and second current sources coupled to the junction of the first and second diode means, said first current source for supplying the first signal to the first input node in response to the signal at said junction and said second current source for supplying the second signal to the second input node in response to the signal at said junction.

3. A variable gain circuit according to claim 2 wherein said first current source comprises a first transistor having a collector electrode coupled to the first input node, an emitter electrode coupled to a first supply line and a base electrode and said second current source comprises a second transistor having a collector electrode coupled to the second input node, an emitter electrode coupled to said first supply line and a base electrode, the base electrodes of the first and second transistors being coupled together to the junction of the first and second diode means for receiving the signal thereat.

4. A variable gain circuit according to claim 3 wherein said negative feedback circuit further comprises a third transistor having a base electrode coupled to said junction, a collector electrode coupled to a second supply line and an emitter electrode coupled to the base electrodes of the first and second transistors.

5. A variable gain circuit according to claim 4 wherein said negative feedback means further comprises third diode means having a first terminal connected to the emitter electrode of the third transistor and a second terminal coupled to the base electrodes of the first and second transistors.

6. A variable gain circuit according to claim 4 or 5 wherein said negative feedback means further comprises fourth diode means having a first terminal coupled to the base electrodes of the first and second transistors and a second terminal coupled to the first supply line.

7. A variable gain circuit according to any preceding claim wherein the differential amplifier means comprises: a first transistor having a base electrode coupled to the first input node, a collector electrode forming an output of the variable gain circuit and an emitter electrode; a second transistor having a base electrode coupled to the second input node, a collector electrode forming the output of the variable gain circuit and an emitter electrode coupled together with the emitter electrode of the first transistor; and a current source coupled to the emitter electrodes of the first and second transistors for providing a current signal thereto.

8. A variable gain circuit according to any preceding claim and further comprising a current source coupled to the first and second diode means for providing a current signal thereto.

9. A variable gain circuit according to any preceding claim wherein said first and second diode means are matched.

10. A variable gain circuit substantially as hereinbefore described with reference to Figure 2 of the drawings.