GB2248998A - Multiple HDLC processor - Google Patents

Abstract

A telecommunications switch for switching TDM signals between incoming and outgoing lines, the TDM signals comprising data frames in respective time slots, the switch including a processor and a memory store, the processor having a single processing channel including receiver means for receiving incoming data frames, sequentially extracting the data therefrom and transferring such data to the memory store, and said single processing channel including transmit means for sequentially reading the data in the memory store and formatting such data into data frames for sending on the outgoing line.

Description

MULTIPLE HDLC PROCESSOR Field of the Invention The present invention relates to telecommunications switching systems for switching time division multiplexed (TDM) signals in data frame format between incoming and outgoing lines.

The data frame format of the signals is particularly though not exclusively HDLC format.

Background Art There is a requirement for example in large offices or buildings for networks handling data and!or digital voice signals.

Such networks normally have the layered form of the ISO reference model in which messages are communicated between host processors by being split into packets, and transmitted along lines in the form of data frames Slayer 2 (data link protocol level) of the reference model]. As such each data frame includes various fields in addition to the information data field. It will be understood for the purpose of this specification that "data frame" refers to data in the format for layer 2 of the ISO reference model.

Such networks may be complex and include junctions between a multiplicity of lines. At such junctions, a complex switch is required to route incoming signals to the appropriate output line.

Such switch may comprise message switching units (MSU), each line to the switch terminating in an MSU and each MSU being coupled to the other MSU. Such an arrangement is shown in Figure 1, in which a plurality of lines 2 each terminate in an MSU 4. The MSU are interconnected as at 6, and the whole switch is controlled by a host processor 8.

A function of the MSU is to receive and store incoming data frames in HDLC format, and to reroute such data frames on output lines. Figure 2 is a block diagram of the construction of an MSU.

In Figure 2, an incoming line 2 and an outgoing line 2' are coupled via an interface 20 to a multiple HDLC processor 22, which receives the incoming HDLC data frames, stores the data in the frames in an external memory 24, and reformats the information as outgoing HDLC data frames. A host processor 26 provides overall control, in particular, the routing of incoming to outgoing data frames.

A multiple HDLC processor is known, as the Rockwell R8071 link layer controller. Such a processor operates by simultaneously processing all 32 channels of the incoming frame of HDLC packets.

This results in a complex and large processor since it must support 32 separate and simultaneous operations, which may create difficulties in construction or implementation of the processor.

Summary of the Invention With a view to overcoming the above-stated disadvantage of the known art, the present invention provides a processor for processing multiple data frames of information for a telecommunications switch for time division multiplexed signals. The processor operates by processing the multiple data frames in a sequential manner in a single high speed channel. In this way the requirements for processor capability and resultant complexity are reduced, although it is necessary for the single high speed channel to operate sufficiently fast to cope with the incoming data rate.

Accordingly the present invention provides, a telecommunications switch for switching TDM signals between incoming and outgoing lines, the TDM signals comprising data frames in respective time slots, the switch including a processor having a single processing channel including receiver means for receiving incoming data frames, sequentially extracting the data therefrom and transferring such data to a memory store, and said single processing channel including transmit means for sequentially reading the data in the memory store and formatting such data into data frames for sending on the outgoing line.

In accordance with the invention, by employing a processor which processes the incoming data frames in sequential manner to create outgoing data frames, a processor of reduced capability and complexity is required.

Thus it is possible in accordance with the invention to employ gate arrays for implementing the processor. These have the advantage of simplicity and speed of development of a correct logic design. Whilst it would be possible to employ an application specific integrated circuit (ASIC) to implement the processor, it is preferred to employ one or more programmable gate arrays (e.g.

Plessey Electronically Reconfigurable Array (ERA)) which are arrays which are configured upon power up by a software algorithm stored in an external memory.

As preferred a first programmable gate array (RXLCA) is employed to carry out a receive function of accepting incoming data frames, storing the frames in a buffer store and then transferring the data content of the frames to a shared memory store external to the gate array. A second LCA (TXLCA) is employed to carry out a frame out function of taking information from the shared memory store, formatting data from and transmitting the frame in the correct time slot of the TDM frame. As preferred one or more LCA (ATTLCA, INLCA, OUTLCA) are provided for control of the shared memory store and interfacing to a host processor.

In more detail, an interface means to an external line comprises a peripheral card controller (PCC). The PCC provides to RXLCA a 2Mbit/s signal, consisting of a frame based 32 timeslots each of 8 bits. Each timeslot is an HDLC channel and is totally independent of the others. For each channel RXLCA must perform the HDLC functions of flag detection, message detection, bit unstuffing, CRC and abort detection passing the message bytes and error information onto shared memory. Similarily TXLCA receives messages bytes from shared memory and must transmit them to the PCC, in the appropriate channel contiguous with Flags, performing bit stuffing and CRC generation. ATTLCA provides the interface to the host processor via a Fifo and Shared Memory storing of the received messages into assigned buffers and reading the transmit messages out from transmit buffers.Each LCA is synchronised to the 2M speech frame by a signal derived from the frame sync pulse provided by the PCC.

The LCA design operates on a single timeslot/channel basis and each channel of the TDM system is processed in turn ie CHO,CH1 etc. Each frame contains 32 channels CHO- > Ch3l. Each channel contains 8 bits of data specific to that channel. A "message" on any channel may be several bytes long, therefore, it will take several frames to receive/transmit the message as only 8 bits per channel is contained within one frame. The design uses several counters and state machines to control the processing of information. Each TDM channel is independent of any other and therefore, the state of each TDM channel is unique ie CHO may be out of service while CH1 is receiving a message. Due to the unique channel status, it is necessary to store the state of each channel.When processing of a current channel (CHO) is complete its status is stored away so that it may be retrieved in the next frame for CHO. Having retrieved the previous channels status, the processor will know what state CHO is in and what to do with the new data it is to receive. The status data is stored in a scratch pad area of memory known as the status store. The status store holds state data for all 32 receiver and transmitter channels.

Thus, the processor according to the invention preferably includes means for selectively enabling/disabling individual channels.

For any given timeslot/channel, the processor has a set sequence of operations that are always performed. A timeslot/channel is subdivided into 8 bits and these operations are executed at specific bits within the timeslot. Whilst all operations are performed on a TDM channel by channel basis, status accesses are made for either the previous or following channel since it is necessary to know what state a channel is in just prior to that channel being processed. A progammable logic array (PLA) is used to ensure that all status store accesses are made to the correct address for an individual LCA access. The channel status must be read, modified and written back to the same address for that channel. An 8 bit counter generates an address for the read access and another address for the write access.The PLA maps both addresses to the same location in the status store, and issues control signals appropriately.

Brief Description of The Drawings A preferred embodiment of the invention will now be described with reference to the accompanying drawings, wherein: Figure 1 is a schematic view of a switch located at a junction between a multiplicity of lines carrying data in a TDM system; Figure 2 is block diagrammatic view of a message switching unit (MSU); and Figure 3 is a more detailed block diagram of the MSU; and Figures 4, 5 and 6 are block diagrams of a multiple HDLC processor in accordance with the invention formed by programmable gate arrays (LCA); Figures 7 to 11 are block diagrams of programmable gate arrays (LCA) employed in this invention; and Figures 12 and 13 are timing tables for the LCA.

Description of the Preferred Embodiment Referring now to the MSU shown in Figure 3, it is based on a Motorola 68000 microprocessor 30 running at 16MHz. Five programmable gate arrays (LCA) (32) are used to handle 32 channel HDLC. The MSU is equipped with a serial synchronous communication control 34 which forms the interface with a subsystem control processor (not shown) and external telecommunications lines.

The MSU has on board RAM/ EPROM 36 and an area of shared memory 38 for communication between the processor and the LCA. The MSU is equipped with an RS422 type asynchronous serial interface 40, a programmable timer 42 and a watchdog timer 44.

Referring now also to Figures 4, 5, and 6 which show the LCA configuration in more detail, they comprise the following main items: RX/TX LCA 60: This contains 2 LCA 61,62. RXLCA 61 receives HDLC serial message data from the PCC, removes non-data frame information and checks and passes the data onto Block 68. The other, TXLCA 62 adds non-data information to the data from Block 68 and transmits it to the PCC.

STATUS STORE ADDRESSING CONTROL 63: This generates addresses for the status store so each LCA can read/write their operational data to/from the status store at the correct time within the frame. A PLA uses an 8-bit counter to determine to which LCA the address relates.

STATUS STORE 64: This contains five 8-bit 32K srams to provide 40-bit wide status data storage. Only 128 locations are used by 4 LCAs (the fifth LCA sharing the locations of 2 others). This gives each LCA 32 locations for operation of 32 channels.

FIFO 66: This is a 512 x 16-bit FIFO which reports "the process state" to the micro 30. The FIFO reports information for both receiver and transmitter for all 32 channels.

LCA DATA HANDLING AND CONTROL 68 : This brings TDM channels into or out of service. It reads data from shared memory and passes it onto block 60 to be transmitted to the PCC. Similarly it also writes data it receives from block 60 into shared memory.

SHARED MEMORY ACCESS CONTROL 70 (Fig. 3): This schedules shared memory accesses between the processor and the LCA. Access is normally set in favour of the micro. However, this does not prevent the LCA gaining access in its alloted period.

SHARED MEMORY 38 (Fig. 3): This is 64kbyte memory and data buffers which interface to the processor and the LCA.

The processor gains access to shared memory by asserting a valid address and address strobe. If the LCA is not already accessing shared memory the processor has access. The LCA gains access to shared memory by asserting a control line DMMD (active low). From the time the LCA asserts DMMD it waits 500ns (2MHz cycle) before it drives the bus. This 500ns will always be sufficient for the micro to have completed its cycle. If the LCA has access to shared ram and the micro tries to access the same area, the cycle will be started but the micro will insert wait states until the LCA negates DMMD. At this point, the micro will continue the cycle and eventually recognise DTACK SYNCHRONOUS I/O TRANSFER CONTROL 34 (PERIPHERAL CARD CONTROLLER): This is the I/O highway between the MSU and the sub system control processor.An arbitration circuit is used to enable the processor or the DMA to become the bus master.

The MSU is able to communicate with the system via a serial link. The processor places data to be transmitted in I/O ram. The processor informs a DMA (Direct Memory Access) of the size of data to be transmitted. The DMA requests the I/O data and address bus, chip selects an ADLC (automatic data link controller) and ram so the ADLC is loaded (in parallel) with data from ram. The data is converted into a serial format and transmitted to the PCC to be inserted into the serial stream to the system.

The ADLC automatically generates and detects the opening and closing flags, ie 01111110. During idle times between messages the ADLC transmits a continuous stream of flags. The contents of messages, ie length bytes, message bytes and check bytes are automatically checked by the ADLC for bytes which contain more than 5 consective l's. The ADLC transmit function automatically inserts zeros such that the only string of bits which contain more than 5 ones are the opening and closing flags. The ADLC receiver uses the flags to synchronise to the incoming data and automatically removes the zeros inserted by the transmitter.

INTERRUPT PRIORITISATION 72: This prioritises the MSU interrupts before presenting them to the processor.

WATCHDOG TIMER 44: This provides a watchdog timer and MSU reset function.

CLOCK GENERATION 42: This contains clock generation circuitry providing 16MHz and 2MHz clocks.

ASYNC RS422 I/F 40: This, man/machine interface allows the MSU to be accessed via a terminal.

CENTRAL PROCESSING UNIT 30: This also contains associated control signals/data buffers for the standard memory.

The processor is capable of executing 2 types of cycle, ie synchronous and asynchronous. A synchronous cycle is referred to as a 6800 cycle and an asynchronous cycle is referred to as a 68000 cycle and the cycle is independent of the processor clock. The processor accesses shared memory, standard RAM, EPROM and the DUART on an asynchronous cycle. The ADLC, DMA and DMA RAM are accessed on a synchronous cycle.

STANDARD MEMORY 36: This contains 8 memory chips providing 4 blocks of 64kbytes. One block of 64kbytes is dedicated to EPROM.

LCA 72: Controls interrupts to the processor providing a prioritised structure.

There are 4 devices that can interrupt the microprocessor: DUART (highest priority); ATTLCA; ADLC; DMA (lowest priority).

The DUART can be programmed such that signals on the input port can generate an interrupt. The DUART asserts its interrupt request line, the microprocessor will read the DUARTs status register to determine the cause of the interrupt request.

LCA 74: Contains circuitry to generate a DTACK signal to the processor from 5 external devices: standard memory, shared memory, DUART, FIFO and the watchdog timer.

The processor is informed of data transfers during a 68000 cycle when external circuits assert a DTACK signal to the processor.

There are 5 external devices which do not have a dedicated DTACK output and therefore employ additional circuits to produce a DTACK.

LCA 76: Provides a BUS ERROR signal to the processor if a write to EPROM or read/write to an unmapped address is initiated.

Programmable Gate Arrays A first programmable gate array (RXLCA) is employed to carry out a receive function of accepting incoming data frames, storing the frames in a buffer store and then transferring the data content of the frames to a shared memory store external to the gate array. A second LCA (TXLCA) is employed to carry out a frame out function of taking information from the shared memory store, formatting a data from and transmitting the frame in the correct time slot of the TDM frame. As preferred one or more LCA (ATTLCA, INLCA, OUTLCA) are provided for control of the shared memory store and interfacing to a host processor.

In more detail, an interface means to an external line comprises a peripheral card controller (PCC). The PCC provides to RXLCA a 2Mbit/s signal, consisting of a frame based 32 timeslots each of 8 bits. Each timeslot is an HDLC channel and is totally independent of the others. For each channel RXLCA must perform the HDLC functions of flag detection, message detection, bit unstuffing, CRC and abort detection passing the message bytes and error information onto shared memory. Similarily TXLCA receives messages bytes from shared memory and must transmit them to the PCC, in the appropriate channel contiguous with Flags, performing bit stuffing and CRC generation. ATTLCA provides the interface to the host processor via a Fifo and Shared Memory storing of the received messages into assigned buffers and reading the transmit messages out from transmit buffers.Each LCA is synchronised to the 2M speech frame by a signal derived from the frame sync pulse provided by the PCC.

The LCA design operates on a single timeslot/channel basis and each channel of this TDM system is processed in turn i.e. CHO,CH1 etc. Each frame contains 32 channels CHO-Ch31. Each channel contains 8 bits of data specific to that channel. A "message" on any channel may be several bytes long, therefore, it will take several frames to receive/transmit the message as only 8 bits per channel is contained within one frame. The design uses several counters and state machines to control the processing of information. Each TDM channel is independent of any other and therefore, the state of each TDN channel is unique i.e. CHO may be out of service while CH1 is receiving a message. Due to the unique channel status, it is necessary to store the state of each channel.When processing of a current channel (CHO) is complete its status is stored away so that it may be retrieved in the next frame for CHO. Having retrieved the previous channels status, the processor will know what state CHO is in and what to do with the new data it is to receive. The status data is stored in a scratch pad area of memory known as the status store. The status store holds state data for all 32 receiver and transmitter channels (See Figure 12).

Thus, the processor according to the invention preferably includes means for selectively enabling/disabling individual channels.

For any given timeslot/channel, the processor has a set sequence of operations that are always performed. A timeslot/channel is subdivided into 8 bits and these operations are executed at specific bits within the time slot. Whilst all operations are performed on a TDM channel by channel basis, status accesses are made for either the previous or following channel, since it is necessary to know what state a channel is in just prior to the channel being processed. A programmable logic array (PLA) is used to ensure that all status store accesses are made to the correct address for an individual LCA access. The channel status must be read, modified and written back to the same address for that channel. An 8 bit counter generates an address for the read access and another address for the write access.The PLA maps both addresses to the same location in the status store, and issues control signals appropriately.

The LCA are RAM based devices which are user re-programmable. Their operation is therefore dependent on how the user configures them. To service each of the 32 channels the LCA allocate a timeslot in every frame to each channel. Each Timeslot is divided into 8 timeslot bits (TSBits for short) so each LCA can carry out its required operations at the correct time without corrupting anothers.

The LCA are divided as follows Block 60: Receives and transmits serial HDLC data streams.

Block 68: Reads and writes valid data bytes from the shared memory. Block 68 is shown in more detail in Figure 5 as comprising ATTLCA 70, INLCA 72, OUTLCA 74.

Blocks 63, 64, 65: Reads and writes LCA operational states for a particular timeslot to and from Status Store memory.

Block 66: Reports events in LCA operation to the processor.

To perform their requested function, the LCA must first be loaded with their configuration data. This is read out of the shared memory by ATTLCA 70 (See Fig. 5) as soon as the host invokes the configuration sequence explained below: LRXDAT, LTXDAT, LINDAT and LOUTDAT are used to carry the configuration data and control signals between the LCAs.

On power-up the LCAs automaticaly try and configure themselves, driving DONPROGL low. However, they are prevented from doingso as LRESET will initially be active low because RESETL will have forced the DUARTs OP pins high. This ensures the LCAs do not configure using invalid data, thereby setting up signal contention.

This also allows the host operating system to boot up on thecard.

The system can download the configuration code via the PCC and DMA into the I/O RAM. The configuration data is moved from the I/O RAM into the Standard memory 36, before finally being written into shared RAM 38.

LCA RX/TX - Block 60 This Block consists of 2 LCAs, RXLCA 61 and TXLCA 62 (Fig. 6). Serial HDLC data stream is received from the PCC 34 via the signal SPAOUT and unwanted frame information removed by RXLCA.

The resultant data bytes are passed onto Block 68 via the CBUS.

RXLCA reports its operational status to Block 68 via LRXDAT and ERRL1. At the end of a message the result of RXLCA CRC check and any Abort detection are reported to Block 68 as a data byte along with the CRC calculated by RXLCA via CBUS.

For transmission, TXLCA reads data bytes from Block 68 via the CBUS and adds frame information accordingly before transmitting the serial HDLC data stream to the PCC via the signal SPAIN. TXLCA reports when it has completed transmitting a data byte in the current Timeslot to Block 68 via the signal ERRL3.

Status Store Addressing Control - Block 63 Four LCA have access to the Status Store RAM. The fifth, ATTLCA 70, shares data bits of locations dedicated to INLCA and OUTLCA. The Status Store is organised as 32k by 40 bits. However the design only allows access to 128 of those locations, i.e. 32 locations for each of the 4 LCAs. Addressing is controlled by an 8 bit counter synchronous to the PCC Speech data. Each of the 256 bits per frame of the PCC speech output has a unique counter value.

A PLA provides a look-up tabel to map those counter values onto appropriate addresses such that different counter values may access the same address. The status store PLA also provides the read/write and output enable signals to the RAM and enable and direction signals to the LCA Bus Transceivers of Block 65, giving Block 68 access to the lower 31 data bits of CBUS. It is the responsibility of the LCA design to avoid data bus contention between the 4 LCA wrt the status store.

Status Store - Block 64 The Status Store is composed of fixe 32k x 8bit RAMs to provide the 40 bit data on CBUs (0:39). Address control 63 provides the address via EBUS and the read/write (RWSTORE) and enable (DESTOREL) control signals.

FIFO - Block 66 Block 68 is able to communicate to the processorvia a 512 by 16 FIFO. The data is provided using various signals and L6 to L15 and is loaded in by a low going pulse on FIFLOAD. On receiving a data word, the FIFO interrupts the processor to request attention.

LCAs ATTLCA 70, INLCA 72 and OUTLCA 74 - Block 68 Block 68 basically performs the following functions when configured: a. Reads received data bytes from Block 60 via CBUS and saves them into the specific area in shared memory.

b. Reads data bytes from a specific area in shared memory and transfers them to Block 60 for transmission, via CBUS.

c. Reports conditions on transmission or receipt of a message.

d. Brings channels into service and aborts transmission.

e. INLCA is used to take care of the incoming data, while OUTLCA takes care of the outgoing data. ATTLCA interacts with both sides and reports status information to the host via the FIFO. ATTLCA monitors the signal ATTENL to check when the host wants a certain function carried out. This function is defined by the Interrupt Control Byte. ATTLCA can either bring a stated channel into service (i.e. ready to transmit and receive data) or abort transmission.

f. ATTLCA also provdes the upper address lines to the share memory so INLCA or OUTLCA can access the shared memory. It can take full control of the addreess bus by inhibiting INLCA via RESETIC and OUTLCA via RESETOG. ATTLCA generates the control signals to access the 64kbyte memory shared with the microprocessor. ATTLCA requests access to the memory via the arbitration circuit in Block 70 by asserting DMND. It waits one 2MHz cycle before driving its LBUS address and BBUS data lines. During this time the arbitration circuitry has to interrupt the processor and stop it accessing shared memory (if at all) before driving the signal LCSEL. This multiplexes the RAM address (TBUS) to LBUS and RAM data bus (MBUS) to BBUS from DBUS. ATTLCA negates DMND when the access is complete allowing the processor access. Only word access is available.

All 3 LCA access the Status Store to save and read back their internal functional states on a per channel basis to service all the channels in each frame. To do this, the LCA read and write information onto LBUS and BBUS and Block EB3 interfaces the information to the Status Store.

RXLCA 60 RXLCA receives a 2Mbit/s data stream. This stream contains 32 x 64kbit/s streams. The 32 streams are time division multiplexed in timeslots of 8 bits in length and each 64kbit/s stream carries an independent HDLC link. During a timeslot, the LCA performs the function of receiving the HDLC link. This consists of searching for flags and aborts, error detection and bit-unstuffing. At the end of each timeslot, the status of the HDLC link is output so it may be stored by the status store and the status of the following timeslot read from the store. If a HDLC byte has been received or a frame has ended, the data orstatus byte is written from the LCA during the following timeslot.

The LCA receives the following signals: SPAOUT is a 2mHz serial data stream. The data is presented as 32 timeslots of 8 bits in length. Each timeslot carries an HDLC link.

8MHz is a clock with a nominal 50% duty cycle. A rising edge nominally occurs simultaneously with changes in SPAOUT.

LTXFSP (Frame Synchronisation Pulse) is a 125ns pulse used by the LCA to synchronize to the data carried on SPAOUT. During normal operation the signal is true from 125ns to 250ns after the beginning of bit 0 of TSO of SPAOUT data. The LCA is in active prior to the first LTXFSP following the LRESST going false.

The following output signals are produced by the RXLCA.

L1DATA (LRXDAT1) and ERRL1 inform INLCA of the status of the previous timeslots HDLC link. They are valid during timeslot bit 3 and the following coding is used.

L1DATA is true when information on DOO to D07 is valid (Frame Data or End of Frame Status).

ERRL1 is true when the device is currently receiving frame data.

LCA States The LCA operates as a finite state machine. At the beginning of each timeslot, the LCA reads the relevant status data from the status store. The status data is modified during the timeslot and returned to the status store at the end.

During each timeslot the LCA may be in one of 3 states (0, 1, 2). Initially the LCA is in state 0.

State 0, Initial State : No complete flag has yet been detected and therefore the device is not synchronized onto the HDLC byte boundaries.

State 1 : The device is synchronized to the HDLC byte boundaries.

The last byte the device received was a flag and it is currently receiving a bit stream which would be a flag.

State 2 The device has received a flag followed by non-flag bits.

This means the device is currently receiving a HDLC frame.

The TS status will become 0 when an ABORT is received. The TS status will become 1 when a FLAG is received. If previous state was 0, the flag is used to synchronize the LCA to the start of the timeslots HDLC byte boundary. If previous status is 1 (the last byte reeived was a flag) the flag indicates nothing new. Repeated flags are transmitted to fill gaps between data frames. If the previous state is 2, the flag indicates the end of a frame and an End of Frame Status byte is produced.

HDLC Data Format Data on a HDLC channel is transmitted in frames. A frame begins with a flag and ends with another flag. The 16 bits immediately preceding a flag contain a frame check sequence. A frame may be aborted by transmission of an abort character. No data in one of these frames is valid. When no data is being transmitted continuous flags are transmitted.

a. Flag A flag comprises a zero, followed by 6 ones, followed by a zero (01111110). A frame is preced and followed by one or more flags.

b. Abort An abort comprises 7 or more consecutive ones.

c. Data : Data is transmitted in frames. Each frame begins and ends with a flag. Data begins immediately following the end of the beginning flag and ends immediately before the beginning of the ending flag. The last 16 data bits of a frame contain a CRC Code. To avoid data being msitaken for a flag or abort a zero is inserted following 5 consecutive ones. Because of the zero insertion (bit-stuffing) HDLC bytes are unlikely to be aligned to TS bytes.

d. Frame Check Sequence The Frame Check Sequence occupies the 16 bits immediately preceding the final flag of a frame. It is implemented as a Cyclic Redundancy Check (CRC) using the polynominal ((x**12) + (x**5) +1).

The RXLCA 61 contains the following lower level circuits, as shown in Fig. 8 a. INCTR gives a timing reference to the rest of the device.

b. SEQCONT produces the clock signals for the rest of the device.

c. L1CNT provides the control and status signals used by the device.

LOGCONT decides on the significance of this data and sends signals to the restof the control circuitry to clock data into the data and CRC registers and to change the contents of the status registers in response to the newly received bit.

STATCNT holds the bit number of the bit (within an HDLC byte) currently being received. Bit O is the first bit received and the least significant.

ONESCNT hold the number of consecutive ones which has been received prior to the current bit.

STATREG holds thestate (see section 4.9) which the device is in during the current timeslot.

STATIO writes and reads status data from the status store.

d. L1DATA stores the received data and writes completed bytes as required. This curcuit contains DATREG, DATAIO, DATAMUX and MSGDAT.

DATREG stores incompletely received data bytes. DATAIO writes and reads incomplete data bytes toand from the status store.

DATAIO also writes frame status and received bytes to INLCA. DATAMUX selects the data to be presented to DATAIO from one of 3 sources; the register holding a completely received byte, the register holding the end of frame status or the register holding an incomplete byte.

MSGDAT holds the end of frame status.

e. L1CRC detects errors in the frame data using the FCS (Frame Check Sequence) which is implemented as a CRC (Cyclic Redundancy Check). The FCS occupies the 16 bits immediately before the end of frame flag. The contents of the CRC register at the end of frame flag are compared with the expected value. If they differ an error is reported.

CRCIO writes and reads status from the status store. CRC16 regenerates the CRC from the received data. ERRDET compares the output of CRC16 at the end of a frame with the expected value.

INLCA 72 circuit description (Figure 9) INLCA contains the following functions: a. COUNTER: This maintains a timeslot bit count synchronised to the frame sync pulse LTXFSP and generates the timing signals for the following logic.

b. ADDRESS: This block generates the least-significant address bits for most shared memory accesses. These LSBs indicate which word in a message buffer is to be accessed. The MSBs, indicating buffer number, are generated by ATTLCA to simpify INLCA, the LSBs for the interrupt control byte and reset vector reads are also generated by ATTLCA. The address register in ADDRESS doubles as a state machine such that the address being accessed indicates what function is being performed. Hence the signal LOADADDRIC is generated by the ADDRESS block.

c. INDATA: This block receives paralle data and control signals from RXLCA. INDATA generates 'address increment' and 'end of message' control signals. The parallel data is presented to the low-order data bus for transfer to shared RAM. INDATA also extracts error flags from the data and passes them to the FIFO.

The accumulation of 2 x 8 bit bytes into a 16-bit word for writing to RAM is achieved by also saving the 8-bit data in status RDM. A subsequent status read transfers the data into an 8-bit register on the high-order data bus.

Note 1: Although this 8-bit register really belongs in INLCA it was moved to ATTLCA to reduce chip occupancy.

2: This accumulation technique only works correctly if an incoming message is an even number of bytes long. However, in the case of an odd-length message it is only the last byte which is corrupted, and as this is the CRC, which has already been checked, no real data is corrupted. If needed for debugging purposes, the last byte can still be retrieved from memory: it will have been written to the low-order byte rather than the high-order byte.

d. DIO This block contains the bidirectional data bus I/O pads.

Only data bus bits 0 to 11 are used by INLCA. The upper and lower bytes have independent 3-state enable since ATTLCA shares the incoming 16 bit word accumulation with INDATA.

ATTLCA 70 Circuit Description (Figure 10) : ATTLCA interfaces to the shared memory and handles the channel attention mechanism. It maintains the upper address bits for the incoming and outgoing channels and works with the incoming and outgoing LCAs: OUTLCA and INLCA.

ATTLCA contains the following functions : a. COUNTER This maintains a timeslot bit count synchronised to the frame sync pulse LTXFSP and generates the timing signals for the following logic. It also counts timeslots, detects synchronisation errors, generates the bus request signal DMND and monitors the channel attention input ATTENL.

b. ADDRESS This block generates the most-significant address bits for all shared memory accesses. These MSBs indicate which buffer is to be accessed. ATTLCA also generates the LSBs of the bus for interrupt control byte and reset vector reads. By testing for the NUll address, this block detects in-service/out-of-service for each channel.

c. ATTENTION This block is used to process the interrupt control byte which is read as part of the channel attention mechanism.

It causes the channel reset vector for the indicated channel to be read.

d. DBUFF This block contains the data bus I/O pads and works with INLCA to accumulate 16 bit data words.

OUTLCA 74 circuit description (Figure 11) OUTLCA forms the interface between the shared memory, FIFO and the outgoing parallel-to-HDLC converter TXLCA. All timeslot bit numbers in this description refer to the incoming side for standardisation.

OUTLCA contains the following functions: a. COUNTER This maintains a timeslot bit count synchronised to the frame sync pulse LTXFSP and generates the timing signals for the following logic.

b. ADDRESS This block generates the least-significant address bits for most shared memory accesses. These LSBs indicate which word in a message buffer is to be accessed. The MSBs, indicating buffer number, are generated by ATTLCA. To simplify 0UTLCA, the LSBs for the interrupt control byte and reset vector reads are also generated by ATTLCA. The outgoing address counter in ADDRESS doubles as a state machine such that the address being accessed indicates what function is being performed. Hence signals such as LOADLEN and SAVELEN are generated by the ADDRESS block.

c. BYTECNT This block is the byte count monitor controlling the number of bytes to be transmitted. The number of bytes is loaded from memory into a register which is thereafter maintained through the status store. To detect end of message, the value in this register is compared with the outgoing address counter (in ADDRESS) which doubles as the actual byte counterand the signal EQH is generated when they are equal.

Note: Since the message buffer format has an 8-byte header before the data, the 'length' loaded into the register must be 8 btes more than the actual required message length.

After the message is transmitted, OUTLCA sets the 'transmit buffer empty' flag in memory. This flag is in the same 16-bit word as the length. To avoid corrupting the length field, the length stored in the register is written back to memory at the same time.

d. OUTDATA : This block takes data from the shared memory and routes it to TXLCA for transmission. It takes the EQH signal from BYTECNT (which indicated that the message has been transmitted) and the ERR3 signal from TXLCA (which tells OUTLCA to repeat the last byte since bit-stuffing delays prevented TXLCA from using it). From these inputs OUTDATA derives 'address increment' and 'end of message' control signals for OUTLCA use and a 'valid data' signal to indicate the start and end of message to TXLCA.

The function of OUTDATA is to read a 16 bit word from shared RAM, select either the high or low byte depending on the least-significant bit of the outgoing address counter, select either this byte or the previous byte depending on the state of ERR3. This byte is saved to status RAM to form the 'previous' byte for the next frame.

By the time OUTLCA has performed all this processing, it is far too late to send it to TXLCA. For this reason the 'valid data' signal described above is saved to status RAM along with the data and both are passed to TXLCA one frame later. The data is not passed via 0UTLCA; instead TXLCA is designed to 'read over OUTLCA shoulder' during OUTLCAs outgoing status read and thereby obtain the information directly from status RAM.

e. DIO : This block contains the data bus I/O pads. All 16 pads are bidirectional. All input data is clocked in the IOBs; this allows status read data to be held until needed. Where direct data input is required (on shared memory reads) this is achieved by clocking the IOBs so they appear almost transparent to the data (there is of course an inherent delay in this method which is allowed for in the design).

This uses fewer LCA resources than using the genuine 'direct input' option of the IOBs.

All output data is also clocked by the IOBs, allowing the LCA to get on with processing data for the next bit time.

Data is clocked out at the start of each bit time.

TXLCA 62 circuit description (Figure 11) TXLCA forms the interface between OUTLCA (outgoing memory interface LCA) and theserial output stream. TXLCA performs parallel-to-serial conversion, bit stuffingand the generation of flags, abort and CRCs.

TXLCA contains the following functions a. COUNTER This maintains a timeslot bit count synchronised to the frame sync pulse LTXFSP and generates the timing signals for the following logic. COUNTER also generates ERRL3 which informs OUTLCA whether or not bit stuffing delays have caused TXLCA to slip an octet, in which case OUTLCA must retransmit the previous data byte.

b. STATREAD Parallel information does not pass directly from OUTLCA to TXLCA. Instead the data passes via the status RAM and enters TXLCA by allowing TXLCA to read the status bus during OUTLCA status read. This mechanism it employed partly for functional and timing reasons OUTLCA must store the data in status RAM anyway) and partly to economise on peripheral interconnection. STATREAD latches parallel data and the 'valid data' signal L3DATA from the status bus during OUTLCA status read and passes the data to the parallel-to-serial shift register.

c. SHFITREG: This block performs parallel-to-serial conversion for transmitted data. It contains a shift register for the conversion and an 8-bit data buffer to hold the next data byte in readiness for when the shift register is empty.

SHIFTREG extracts control information from L3DATA and the data byte and passes this to the TXLCA state machine.

SHIFTREG also indicates when the shift register is empty.

The contents of the shift registerare saved in status RAM at the end of each timeslot, but the contents of the buffer register are updated from OUTLCA (via the status RAM) every timeslot since there are insufficient status RAM bits available in the current architecture. This block also performs flag and abort generation.

d. CRCGEN This block calculates the CRC for the message from the ouptut of the shift register. When instructed to do so, CRCGEN inserts the calculated CRC into the serial stream.

The CRC bits are saved in status RAM at the end of each timeslot.

e. BITSTUFF If enabled, this block counts the number of consecutive l's in the serial stream and upon reaching a count of 5 inserts a zero bit. The signal STCLKEN is generated to disable the shift register and CRC generatorfor 1 bit to prevent data loss. The 1's count is saved in status RAM at the end of each timeslot.

f. STATE This block controls the message sequence of TXLCA, causing flag/abort generation, CRC insertion and disabling bit-stuffing as appropriate. It is controlled by signals derived from the 'valid data' signal L3DATA and the parallel data.

g. Discrete logic: The only ligic in the top level block is output D-type C1 which retimes the serial output, aligning it with the timeslot bit boundaries (see section 4.21.2).

Incoming Message HDLC Operation The Rx functions are performed by RXLCA and INLCA associated with a part of ATTLCA on a per channel basis.

RXLCA Involvement After configuration RXLCA looks for a 'O' in the incoming channel data and checks the next 7 bits are 1111110, i.e. a flag.

Since HDLC bytes are not necessarily aligned to Timeslots then the Flag may bespread across 2 timeslots. When a complete flag has been received RXLCA uses the flag boundary to receive and recognise the firstand subsequent bytes of an incoming message. The incoming message is bit unstuffed and CRC checked. Complete bytes aresent to INLCA via CBUS (0:7) during bit 3 of RXLCAs Timeslot. In Bit 3 LRXDAT and ERRL1 are also used to report to INLCA the event occurring in RXLCA and when RXLCA has a byte to transfer. LRXDAT high and ERRL1 high indicates a message byte is available on CBUS. LRXDAT high and ERRL1 low indicates an 'end of message' status byte is available on CBUS. LRXDAT low and ERRLllow indicates no frame has been detected and therefore no data is available on CBUS. LRXLCA low and ERRL1 high indicates a frame is in progress but no data byte was completed during the timeslot.

At the start (bit O) of the timeslot RXLCA stores in the status store the following information: a. The value of the 16 bit CRC at the end of the previous timeslot via CBUS 8 (16:31).

b. The bits of an incomplete messsage byte received in the previous timeslot via CBUS (0:7).

c. The value of a 3 bit counter describing the bit position within the HDLC byte at the end of the previous timeslot via CBUS (8:10).

d. The status of the channel at the end of the previous timeslot via CBUS (14:15). This can be one of the following: i. Looking for Flag (state 0): this is the initial status after configuration and after loss of frame snchronisation. The LCA looks for the leading zero of the Flag and checks the subsequent 7 bits for a flag.

ii. Looking for Data (state 1): the position of the Timeslot boundary has been found by the reception of a flag and subsequent bytes are checked to find the start of a message, ie iii. Looking for EOM (state 2): the channel contains message bytes which are checked to find the end of the message, ie a flag or an abort.

At the end of timeslot the status store is read to retrieve the above information for the channel allocated to the next timeslot.

Due to bit stuffing the message need not be an integral number of bytes long so a flag or an abort (detected by 7 or more consecutive 'l's) indicating the end of the message is likely to be on a new timeslot boundary. At the end of a message, the 'end of message' status byte sent to INLCA indicate whether the CRC has failed oranabort has been detected.

INLCA/ATTLCA Involvement (Bringing receiver channels into service) Each channel is designated as being 'In Service' (IS) or 'Out of Service' (OOS). To describe this operation it is necessary to state some assumptions.

a. The S/W has written the channel number to be IS plus one to the Interrupt control byte (ICB) in shared RAM.

b. Rx CH:5 to be made IS. This is achieved by instructing the DUART to assert the O/P signal ATTENL (low).

c. ATTENL has been asserted arbitrary in TS3 (CH:3) bit5, just prior to the next bitl time. Refer to figure 5.1 for information on inter timeslot access structure.

The sequence of events to bring a channel IS is depicted in figure 5.2 on a TS basis. At the next bit 1 time (TS4 bit 1) ATTLCA reads the ICB. At this stage ATTLCAs address but point to the first buffer in shared RAM. The ICB will hold the value 6 and therefore nothing else will happen until the actual TS number equals the indicated channel, ie TS6. At TS6 bit6 ATTLCA signals to INLCA by asserting RESETIC (HIGH). This informs INLCA that ATTLCA will need to read the channel reset vector at the next bit 0 time. At TS7 bit 0 ATTLCA reads the appropriate vector from shared RAM. This vector points to a 'dummy buffer' whose link address (next buffer address) is the address of the first available buffer in a receiver buffer linked list set up by the F/W. This 'dummy buffer( is a mechanism required by the S/W.

Note: Figure 5.1 which details shared RAM and status store access shows that in bit 3 the RXLCA would write message bytes to INLCA.

However, in this instance the channel is out-of-service and is being in-serviced and therefore, INLCA ignores the byte written to it because RESETIC is high. RESETIC stays asserted from bit 6 to the following TS bit 6. At TS7 bit5, ATTLCA writes the buffer address to the status store whilst INLCA writes the value 8 to the status store.

The value 8 is an offset such that when the message bytes are stored, the first byte to be stored is stored in the first location after the buffer header information bytes. This is the last action in the current frme. By virtue that CH:5 has a buffer address in the status store as opposed to the null vector (FFFF) the logic knows that channel must now be IS.

RXLCA does not know if a channel is 'IS' or 'OOS'. RXLCA monitors the incoming serial 2M stream and indicates the state of the line to INLCA. INLCA decodes the state and takes the appropriate action, see section 4.7.

INLCA/ATTLCA Involvement (Receiving message bytes) (See Figure 13) The status store has been set up so the logic recognises CH:5 is IS, CH:5 is ready to receive message bytes in the next frame (n+1) where RXLCA will write the message byte to INLCA in TS6 bit 3.

INLCA holds the byte until it knows which address to store it in. In TS6 bit 6, ATTLCA and INLCA read the status store for CH:5 if ATTLCA has asserted ICOOS (low) indicating CH:5 is IS.

If during recepiton an 'end of message' status byte is received from RXLCA, INLCA points to the second location of the buffer to write the length of the message in the buffer. It asserts FIFOLOAD so the FIFO can report the message in that buffer. INLCA points to zero and hence instructs ATTLCA to load the link address from the first location of the buffer. ATTLCA uses this to point to the next buffer. At end of message is received at some stage in every buffer.

If at any time a link address is found to be FFFF, ATTLCA brings the channel OOS and any subsequent data from RXLCA is ignored.

Outgoing Message HDLC Operation The transmission of messages to the system is handled by OUTLCA/ATTLCA and TXLCA LCAs. The method is in some instances similar to the method used by INLCA/ATTLCA for reception and reference should be amde to that section if more detail is required.

OUTLCA/ATTLCA Involvement : As for Rx channels, Tx channels areall initially OOS and transmitting flags. ATTLCA/INLCAs internal address register point to the Interrupt Control Byte, waiting for the firm ware to assert ATTENL lowand invoke the channel attention mechanism and thus bring a channel IS. The Interrupt control byte is read on the next bit 1 and will contain the channel number of the channel to be IS'ed. This determines which reset vector ATTLCA should read. ATTLCA waits until the timeslot allocated to that channel arrives and takes control of all the LBUS address lines (disabling OUTLCAs generation of the lower lines via RESETOG high) to read the reset vector in bit 7, ie when ATTLCA/OUTLCA normally access shared memory. The reset vector is saved into status store and read back in subsequent frames at the timeslot allocated to that channel.

The F/W sets up the reset vector for that channel so it points to a dummy buffer. ATTLCA continually read the Empty Buffer Flag within the header of each Tx buffer and proceeds to the next buffer if it is true by reading the link address of the first buffer.

As the empty flag in the dummy buffer is set true (high) in effect the LCAs loop around the dummy buffer. This is the IS'ed state. The dummy buffer will be different per IS'ed channel.

The firmware can attach valid data buffers onto this loop by inserting the address of each buffer in the link address of the previous buffer. This means the dummy buffer points to the first valid buffer and the last buffer points to the first buffer.

OUTLCA/ATTLCA will read and examine each empty flag of each buffer and loop around as all these will be set.

To transmit the buffer(s) the firmware has to set the empty flag(s) to false. As for INLCA/ATTLCA ATTLCA points to the buffer, while OUTLCA points to the location within the buffer. OUTLCA/ATTLCA read the message length from the header of each non-empty buffer and hold it in OUTLCA and status store (when operating on other channels). The LCAs read the data bytes from the buffer in shared memory and pass it onto TXLCA via ATTLCA/OUTLCA status store read/write operation.

This continues until the number of bytes read equals the message length. OUTLCA instructs ATTLCA to read the link addres and hence point to the next buffer, by asserting LOADOG high.

TXLCA Involvement TXLCA start a new times lot 1/2 way throughbit 3 of RXLCAs timeslot. However this is only after it has read its functional states for the new timeslot from status store 1/2 way through bit 1 and written the functional states in the previous timeslotat the beginning of bit 3.

ATTLCA/OUTLCA pass data to TXLCA for transmission by writing the data to its status store locations. TXLCA latches CBUS (7:14) when ATTLCA/OUTLCA read their status store locations in bit 2.

CBUS (7) is used to inform TXLCA if the byte on CBUS (:14) is a flag/abort (if high) or a valid data byte (if low).

If the shift register in TXLCA is empty, ie contains zeros, the new byte received in the previous TXLCA timeslot, is latched into the shift register and shifted. If 5 consecutive ones of a valid data byte has already been shifted and the next bit is also 1, the shifting is paused so a bit 0 can bestuffed after the 5 ones.

Sometimes bitstuffing can mean TXLCA does not have time to load the new byte received from ATTLCA/OUTLCA in the previous TXLCA timeslot, therefore TXLCA reports this to ATTLCA/OUTLCA via ERRL3. If ERRL3 goes active during the timeslot the new byte is loaded.

Claims (10)

1. A telecommunications switch for switching TDM signals between incoming and outgoing lines, the TDM signals comprising data frames in respective time slots, the switch including a processor and a memory store, the processor having a single processing channel including receiver means for receiving incoming data frames, sequentially extracting the data therefrom and transferring such data to the memory store, and said single processing channel including transmit means for sequentially reading the data in the memory store and formatting such data into data frames for sending on the outgoing line.

2. A switch as claimed in Claim 1 wherein the processor is implemented with one or more programmable gate arrays.

3. A switch as claimed in Claim 1 or 2 wherein the processor means is arranged to process data frames in HDLC format.

4. A switch as claimed in any preceding claim wherein the receiver means includes data buffer means for temporarily storing extracted data.

5. A switch as claimed in any preceding claim wherein the memory store includes a plurality of data buffers for respective/TDM channels, said receiver means being arranged to write data from the respective channels into the respective data buffers, and the switch including mapping means for defining a corresponence between the data buffers and the outgoing TDM channels.

6. A switch as claimed in Claim 5 wherein the mapping means is operative to change an address pointer to change the address of a buffer from a receive address to a transmit address.

7. A switch as claimed in Claim 2 including a plurality of gate arrays, and a status store including channel locations for each TDM channel and a set of gate array address locations with each channel address location, each gate array location storing status information wherein in order to carry out their alloted tasks each gate array accesses its respective location in order to recall its previous status prior to dealing with a channel, and each gate array is arranged to write a revised status to the location when it has finished processing that channel.

8. A switch as claimed in Claim 2 wherein the or each gate array is arranged to carry out a series of operations during each TDM channel, and including counting means for defining a plurality of time slot bits within each channel according to which the operations are carried out.

9. A switch as claimed in any preceding claim including means for storing information as to whether a TDM channel is in service or out of service, and means for preventing the transmit means from operating during such TDM channel.

10. A telecommunications switch substantially as described with reference to the accompanying drawings.