GB2122783A - Apparatus and method for processing data arrays - Google Patents

Abstract

For speed in image processing it is advantageous to have one processor for each element of a data array which is to be processed. However arrays of processor cells become expensive when data arrays become large. An alternative is to scan a large data array with a small cell array but problems then arise where data elements needed in a partial scan are outside the current partial scan. In the apparatus described groups of processor cells 13 to 16 form a cell array, with similar groups, for scanning a data array, and to overcome the above mentioned problem, edge-signal stores 17 to 20 are provided. These stores hold signals relating to information in the data array just outside the current partial scan or processed information required for the next partial scan. In propagation processing time is saved by passing processed information from edge-signal stores in a leading edge of the cell array in scanning to edge-signal stores in the trailing edge by way of paths 48 and 49. <IMAGE>

Description

SPECIFICATION Apparatus and method for processing data arrays The present invention relates to an apparatus and method for processing two dimensional arrays of numbers, each number usually, but not necessarily, representing the intensity of a picture element (pixel) of an image to be processed.

Image processing has many different objects, for example recognition of objects represented by the image, clarification of an image and classification of objects within an image.

One image processing system, the CLIP 4 system, is described in a paper "Review of the CLIP Image-Processing System" by M. J. B. Duff, National Computer Conference, 1978. The system described in this paper comprises an array of 96x96 CLIP 4 cells. Each cell which is as shown in Figure 1 of this specification comprises a processor 10 which is controlled to carry out various Boolean functions by control signals applied to terminals 11, three single-bits of buffer memory A, B and C, a 32 by 1 bit RAM D and individually gated inputs 12 from neighbouring cells. Various gates and control terminals are also included as shown.

CLIP 4 cells are made in integrated circuit form with eight cells in each integrated circuit, the cells being arranged in two rows of four.

In this specification a cell comprises a plurality of input terminals, an output terminal for connection to the input terminals of other cells, a logical processor circuit, cell data-storage means, data input and output paths for connection to circuits external to an array and gating means for selectively interconnecting the input terminals, the data input and output paths, the processor circuit, the cell data-storage means and the output terminal, the processor circuit and the gating means being constructed to operate in accordance with control signals, in operation, applied to control terminals of the array. The processor circuit is preferably constructed to carry out Boolean operations, but other operations, such as arithmetic operations, may be carried out in addition, or instead.

Processing operations carried out by an array may comprise:~ (a) "Pointwise" where the operation carried out by each cell depends only on data relating to the point in an image corresponding to that cell.

The result of the operation is stored but no output is supplied to the cell output terminal.

(b) "Local" where inputs are received from other cells relating to the state prior to the operation of points they represent and the operation carried out by a cell depends on these inputs and data relating to the point corresponding to the cell. Again the result of the operation is stored but no modified output is supplied to the cell output terminal.

(c) "Global" or "propagation" where the signal at the output terminal of a cell after an operation depends at least partially on signals received from one or more other cells after the same operation has been carried out by such a cell or cells. A result for a processing operation is also obtained and stored.

According to the first aspect of the present invention there is provided apparatus for processing data held by a data array having at least a predetermined number of elements, comprising: an array of cells, as hereinbefore defined, in which the number of cells is substantially less than the predetermined number, the cells being interconnected systematically according to position in the cell array, control means adapted to scan the cell array across a data array by carrying out a number of successive scan cycles in which data is read from successive blocks of elements of the data array into the cell array, processed and read from the cell array to form a processed-data array, the control means supplying control signals for the cells, and a plurality of edge-signal stores interconnected with those cells along edges of the cell array contiguous, in a scan cycle, with parts of the data array which have been, or will be, scanned in other scan cycles, the edge-signal stores also being interconnected to transfer data in at least one direction, from edge-signal stores along at least one edge of the cell array to edge-signal stores, corresponding by position, along the opposite edge of the array, the control means being adapted to transfer, in each scan cycle, data between the edge-signal stores and elements of the data array which are contiguous with that part of the data array being processed in the current scan.

In "local" or "global" operations where the stored result of a processing operation depends on the value of the output of a neighbouring cell, apparatus according to the invention has a speed advantage because the outputs of those cells along a leading edge of the array in scanning can be transferred to the adjacent edge-signal stores and thence at the end of a scan cycle to the edgesignal stores along the trailing edge where they are then available for use in the next scan cycle.

Thus less data transfer to and from the array data storage means is required.

Another advantage of apparatus according to the invention is that while the advantages of scanning are obtained in that it is unnecessary to provide one logical processor circuit for each data element, or pixel, comparatively fast processing for a data array is also realized. Fast processing is achieved since in each scan cycle all the information for each cell is available either from its neighbouring cells or from the edge-signal stores.

Further, "standard" cells can be used for the array since they may be interconnected to edgestores in a way which corresponds to the interconnection of cells in the array.

Preferably apparatus according to the invention is constructed to scan a data array, having at least a second predetermined number of elements in one dimension, in directions normal to that dimension only by including in the apparatus at least the second predetermined number of cells to allow the cell array to extend completely across the data array along the said one dimension. In apparatus of this type edgesignal stores are provided along those edges of the cell array extending normal to the direction of propagation.

Scanning in one direction with an array of this type simplifies reading and writing data to the cell array since addresses can be incremented by a fixed amount at the beginning of each scan cycle.

Preferably the cells are divided into groups each corresponding to a section of a row or column of the data array normal to the direction of scanning, and each group of cells is coupled to external storage means for that group. If the external storage means have sufficient capacity such an arrangement has the advantage that data from the data array can be transferred to the external storage means before scanning, the external storage means can be used to hold intermediate results during processing and data forming the processed-data array can be held in the external storage means after processing.

The cell array may be made up by a plurality of first and second integrated circuits, the first integrated circuits each comprising a plurality of cells and the second integrated circuits each comprising as many of the edge-signal stores as there are cells in one first integrated circuit.

According to a second aspect of the present invention there is provided a method of local or propagation processing for data held by a data array using an array of cells as hereinbefore defined, having significantly fewer cells than there are data array elments, and a plurality of edgesignal stores, inter-connected with those cells along edges of the cell array normal to a direction of scanning, the method comprising:: scanning the cell array across a data array by carrying out a number of successive scan cycles in which data is read from successive blocks of elements of the data array into the cell array, processed according to control signals, applied to the cells, and read from the cell array to form a processed-data array, the control signals controlling data input to the cells from other cells in addition to the processing operations carried out, each scan cycle including transferring data from edge-signal stores of the trailing edge of the cell array in scanning, to adjacent cells of the array transferring data, after processing in that cycle, from cells along the opposite edge of the array to edge-signal stores of the leading edge, and transferring data from edge-signal stores of the leading edge to edge-signal stores of the trailing edge.

The method of the invention may be used where the cell array does not extend completely across the dimension of the data array by dividing the data array into sections and each having a suitable dimension and then using the method to scan one section at a time. Preferably further edge-signal stores are then provided to correspond to data elements just outside the section being scanned along the edges of the array parallel to the direction of scanning.

One method of carrying out global (or propagation) processing operations when some elements of the data array represent a recursive shape, is to scan the array completely in one direction and then in the opposite direction and so on until no change is observed in cell outputs. The method of the invention is advantageous particularly in recursive global operations because in such operations data is transferred between edge-signal stores in one direction while scanning is in a first direction and in the opposite direction when scanning is in a second direction opposite to the first.

An embodiment of the invention will now be described by way of example, with reference to accompanying drawings, in which:~ Figure 1 is a block circuit diagram of a cell for processing in a data-array element Figure 2 is a block circuit diagram of a section of an array of cells of the type shown in Figure 1, Figure 3 is a diagram illustrating interconnections between cells and edge-signal stores in the cell array, Figure 4 is a partial memory map for a RAM of the type included in Figure 2, Figure 5 is a block diagram showing data paths to and from the array, and Figure 6 is a block diagram of control circuit for the cell array.

Figure 2 shows one of sixty-four identical sections of a cell array which is constructed to scan a 512 by 512 data array. Each section comprises four CLIP 4 integrated circuits (ICs) 13 to 16 and each IC contains two rows of four CLIP 4 cells. Each cell (one of which is designated 21) has its own processor, memory and input gating and is as shown in Figure 1. The sixty-four sections each with two rows of eight cells can be regarded as extending completely across one dimension of the 512 by 512 data array from one side to the other and since there are two rows of CLIP ICs each containing two rows of cells, the cell array extends across four rows of the data array. Thus in order to scan the complete data array it is necessary to perform 128 scanning operations.

In order to allow the scanning operation to proceed as simply as possible two additional types of circuit are provided, firstly ICs 17 to 20 each comprising four edge-signal stores and secondly four additional RAMs 22 to 25 each 8K by 8 bit.

Dealing firstly with the need for the groups of edge-signal stores 17 to 20, each cell has eight input terminals 12 (as shown in Figure 1) and these are normally connected to the eight surrounding cells in a cell array. However this is not possible for those cells on the upper and lower edges of an array made up of the units of Figure 2, and for this reason some of the edgesignal stores in the ICs 17 and 18 are connected to a cell 21 together with those other cells which are available. In Figure 3 connections 26 are internal to the CLIP integrated circuits, connections 27 are provided by the interconnection of CLIP 4 integrated circuits but connections 29 and 30 are provided by paths 32 and 33 shown in Figure 2.Hence provided the edge-stores in the ICs 17 and 18 are loaded with information relating to the previous row in a vertical scan the cell 21 receives all the inputs required in a current row of the scan.

Since the edge-signal stores do not carry out processing there is no need for them to receive output signals from cells, except during local or propagation operations when as will be explained the output from a cell in a leading edge during scanning is stored in the adjacent edge-signal store; for example a path 30' would be used to transfer the output of the cell 21 to an edgesignal store in the IC 17.

The other cells in the array are either connected to adjacent cells by internal and external integrated circuit connections, or to other cells and edge-stores by similar connections and data connections, such as 34 and 35 connecting the edge-stores in the ICs 19 and 20 of Figure 2.

Interconnections between cells which are not adjacent to the edges of the array are shown in Figure 3 for a cell 36 in the integrated circuit 16.

These connectors are made by internal integrated circuit connections and external connections between chips. Input connections to the other cells in Figure 3 are omitted for clarity.

The RAMs 22 to 25 are provided so that data for each element of the data array can be stored before scanning commences, any intermediate data can also be stored, as can processed data.

During scanning the cell array plus RAMs of the type designated 22 to 25 are self-contained as far as data is concerned, allowing fast scanning.

Figure 4 shows one of the eight columns of the RAM 22 corresponding to data relating to top right cell 37 of the integrated circuit 13. Thus in the first scan of four data-array rows, up to 64 bits relating to the first point in the data array may be stored at RAM address 1 to 64 to input data, to store intermediate results and to store data output from, the cell 37. Data for the other cells in the upper rows of the ICs 13 and 14 are stored in the other seven columns of the 8Kx8 RAM and cells in other ICs store data in other RAMs 23 to 25.

In the second scan of four data array rows, the cell 37 corresponds to data array address 2049 and data relating to this address is stored in RAM column addressed 65 to 128. In this way after 128 scans the column of the RAM 22 shown in Figure 4 contains up to 64 data-bits relating to 128 pixels (that is 8K bits).

The single-bit buffer memories A (See Figure 1) of the cells in each section of the cell array are connected to form an eight-bit shift register using the data input and data output connections of the cells. Thus the buffer memories A of the cells of the upper rows of the integrated circuits 13 and 14 form one eight-bit register and in order to shift information to or from the RAM 22, a data path 38 is used to transfer the information once per scan line into a buffer register 40 from where it is read into the RAM 22 with the appropriate row address corresponding to the current scan line, these row addresses being incremented by 64 at the end of each scan line. Similar data paths and buffer registers 42 to 45 are provided for the RAMs 23 to 25, respectively.

Before starting a scan an external RAM 60 (see Figure 5) comprising the RAMs 22 to 25 and the RAMs of the 63 other similar units are loaded by way of the cell array designated 61 in Figure 5 with data corresponding to unprocessed data array elements.

Since the only access to these RAMs is by way of the A registers in the cells, loading is by way of the shift registers formed by these registers and the buffers, including the buffers 40, 42, 43 and 44.

The data array may be held in an input RAM 62 which may be coupled to a video input (not shown) or obtained from a direct data input 63.

When scanning and processing are complete, data is read from the RAM 60 to an output RAM which may be used to drive a video monitor (not shown) or passed to a direct data output 65.

Since items 62 to 65 are known in the art they are not described further.

Data is written from the RAMs 22 to 25 and similar RAMs to all the cells in the array before processing a group of four rows of the data array and after processing from the cells to the RAMs.

In order to load the edge-stores for local processing data is read from the RAMs into the top and bottom edge-stores again by way of the buffers and the cells.

In global or propagational processing data is read into edge-stores after each four row scan.

Thus the outputs of cells along the leading edge are read into adjacent edge-stores, for example in the ICs 19 and 20 in a downward scan. The contents of these edge-stores are then passed to corresponding edge-stores along the trailing edge, in this example in the ICs 17 and 18 for use as inputs in the next four row scan, when they are used as inputs for the top row of cells in the array.

If the data array is being scanned upwards then before each group of four lines is processed (except the first) data from the top edge-stores relating to processing the previous four rows of the data array is read into the bottom edge-stores.

Paths for these upward and downward transfers are designated 48 and 49 in Figure 2.

The circuits shown in Figure 6 are used to control the cell array. A microcomputer 50 which may for example be DEC type LSl-1 1/23 is programmed to cause the required processing of the data array to be carried out using an assembly language of the type exemplified in the above mentioned paper by M. J. B. Duff.Each processing operation may consist of three or four instructions of three types:~ SET-specifies the type of operation to be carried out in that it sets each Boolean processor 10 (Figures 1) by applying control signals to the terminals 11, it sets the input gating by applying signals to the control terminals of the input gates and sets up the internal logic by applying signals to the three control terminals "enable B, R and D load clock", LDA or LDB-Ioads buffer memories A and i3 in each cell, and PST-causes the operation specified by SET to be carried out and the result passed to the buffer memory D.

These instructions in an appropriate sequence are applied to a bus 51 and steered to an array register interface 52 where they are held in two sets of registers. The instructions from the microcomputer 50 are "pipelined" by means of a sequence of 53 which usually loads the first set of registers in the interface 52 while the second set of registers is controlling operations carried out by the CLIP integrated circuits, and the RAMs associated with the array cells.

Although the digital code held by the registers on the interface 52 would be suitable for application to CLIP 4 cells when such cells form a complete array, it must be translated in order to drive a cell array which scans the data array and to drive the accompanying circuits. This function is carried out by an array sequence microcode generator 54 which provides signals for array drive circuits 55 and also for a RAM address generator 56 which provides address signals to read out the RAMs associated with the cell array.

The array drive circuits 55 comprise circuits which appropriately buffer the generator 54 to the cells of the array.

Since the output from the microcomputer 50 is in the form of an assembly language which would be applied to a cell array having cells in a one to one correspondence with data elements, the control system of Figure 5 makes two operations necessary for a scanning array transparent to the programmer. These operations are firstly transfer of data between the internal memories D of the cells and the external RAM associated with the cells (that is for example RAMs 22 to 25) and secondly the scanning of the system. As an example of the first of these operations suppose that the following block of code has been received by the microcode generator 54 from the microcomputer 50: SET P.A LDA 17 LDB 43 PST 28 The first of these operations sets up the processors 10 to carry out an AND operation between the content of each register A and the content of each register B.In the LDA operation the contents of location 17 in the external RAM relating to each cell, is loaded into register A and LDB is a similar operation in which the contents of location 43 are loaded into register B. In the last operation processor 10 is instructed to carry out the AND operation and write the result into RAM location 28.

This block of code is written for a complete cell array with one call for each data element but in view of the way in which the CLIP cells are configured in the array and internally, the actual sequence which must be executed, omitting for the moment scanning, is: 1. SETA 2. Load series-parallel buffer from external RAM location 43 3. Serial A 4. PST1 5. SET PA.

6. Load series-parallel buffer from external RAM location 17 7. LDB 1 8. Serial A 9. PST2 10. LDA2 11. Serial A 12. Load external RAM location 28 from series-parallel buffer.

Operations 1 to 4 of this sequence take the contents of location 43 and load it into location 1 of the internal RAM D. SET A sets up an operation in which the processor output is made equal to the input of the register A. The second operation loads the buffer from the external RAM and the third operation loads register A serially from the buffer. In the fourth operation the contents of the register A are transferred to internal RAM location 1.

Operation 5 sets the processor to carry out the required AND operation between the contents of the registers A and B and the buffer is loaded from RAM location 17 in operation 6. Register B is loaded from location 1 of RAM D in operation 7 and in operation 8 the A register is loaded from the buffer. Operations 9. 10 and 11 cause the AND operation to be carried out and the result written to RAM location 28.

Thus the sequence microcode generation 54 generates code corresponding to operations 1 to 12 above from code corresponding to the four instructions received from the microcomputer 50.

As can be seen LDA, LDB and PST operations as seen by the cell array 61 are always "dummy operations", used with predetermined addresses.

The program addresses are always applied to the external RAM.

For the "pointwise" class of operations where operations are carried out by a cell on data which relates to the data element corresponding to that cell only, such as the above example, the only modification which the scanning process involves is to the external RAM addresses. For each movement of the scan strip the addresses are incremented by 64 so that a general expression for these are:~ AEXT=1 7+64n BEXT=43 +64n PEXT=28+64n=0 to 127 Where a "carry" is involved in the operation carried out by the Boolean processor 10 the translation of the output of the microcomputer 50 is more complicated but will be apparent to those familiar with the art.

The two other types of classes of operations which are required of the cell array are: "local" where data is used which relates to data elements corresponding to other cells than that carrying out processing; and "propagation" where as has been mentioned, the signal applied to the interconnection output of a cell depends upon the value of the interconnection output from a neighbouring cell.

Recursive shapes, for example hooks or loops, present a problem when carrying out a propagation operation by scanning, in that while propagation takes place in the direction of scanning it cannot take place in the opposite direction because part of the data array has already been scanned. This problem is overcome by carrying out a complete scan in first one direction and then the other until no further changes in cell outputs occur. In order to continue propagation at a point where it finished in one scan direction a "seed" value is held by the array indicating the temporary finish point. This "seed" is picked up when scanning is in the other direction to restart propagation.

For a local operation the instructions received by the microcode generator 54 from the microcomputer 50 might for example be SET A.P, (2) A LDA 37 PST9 where the first operation prepares the processor to output via the interconnection outputs the value resident in its A register, and causes the final result of processing to be the AND of the value resident in the A register and the value received from its neighbour in a direction specified as (2).

The sequence of machine operations using edge-stores is then:~ 1. Set upper edge stores to array edge value (1 orO) 2. Load lower edge stores from external RAM address 37+64 (n+ 1) 3. SETA.P(2)A 4. Load serial-parallel (S-P) buffer from RAM address 37+64n 5. Serial A 6. PST2 7. Load lower edge-stores from interconnection output N 8. Load upper edge-stores from lower edge stores 9. LDA2 10. Serial A 11. Load external RAM address 9+64n from S-P buffer Operations 2 to 11 are repeated for n=O to 127 to complete the scan.

Global propagation is handled in the following way: Suppose there are black objects on a white background, and an outside edge function is required. The CLIP 4 instructions are:~ SET-A.P, (1-8) A.P,E LDA 10 PST 15 In the scanned array those instructions are split into two operations, one global and one Boolean:~ SET P, (1-8) A.P,E LDA 10 PST 20 SET~A.P LDA 10 LDB 20 PST 17

Global to find propagation path Boolean to give outside edges.

These are translated by the microcode sequence generator into the following set of operations: 1. Clear RAM add 63+64n for n=(iI-1 27 2. Set upper edge stores to array edge value 3. Set lower edge store to ~ 4. Load S-P buffer from RAM add 63+64n 5. Serial A 6. SETA 7. PST31 8. LDB 31 9. Ld S-P buffer from RAM add 1#+64n 10. Serial A 11. SET P, [ Bl-8 ] A.P,E 12. PST 16 1 3. Load lower edge stores from N outputs 14. Set upper edge stores to ~ 1 5. Transfer edge stores 16. LDA 16 17. LOB 31 18. SETA@P 19. PST28 20. Test array gate output 21. Serial A 22.Load external RAM 63+64n from S-P buffer Repeat 4-22 for n=Q)--l 27 Repeat until no change at operation 20. Then: 1. SETA 2. Load S-P buffers from RAM add 63+64n 3. PST 2 4. SET-A.P 5. Load S-P buffers from RAM add 1Q)+64n 6. Serial A 7. LDB2 8. PST 1 9. LDA 1 10. Serial A 11. Load RAM add 15+64n from S-P buffer Scan for n=Q1--l 27 The effect of these operations is as follows: Operation 1 clears a plane of the external RAM which will store the accumulating propagation path, whilst operations 2 and 3 set up the initial condition for the operation. Operations 4 to 8 load the current propagation path (initially zero) into the B register to act as a 'seed' for the next cycle of the scan.Operations 9 and 10 load one point of the image data into the A register of each cell.

The SET instruction at operation 11 is a program instruction designed to produce the propagation path. The propagation path is stored in D16 at step 12, and that part which is to be passed to the next strip of array is loaded to the lower edge stores at 13, and transferred to the upper edge stores at 15, whilst 14 ensures that no spurious signals are input from the lower edge. Operations 1 6 to 20 test whether the new propagation path (D16) differs from the old (D31). Finally, operations 21 and 22 load the new propagation path to external RAM address 63+64n (n=O to 127). Operations 4 to 22 are repeated for n=O to 127, i.e. for the 128 scanning strips. This scanning is repeated up and down the array until no further change in the propagation path occurs.

The second sequence then operates.

The above operations which establish the propagation path must be completed before image analysis results based on the path can be calculated in the second sequence of operations.

Operations 1 to 3 and 7 move the current slice of propagation path to the B register. The SET instruction at operation 4 prepares the cell to compute the result required by the program instruction, using the original image and the propagation path derived in the first sequence.

Operations 5 and 6 load the original image into the A register, whilst operations 8 to 11 transfer the result to external RAM. The sequence is repeated for n=O to 127.

in order to determine when global propagation is complete and scanning up andwhen thedata array should cease, a group of gates (not shown) is provided with one gate for each data array element, the gates forming, in effect, a single OR gate. In each scan except the first, an EX-OR operation is carried out by each processor at the end of each scan of four lines of the data array.

The EX-OR operations compare the current value of data elements with respective previous values and each indicates by its output if a change has occurred in the corresponding data element.

By applying the outputs obtained to the single OR gate any change occurring in a scan is detected.

When no such change is detected a "scanning complete" signal is given.

While a specific embodiment of the invention has been described, it will be clear that the invention can be put into practice in many other ways. For example scanning may be in two orthogonal directions and cells other than CLIP cells may be used.

Claims (6)

Claims

1. Apparatus for processing data held by a data array having at least a predetermined number of elements, comprising an array of cells, as hereinbefore defined, in which the number of cells is substantially less than the predetermined number, the cells being interconnected systematically according to position in the cell array, control means adapted to scan the cell array across a data array by carrying out a number of successive scan cycles in which data is read from successive blocks of elements of the data array;; into the cell array, processed and read from the cell array to form a processed-data array, the control means supplying control signals for the cells, and a plurality of edge-signal stores interconnected with those cells along edges of the cell array contiguous, in a scan cycle, with parts of the data array which have been, or will be, scanned in other scan cycles, the edge-signal stores also being interconnected to transfer data in at least one direction, from edge-signal stores along at least one edge of the cell array to edge-signal stores, corresponding by position, along the opposite edge of the array, the control means being adapted to transfer, in each scan cycle, data between the edge-signal stores and elements of the data array which are contiguous with that part of the data array being processed in the current scan.

2. Apparatus according to Claim 1 constructed to scan a data array which has at least a second predetermined number of elements in one dimension, in directions normal to that dimension only, wherein the number of cells is at least equal to the second predetermined number to allow the cell array to extend completely across the data array in the direction of the said one dimension.

3. Apparatus according to Claim 2 wherein for each cell which is in an edge of the cell array normal to a direction of scanning there is a corresponding one of the edge-signal stores, and each edge-signal store is connected to receive output signals from the cell to which it corresponds and to transmit input signals for its corresponding cell and adjacent cells in the same edge of the cell array.

4. Apparatus according to Claim 2 or 3 wherein the cells are divided into groups each corresponding to a section of a row or column of the data array normal to the direction of scanning, and each group of cells is coupled to external storage means particular to that group.

5. A method of local or propagation processing for data held by a data array using an array of cells as hereinbefore defined, having significantly fewer cells than there are data array elements, and a plurality of edge-signal stores, interconnected with those cells along edges of the cell array normal to a direction of scanning, the method comprising scanning the cell array across a data array by carrying out a number of successive scan cycles in which data is read from successive blocks of elements of the data array into the cell array, processed according to control signals, applied to the cells, and read from the cell array to form a processed data array, the control signals controlling data input to the cells from other cells in addition to the processing operations carried out, each scan cycle including transferring data from edge-signal stores of the trailing edge of the cell array in scanning, to adjacent cells of the array, transferring data, after processing in that cycle, from cells along the opposite edge of the array to edge-signal stores of the leading edge, and transferring data from edge-signal stores of the leading edge to edge-signal stores of the trailing edge.

6. Apparatus for processing data held by a data array substantially as hereinbefore described with reference to the accompanying drawings.