GB2121579A - Coin validating - Google Patents

Abstract

An electronic coin validating arrangement wherein an entered coin is first sensed by a true coin sensor (16) and if not rejected is permitted to pass an apertured obturator (21) with which is associated an optical sensor (17). Signals generated by the two sensors are fed to control logic (30) in the form of an array of latches and a status counter which is clocked by successive changes in the output signals received from the sensors. Following each count, the actual sensor output is compared with a predicted output. Correspondence throughout the entire sequence of signals, which represent the progress of the coin along a coin feed path, is necessary in order to achieve final coin acceptance. <IMAGE>

Description

SPECIFICATION Electronic coin validating arrangement This invention relates to an electronic coin validating arrangement.

Coin validating arrangements are employed in conjunction with coin freed mechanisms to check an entered coin for value and authenticity. Such validating arrangements are currently for the most part of electronic nature, and include anti-fraud circuitry.

Thus, although the basic validator can check a coin for dimensions and composition and thereby usually satisfactorily verify if a true coin has been entered, it is also desirable to check that the validator has not been fraudulently tripped by illegal actions such as one or more coins suspended on threads or adhered to other flexible recovery means or by the entry of a close succession of two or more false coins selected to stimulate the validator in like manner to a true coin or by a combination of such methods.

The above are but examples of frauds which can be practised; more complex frauds are also known, and are difficult to avoid altogether because necessarily the validating arrangement must include tolerances sufficient to allow for normal variations in true coins of the correct denomination, the wear and surface conditions of which can affect both the magnitude of signals output from the checking sensors and the speed of travel of a coin.

Commonly, the mechanism will include a mechanical gate which diverts a coin to accept or reject, and a sensor downstream of this gate verifies that a coin has entered the accept path. It is known to AND this signal with a delayed output of the upstream true coin sensors and/or to NAND the accept sensor signal with the current output of the upstream sensors, allegedly to check that the coin which has tripped the accept sensor is the same true coin which has previously been verified upstream.

However, anti-fraud circuitry of this kind becomes increasingly complex as efforts are made to prevent differing types of fraud, and can still fail to be completely effective.

It is an object of this invention to provide an improved form of electronic coin validating arrangement.

The invention is based on the concept of producing an ordered sequence of pulses as a coin passes from entry to acceptance, and verifying that this ordered sequence is adhered to.

According to one aspect of the present invention, there is provided an electronic coin validating arrangement comprising a sensor means arranged to initiate development of a sequence of signals corresponding to successive stages in the passage of a coin along the feed path, a status counter which is successively clocked by the successive signals of said sequence, and logic means for decoding the status count to develop signals which predict the output of the sensor means at each stage of coin passage and for comparing the predictive signals with the actual output of the sensing means at each stage of coin passage.

Preferably, the sensor means will comprise at least two sensors spaced along the coin feed path, each producing a succession of signals responsive to coin passage, and means will be provided for combining the two or more said successions of signals together to produce the signal sequence which is used to clock the status counter.

Assuming the use of two sensors, one such sensor, usually the more upstream one, may be a sensor which checks a coin for denomination and truth. The more downstream sensor may then be a sensor which either checks further progress of the coin or checks operation of an essential part of the mechanism such as a mechanical gate or obturator or checks both.

It will often be convenient to employ in the true coin sensor an oscillator circuit for generating an electromagnetic field of predetermined frequency. In this case, a second output of the oscillator may be used to drive a multi-stage timer which supervises the logic means. The latter, i.e. the logic means, can perform the multiple tasks of verifying the true coin signal output from the upstream sensor, of controlling timing intervals and of verifying the status count.

The invention is particularly suited to use in a coin validatorwhich tests a coin immediately inside the entry bezel and includes an obturator which, if not lifted responsively to production of a true coin signal, re-presents the coin at the entry bezel.

Uniquely, the present invention also concerns the use of a sensor means which cooperates with such an obturator to produce or contribute to a sequence of signals which may then be verified.

Thus, according to another aspect of the invention, there is provided an electronic coin validating arrangement comprising an obturator in a coin feed path, sensor means associated with the obturator, means whereby the obturator is first displaced for passage of a true coin and is then returned to its rest position, the obturator and sensor means being arranged thereby to produce a succession of signals responsive to said obturator movement, and means for verifying the sequence in which said succession of signals is produced. An apertured obturator is especially suitable.

Thus, for example, if the more downstream sensor is an optical sensor, this can be arranged to produce a succession of signals as the sensor is first unobstructed; obstructed by displacement of the obturator as the coin is pushed in; unobstructed as the aperture aligns with the sensor (this conveniently generally corresponding to the position at which the coin is verified by the true coin sensor); obstructed by the entering coin on the assumption that the obturator is lifted due to generation of a true coin signal; unobstructed as the coin leaves the mechanism to pass to acceptance; obstructed when the obturator fails and performs its return movement; and finally unobstructed again when the obturator has returned to its rest position.

Alternatively, it can be arranged that the optical sensor, or an additional optical sensor, tests the successive positions of the obturator during the forward and return movement on a line outside the coin feed path. This may be preferred, especially for checking the return movement of the obturator, in order to avoid reliance on any signals dependent on coin passage, which might possibly be simulated by a fraudulent obstruction.

In a preferred arrangement, the above succession of pulses generated by the optical sensor is combined with the true coin signal, for example as generated by the previously mentioned upstream sensor constituted by the oscillator circuit which tests a coin for denomination and truth at entry to the coin feed path, and the combined signal differentiated to produce the required pulse sequence in the form of clock pulses of short durations of which the leading edge represents a change in output signal level of one of the sensors. At each stage in the sequence, the logic means is arranged to decode the existing status count to predict the outputs of the sensor, and at the trailing edge of each clock pulse to compare the predicted sensor signal with the actual sensor signal. If correspondence is not maintained throughout the sequence, a final accept signal is not generated.In addition, the lift obturator signal will be cut short, timing control being exercised to ensure that the obturator does not fall on to a coin and cause the mechanism to jam.

A practical arrangement of electronic coin validating arrangement in accordance with the invention will now be described by way of example with reference to the accompanying drawings, in which: Figures IA to 1D show stages in the passage of a coin through the entry zone of a coin freed mechanism; Figures 2 and 3 show a preferred true coin sensor; Figure 4 is a schematic diagram of the coin validating circuitry; Figure 5 is a block circuit diagram of the validator; Figure 6 shows the sensor outputs and associated waveforms developed therefrom; Figure 7 shows the manner in which a sequence of clock pulses for a status counter is developed; and Figure 8 is a truth table for the sequence checking and control signals of a logic circuit at each status count.

Referring first to Figure 1, the entry zone of a coin freed mechanism has an entry slot (bezel) 20 blocked by a solenoid operable obturator 21 having an aperture at 22. Immediately downstream of the entry slot 20 is a true coin sensor 16 and downstream of the latter is an optical sensor 17.

The true coin sensor 16 is in the form of an orthogonal coil array, as shown in Figures 2 and 3, which normally affords minimal coupling between transmit coil 12 and receive coil 14. Coupling is maximised when coin 11 on feed path 10 centres on the point of intersection of the normals 13 and 15 to the planes of the coils. Further details of such an orthogonal coil sensor can be found in our copending U.K. Patent Application No.

Reverting to Figure 1, Figure 1A shows coin 11 at the point of intersection. The coin 11 abuts the obturator 21 and pushes it inwards (Figure 1 B); the coin is now tested by true coin sensor 16 and, if verified, a lift-obturator signal is generated. Assuming a true coin, when obturator 21 is lifted, coin 11 passes beneath it (thus also passing optical sensor 17), as shown in Figure 1C. After the coin 11 has cleared the mechanism to enter acceptance (see Figure 1 D), the lift-obturator signal terminates, the obturator 21 drops and is spring returned to its rest position (Figure 1A). In so doing it again passes the optical sensor 17, 17A. If a true coin signal, and thus lift-obturator signal, is not generated, the coin will be re-presented at entry slot 20.Further details of such a reject-at-entry coin input mechanism are given in out copending U.K. Patent Application No.

Figure 4 shows the principle of the electronics of the coin validator. The transmit coil 12 is powered by a high stability oscillator 25 through a frequency divider 26 and isolation resistor 27. Frequency divider 26 can conveniently provide a 10 KHz output.

Normally, the output (Rx) of the receive coil 14 is low (zero), but this coil gives a high level output when the coils 12, 14 are coupled on entry of a coin.

The transmit coil signal (Tx) and the Rx signal are fed to a validator 28 in which the two signals (Tx and Rx) are compared: a) in relative magnitudes: b) in relative phases; and c) in relative phase sense. The validator 28 contains window comparators and the signals representing the results of the three checks (magnitude, phase and phase sense), assuming that each and all satisfy the limits set by the window comparators, are combined to generate a true coin signal.

The true coin signal is fed to control logic 30 supervised buy a 13-stage timer 31 which receives 10 KHz timing pulses taken from the frequency divider 26. The control logic 30 also receives the output signals Rx and 0x of the true coin and optical sensors. The control logic comprises a complex array of latches arranged in accordance with conventional principles for the functions to be performed.

The control logic 30 also includes a status counter which is in effect clocked by successive changes in the levels of the Rx signal and the Ox signal, and at each count, following a short delay, compares a predicted output of each sensor with the actual output thereof. Throughout the status count, correspondence between the predicted outputs and the actual outputs is necessary in order that a final coin accept signal will be generated.

Figure 5 shows the validator circuit in more detail.

Oscillator 25 is conveniently a ceramic resonator, and it will be noted that resistor 35 is connected in series with the transmit coil 12 in order that the Tx signal may be a current signal, although Rx remains a voltage signal.

Amplitude comparator 36 and phase and phase sense comparator 37 lead, in the event of entry of a true coin, to the production of a true coin signal output from AND gate 38. The signal is fed to the control logic 30 supervised by the timer 31.

Referring now to Figure 6, waveform (a) indicates the output of true coin sensor 16 (assuming a coin is entered) and likewise waveform (b) indicates the output of the optical sensor 17 resulting from inward and return displacements of the apertured obturator (assuming a true coin is passed to acceptance).

Waveform (c) indicates the true coin signal, waveform (d) the lift-obturator signal and waveform (e) the final accept signal. Finally, beneath waveform (e) is indicated a sequence count (0) to (8) which is to be effected as hereinafter described.

Thus, referring first to Figure 7, waveform (f) indicates an inverted Rx signal and waveform (g) a composite signal obtained by combining the inverted Rx and 0x signals at an Exclusive-Or gate.

Waveform (h) indicates a pulse sequence (0 to 8) obtained by differentiating the composite signal (g).

Pulses of the sequence have a duration of one to two 10 KHztiming pulses.

Reverting to Figure 5, a generator 40 for the above pulse sequence, fed with the inverted Rx and Ox signals, outputs to a status counter 41. The counter 41 has various outputs to the control logic 30, and a reset input 42 from the control logic, which reset input is also fed back to timer 31.

At each status count, and under supervision of timer 31, the control logic decodes the status count and, after a short delay, supplies an output to comparator 50, which also receives the Rx and 0x signals. The outputs from the control logic 30 to the comparator 50 (also in the form of a pluraiity of latches) correspond to predicted Rx and 0x signal levels appropriate to the status count, and correspondence at all stages is necessary if the control logic 30 is to generate a final accept signal on line 51.

If there is not correspondence at any stage, the system clears back to zero through reset 42, and a lift-obturator signal (if in existence) on line 52 is terminated.

Figure 8 is a truth tabie associated with the control logic 30.

The operation of the circuitry will now be further elaborated.

The status count is decoded by the control logic 30 to produce the various control and checking signals listed in Figure 8, of which the most important are S1 and S2, which predict the states of the sensors 16 and 17 at each stage in the sequence. "lint, clear" is an internal logic reset signal fed to the timing counter, whilst Z is a signal for clearing a sequence error latch and W is a signal for resetting the logic if the obturator has not lifted.

At status count 0, the logic is in its rest condition with the timing counter and sequence error latch held cleared by "Int. clear" and W respectively. As a coin is inserted, Rx changes state, a clock pulse is generated and the status counter is incremented to count 1.

On the falling edge of a clock pulse, to allow time for S1 and S2 to settle, the result of the sensor check is clocked through to the comparator 50. The condition of the sensors is checked in this way at every stage in the operational sequence of the mechanism.

Next the optical sensor 17 is obstructed, the status count is incremented to 2, and then to 3 as the optical sensor becomes unobstructed. As stated above, S1 and S2 are verified at each stage.

The coin is now in the measure position and the continuous counter clear is removed from a relevant latch L. After a delay (12.8 msec) to allow the coin to come to rest, the coin true signal is clocked through to a control latch M. If this signal is high it must remain so for a further period of 12.8 msec (i.e. Rx duration is timed), otherwise the coin will be judged marginal or a close fraudulent blank and the relevant logic fed with the true coin signal will be reset and a fresh clear will be applied at latch L. However, assuming the true coin signal remains high for 12.8 msec it is then held high by feeding it back via an OR gate. The obturator is then lifted.

In order to allow for validatortime constants and marginal coins, the true coin signal is tested repeatedly until either the verification signal Vx output from comparator 50 goes true or a signal Xx goes high at the mid-point of a time-out period (16 tries).

This avoids any possibility of a race condition developing between the time-out signal and the fresh clear on latch L which could result in the obturator dropping on to a true coin and jamming the mechanism.

If the coin fails the validation test by the true sensor 16, the logic eventually times out and resets to zero. Since the obturator 21 has not lifted, it is possible only to take the rejected coin back out of the entry slot.

However, assuming the obturator lifts, the coin will fall through the mechanism unless somehow restrained from so doing. However, if so restrained, a true coin signal, at least of intermittent form, will be maintained, and the timer will be repeatedly cleared via a latch N, preventing the logic from timing out and dropping the obturator on to the coin.

As the coin falls through the mechanism, the status count is incremented to 4 when the coin covers the sensor 17. The rising edge of "Int. clear" generates a pulse of three to four 10 KHz clock periods which clears the timing counter through latch L. At this point, the control logic, in addition to the repetitive checking of the sensor outputs, also checks that the oburator has lifted. If it has not, it is assumed that a fraud is being attempted; W goes high and resets the logic.

The status count is now on 5, and the coin has up to the time-out period to fall right through the mechanism and increment the status count through 6, 7 and 8. At status count 6, "Int. clear" resets the timer. When the coin has passed both sensors (count 7) itis deemed irretrievable, and after a delay of one half the time-out period, when Xx goes high, the obturator drops and returns to its rest position, incrementing the status counter to 8 within the time-out period. At count 8 an active-low accept signal of one half the time-out period is generated, and the timing counter is reset.

If the output of comparator 50 goes false at any stage, the sequence error latch is set and the logic drops the obturator (if it is lifted) and resets itself to zero via reset 42 and the status counter. Assuming the mechanism to be part way through its sequence when a false signal is produced, repeated clocking of the status counter will occur as the obturator returns to its rest position, and further sequence error signals will be generated, in the form of a short burst thereof.

It will be appreciated that the above-described mechanism and circuitry is by way of example only and may be modified in various ways within the scope of the invention as herein before defined. In particular, the concept of repetitively testing the output of the sensor means at various stages of the operating sequence of the mechanism is applicable to various mechanisms of more conventional type having separate accept and reject paths gated by a diverter, and to mechanisms employing various conventional kinds of true coin sensor in place of the orthogonal coil array hereinbefore described.

CLAIMS (Filed on 30 Mar 1983) 1. An electronic coin validating arrangement comprising a sensor means arranged to initiate development of a sequence of signals corresponding to successive stages in the passage of a coin along the feed path, a status counter which is successively clocked by the successive signals of said sequence, and logic means for decoding the status count to develop signals which predict the output of the sensor means at each stage of coin passage and for comparing the predictive signals with the actual output of the sensing means at each stage of coin passage.

2. An arrangement according to claim 1, wherein the sensor means comprises at least two sensors spaced along the coin feed path, each producing a succession of signals responsive to coin passage, and means are provided for combining the two or more said successions of signals together to produce the signal sequence which is used to clock the status counter.

3. An arrangement according to claim 2, including an upstream sensor which checks a coin for denomination and truth and a downstream sensor which checks progress of the coin into the mechanism or checks a part of the mechanism operable by such progress.

4. An arrangement according to claim 3, wherein the true coin sensor comprises an oscillator circuit for generating an electromagnetic field of predetermined frequency, the oscillator having an output for driving a multi-stage timer which supervises the logic means.

5. An arrangement according to any of claims 1 to 4, wherein the logic means acts to verify a true coin signal, to control timing intervals related to coin progress and to verify the status count.

6. An arrangement according to any of claims 1 to 5, wherein the sensor means includes a true coin sensor at the upstream end of a coin feed path, said sensor being associated with an obturator which re-presents a coin at an entry slot unless a true coin signal is generated.

7. An arrangement according to claim 6, wherein the sensor means includes a downstream sensor which cooperates with the obturator to produce or to contribute to the said sequence of signals.

8. An arrangement according to claim 7, wherein the said downstream sensor is a photo-electric sensor which cooperates with an apertured obturator.

9. An electronic coin validating arrangement comprising an obturator in a coin feed path, sensor means associated with the obturator, means whereby the obturator is first displaced for passage of a true coin and is then returned to its rest position, the obturator and sensor means being arranged thereby to produce a succession of signals responsive to said obturator movement, and means for verifying the sequence in which said succession of signals is produced.

10. An arrangement according to claim 9, comprising an apertured obturator.

11. An arrangement according to claim 9 or claim 10, comprising a sensor means in the form of an optical sensor.

12. An arrangement according to claim 11, wherein the optical sensor produces a succession of signals as the sensor is first unobstructed; obstructed by displacement of the obturator as the coin is pushed in; unobstructed as the aperture aligns with the sensor (this conveniently generally corresponding to the position at which the coin is verified by a true coin sensor); obstructed by the entering coin on the assumption that the obturator is lifted due to generation of a true coin signal; unobstructed as the coin leaves the mechanism to pass to acceptance; obstructed when the obturator falls and performs its return movement; and finally unobstructed again when the obturator has returned to its rest position.

13. An arrangement according to claim 11, wherein the optical sensor tests successive positions of the obturator during a forward and return movement thereof, on a line outside the coin feed path.

14. An arrangement according to claim 11, wherein the said succession of signals is combined with a true coin signal derived from a true coin sensor, and the combined signal is differentiated to produce a required signal sequence in the form of short duration clock pulses of which the leading edges represent changes in output signal level of one of the sensors.

15. An arrangement according to claim 14, wherein, at each stage in the sequence, a logic means is arranged to decode the existing status count to predict the outputs of the sensor, and at the trailing edge of each clock pulse to compare the predicted sensor signal with the actual sensor signal.

16. A coin validating arrangement substantialiy as hereinbefore described with reference to the accompanying drawings.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (16)

**WARNING** start of CLMS field may overlap end of DESC **. particular, the concept of repetitively testing the output of the sensor means at various stages of the operating sequence of the mechanism is applicable to various mechanisms of more conventional type having separate accept and reject paths gated by a diverter, and to mechanisms employing various conventional kinds of true coin sensor in place of the orthogonal coil array hereinbefore described. CLAIMS (Filed on 30 Mar 1983)

1. An electronic coin validating arrangement comprising a sensor means arranged to initiate development of a sequence of signals corresponding to successive stages in the passage of a coin along the feed path, a status counter which is successively clocked by the successive signals of said sequence, and logic means for decoding the status count to develop signals which predict the output of the sensor means at each stage of coin passage and for comparing the predictive signals with the actual output of the sensing means at each stage of coin passage.

2. An arrangement according to claim 1, wherein the sensor means comprises at least two sensors spaced along the coin feed path, each producing a succession of signals responsive to coin passage, and means are provided for combining the two or more said successions of signals together to produce the signal sequence which is used to clock the status counter.

3. An arrangement according to claim 2, including an upstream sensor which checks a coin for denomination and truth and a downstream sensor which checks progress of the coin into the mechanism or checks a part of the mechanism operable by such progress.

4. An arrangement according to claim 3, wherein the true coin sensor comprises an oscillator circuit for generating an electromagnetic field of predetermined frequency, the oscillator having an output for driving a multi-stage timer which supervises the logic means.

5. An arrangement according to any of claims 1 to 4, wherein the logic means acts to verify a true coin signal, to control timing intervals related to coin progress and to verify the status count.

6. An arrangement according to any of claims 1 to 5, wherein the sensor means includes a true coin sensor at the upstream end of a coin feed path, said sensor being associated with an obturator which re-presents a coin at an entry slot unless a true coin signal is generated.

7. An arrangement according to claim 6, wherein the sensor means includes a downstream sensor which cooperates with the obturator to produce or to contribute to the said sequence of signals.

8. An arrangement according to claim 7, wherein the said downstream sensor is a photo-electric sensor which cooperates with an apertured obturator.

9. An electronic coin validating arrangement comprising an obturator in a coin feed path, sensor means associated with the obturator, means whereby the obturator is first displaced for passage of a true coin and is then returned to its rest position, the obturator and sensor means being arranged thereby to produce a succession of signals responsive to said obturator movement, and means for verifying the sequence in which said succession of signals is produced.

10. An arrangement according to claim 9, comprising an apertured obturator.

11. An arrangement according to claim 9 or claim 10, comprising a sensor means in the form of an optical sensor.

12. An arrangement according to claim 11, wherein the optical sensor produces a succession of signals as the sensor is first unobstructed; obstructed by displacement of the obturator as the coin is pushed in; unobstructed as the aperture aligns with the sensor (this conveniently generally corresponding to the position at which the coin is verified by a true coin sensor); obstructed by the entering coin on the assumption that the obturator is lifted due to generation of a true coin signal; unobstructed as the coin leaves the mechanism to pass to acceptance; obstructed when the obturator falls and performs its return movement; and finally unobstructed again when the obturator has returned to its rest position.

13. An arrangement according to claim 11, wherein the optical sensor tests successive positions of the obturator during a forward and return movement thereof, on a line outside the coin feed path.

14. An arrangement according to claim 11, wherein the said succession of signals is combined with a true coin signal derived from a true coin sensor, and the combined signal is differentiated to produce a required signal sequence in the form of short duration clock pulses of which the leading edges represent changes in output signal level of one of the sensors.

15. An arrangement according to claim 14, wherein, at each stage in the sequence, a logic means is arranged to decode the existing status count to predict the outputs of the sensor, and at the trailing edge of each clock pulse to compare the predicted sensor signal with the actual sensor signal.

16. A coin validating arrangement substantialiy as hereinbefore described with reference to the accompanying drawings.