GB2180729A - Direct memory access window display - Google Patents

Abstract

The present invention includes a DMA controller 20 coupled over a bus 12 to a frame buffer 18 for use in displaying digital images in an animated form on a CRT display 14. The frame buffer includes one or more bit maps representative of the display. A block of memory within the frame buffer is mapped onto corresponding picture elements (pixels) on the display. The frame buffer continuously scans the bit map representing the CRT screen such that modifications to data bits within the frame buffer are correspondingly displayed on the screen. A plurality of windows may be displayed on the CRT having varying predefined widths which are appropriately represented within the frame buffer. Digital images stored as sequential "frames" of data in a memory, such as for example a hard disk 22 or RAM memory 15, may be directly transferred from the memory to the frame buffer for display without the need for central processing unit (CPU) 10 interaction, the location within the frame buffer to which such data is to be transferred being specified by an origin point and a width value. <IMAGE>

Description

SPECIFICATION Method and apparatus for DMA window display 1. Field of the invention: The present invention relates to apparatus and methodsfordisplaying graphic information. More particularly, the present invention relates to direct memory access (DMA) apparatus and methods for generating and manipulating images and data on a display system.

2.Artbackground: In the computing industry, it is quite common to represent and convey information to a userthrough graphic representations. These representations may take a variety of forms, such as for example, alphanumeric characters, cartesian or other coordinate graphs, as well as shapes ofwell-known physical objects. Historically, humans have interfaced with com puters through a system of discrete commands which typically comprise a combination of both text and mathematical symbolic characters. Examples of such systems are numerous and include the programming languages of FORTRAN, ALGOL, PLI, BASIC, and COBAL, which transform a given set of user commands into machine executable "object" code.

However, the ease with which a user becomes pro ficientin programming or interacting with the computer based system is generally a function of how close the system modelsthe logical thought of the user himself. One system which has been developed to minimize the learning and acclimation period in which a user must go through to become proficient in the interaction with a computer system isfrequ- ently referred to as an "object oriented" system. This system may utilize multiple "windows" displayed on a cathode ray tube (CRT) in which combinations of text and graphics are used to convey information.For example, each window maytake theform of a file folder, ofthetype used in a standard filing cabinet, overlapping other folders, with the "top" fully visible folder constituting the current work file. A user may add or delete information from a window, refill the file folder in another location, and generally operate with the windows just as if actual files in an office were being used. Thus, by graphically presenting an image which represents the object of the users command, and allow the userto operate on and manipulate the image in substantially the same way as he would as if the image constituted the actual object, the machine becomes easier to operate to the user and a stronger machine-man interface is achieved.

One historic limitation on the use of window based displays is in the case where animation within a window is desired. In such event, a series of sequen tialframesofdata are displayed within a window overtime, thereby appearing to the user as if the object displayed is animated, such as in a television or movie presentation. However, speed limitations in accessing memory have historically rendered animation of images difficult to achieve. The time which the central processing unit (CPU) requires to read data comprising an image from memory and then display such data was generally rather slow, and the images did notappearto "move" from oneframeto another in a continuous and fluid fashion.As will be descri bed, the present invention provides a direct memory access (DMA) system which permits images stored in memory to be displayed within a window on a CRT at a rate which permits an animation effect to be achieved.

Summary ofthe invention The present invention discloses apparatus and methods for direct memory access (DMA) having particular application for use in displaying digital images in an animated form on a CRT display. The present invention includes a DMAcontrollercoupled over a bus to a frame buffer. The frame buffer includes one or more bit maps representative of the display. A contiguous block of memory within the frame buffer is mapped onto sequential picture elements (pixels) on the display. The frame buffer con tenuously scans the bit map representing the CRT screen such that modifications to data bits within the frame buffer are correspondingly displayed on the screen.A plurality ofwindows may be displayed on the CRT having varying predefined widths which are appropriately represented within the frame buffer.

Digital images stored as sequential "frames" of data in a memory, such as a hard disk or RAM memory, may be directly transferred from the memory to a frame bufferwindowfor display withoutthe need for central processing unit (CPU) intervention and addressrecalculation.Auserinitiallydefinesa window width. The window height is implied by the number of data transfers to becompleted.Arec- tangulararea is thereby defined into which the graphic data will be transferred. The user then sets a base address which corresponds to the initial memory address and is assigned to the origin ofthe predefined window; namely the upper left hand pixel defining thewindow.A DMA controller initiates a read operation whereby a frame of data defining the image is read sequentially from diskormain memory and writtentto memory in a graphics controller. The graphics controller transfers the incomming data to a window in theframe bufferforsubse- quentdisplay. The host software then waits a predefined time interval ("T") to elapse priorto initiating any further data transfer operations. If additional frames are to be displayed, a new base address is set for the next sequential frame and the process is repeated. Using the present invention, digital images stored in memory may be directly transferred to a "window" within the frame buffer at high speed, thereby permitting an animation effect to be achieved.

Briefdescription ofthe drawings Figure 1 illustrates a computer system incorporating the teachings of the present invention.

Figure2 is a block diagram illustrating one implementation of the present invention to permit DMA access and display of stored images.

Figure 3 symbolically illustrates the use ofthe pre- sent invention's DMA controller to transfer data comprising images stored on magnetic disks and display ing such images in an animated fashion.

Figure4is aflowchart illustrating the sequence of operations of the present invention to display images stored in memory.

Notation andnomenclature The detailed description which follows is presented largely in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing artsto most effectively convey the substance of their work to others skilled in the art.

An algorithm is here, conceived to be a selfconsistent sequence of steps leading to a desired re suit. These steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It proves convenient at times, principly for reasons of common usage, to referto these signals as bits, values, elements, symbols, characters,terms, numbers, orthe like. It should be born in mind,however,thatall oftheseandsimilartermsare to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities.

Further,the manipulations performed are often referred to in terms, such as adding, transferring or comparing, which are commonly associated with mental operations performed by a human operator.

No such capability of a human operator is necessary, or desirable in mose cases in any of the operations described herein which form part of the present invention; the operations are machine operations.

Useful machines for performing the operations of the present invention include general purpose digital computers orsimilardevices. In all cases it must be kept in mind the distinction between the method operations of operating a computer and the method of computation itself. The present invention relates to method steps for operating a computer and processing electrical or other (e.g. mechanical, chemical) physical signalsto generate other desired signals.

The present invention also relates to apparatusfor performing these operations. This apparatus may be specially constructed forthe required purposes (i.e. a direct memory access controller and frame buffer) or it may comprise a general purpose computer as selectively activated or configured by a computer program stored in the computer. The algorithms and circuits presented herein are not inherently related to any particuiar computer or other apparatus.

Detailed description of the invention Apparatus and methods for direct memory access (DMA) for displaying digital images in an animated form are disclosed. In the following description, numerous details are set forth such as number of bits, architectures, sequences of operations, etc. to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practised without these specific details. In other instances, well known circuits and structures are not described in detail in order not to obscure the present invention unnecessarily.

Refering to Figure 1, a computer system forgenerating and displaying digital images in accordance with the present invention is illustrated. A host CPU 10 (which in the presently preferred embodiment comprises a Motorola 68010 based 32 bit microprocessor) is coupled to bus 12. Host CPU 10 performs a variety of functions including the execution of application software provided by a user which may define images to be displayed within windows on a cathode ray tube (CRT) display 14. A memory 15 is illustrated coupled to CPU 10 permitting data to be transferred over the bus to the various data processing resources attached thereto. To display images, the present invention utilizes a graphics controller26 including a colorframe buffer 18 coupledto bus 12 and CRT 14. The frame buffer 18comprises one or more "bit maps" of the display screen of CRT 14.In each bit map, a block of memory within frame buffer 18 is allocated such that each memory address and data value is mapped onto a corresponding picture element (pixel) on the display system. Thus, for each bit map the entire CRT screen is represented as eithera 1 (e.g. foreground) ora 0 (e.g. background) in a block of memory referred to as a "bit map". In a multiple-planesystem,the "bit" value at each memory address istypically mapped through a color map look-up RAM to provide a range of colors for each pixel. Frame buffer 18 continuously scans the bit map representing the CRT screen, as is well known in the art, such that modifications to data bits withintheframebuffer18arecorrespondinglydis- played on CRT 14.A DMA controller 20 is coupled to bus 12 and to a harddiskdrive22. In addition, DMA controller may be coupled to a network interface 24, such as ETHERNET, DECNET orthe like, or additional hard disk drives or other memory devices.

Referring now to Figures 1 and 3, in accordance with the present invention, a plurality of windows may be displayed on CRT 14 by appropriately writing data into areas within frame buffer 18. In practice, frame buffer 18 comprises a dual ported dynamic RAM bit map memory in which each memory byte corresponds to a pixel on the CRT 14 display. In addi tion, frame buffer 18 may include a plurality of bit maps representative of CRT 14, such that one memory set may be updated while another is read for display, with the first set being displayed while the second map is updated, and soforth. Thistechnique is referred to as double buffering and allows an in stantaneous switch for one imagetothe nextwithout thevisual effect of displaying a partially updated image. As illustrated, each window displayed on CRT 14 may contain a variety of alphanumeric characters and/or graphics. The windows may be overlapped upon one anothertherebygiving the appearance of folders overlaid on a desktop. In most instances, data to be displayed is processed by CPU 10 through the execution of an application software program.

The data to be displayed is then transferred over bus 12 into one or more bit maps comprising frame buf fer 18. However, in the case where digital images are to be displayed in an animated fashion, it has been foundthatthe processing requirements of CPU 10 in accessing the image located, for example, in memory 15, are too slow to achieve a believable animated effect. In addition, the storage space required to store a CPU hundreds orthousands of precomputed images in a CPU main memory is prohibitively expensive as compared to the cost of a mass storage device such as disk 22.The present invention overcomes the limitations in prior art display systems by providing circuitry within DMA controller 20 which permits the controllerto read disk 22, or data received over network 24, comprising a frame of digital information defining an image, and displaying the image on CRT 14withoutthe needforCPU 10 processing and the use of large amounts of CPU main memory. The present invention permits a "window" to be defined on CRT 14 having a desired width, and sequentially writing data into a portion of the frame buffer 18 where the window is located.

Referring now to Figures 1,3 and 4, assumefor sake of example, that a userdesiresto access a sequence of digital images (defined as frames) stored on magnetic disk 22. In the presently preferred embodi ment, CRT 14 and the corresponding bit map within frame buffer 18 are organized such that the pixel in the upper leftcornerofthe screen 14 is designated as the origin (0,0) point ofthe display. In addition, in the present embodiment, CRTdisplayl4numbers each subsequent pixel along a scan line in a linearsequen tial fashion. Presently, there are 1,152 pixels along each scan lineofCRTdisplay 14, numbered Oto 1151.

The pixel beginning with the next scan line is numbered 1152 and so forth. Windows within the display screen are defined by areas contained within the larger bit map, as illustrated best in Figures 1 and 3. In accordance with the present invention, a user desiring to sequentially and directlytransfer graphic images stored in digital form in a memory, such as memory 15 or disk 22, initially defines a window width within each of the frame buffer 18's bit maps and corresponding area of CRT 14. As best shown in Figure 3, the window width defines a rectangular area into which the graphic data will be transferred.

In the presently preferred embodiment, the size of the image stored in the memory device corresponds to the size of the image which will be subsequently displayed on CRT 14 as stored in the frame buffer 18.

For example, a digital image stored within hard disk 22 having the dimensions of 512 bits by 512, will be displayed on CRT 14 as an image 512 pixels wide by Sl2pixelshigh. Itisthereforeimportantfortheuser to specify the window width which corresponds to the width of the imagesto be displayed within the window. The user then sets the base address for the memory access, which corresponds to the initial memory address which will be assigned to the origin of the predefined window; namely the upper left hand point defining the window. Inthe example of Figure 3, this base address point is identified as point "B".DMA controller20 then initiates a sequential read operation whereby a frame of data defining the image is read from memory (e.g. hard disk 22 or memory 15) and is transferred over bus 12 into frame buffer 18, at a predetermined address range. Logic disposed on graphics controller 26 and frame buffer 18 decides the supplied address and re-directs the incomming data to the appropriate location in the frame buffer comprising the desired window on the CRT 14. Upon transfer ofthe data to frame buffer 18, it is subsequently scanned, as iswell known in the art, and displayed on CRT 14. The host software then waits a predefined time (e.g. 1/24th or 1/1 6th second) prior to proceeding with further data operations to display subsequent frames of digital graphic data.It will be appreciated by one skilled in the art, that in the event frame buffer 18 its double buffered (such that forexampleframe buffer 18 contains two full size bit maps which may be "toggled" alternatively) during the vertical retrace of the CRT 14, DMA controller 20 would alternate between frame buffer bit maps for each write cycle.

In the event additional frames are to be displayed to provide an animated effect, DMA controller 20 sets a new base address forthe next memory access and initiates additional read operations from memory to fetchthe nextframe ofthe digital image. This cycle is continued until all of the frames are mapped directly from the memorythrough DMA controller 20 and into the frame buffer 18 window.

Referring now to Figure 2, a block diagram is provided which illustrates a portion of the memory access logic within the frame buffer 18. As will be described below, the circuitry illustrated outputs row address signals (RAS) and column address signals (CAS) which are coupled to the appropriate memory device storing the digital images. A user sets an initial base address and provides the address to base counter 30. Similarly, the user sets the width ofthe DMAwindowto be displayed onCRT14bydefining, in binary, the number of pixels the window is to be wide and writing this number to width register 32.

The output of width register 32 is coupled to a 12 bit counter 34 such that the value of the width is prov idedthe load data inputs of counter 34. Theterminal count (TC) output of limit counter36 is coupled tothe count enable input of counter 30 which will count up to a predefined number of cycles before holding. For example, in the example illustrated in Figure 3,the CRT screen size, and therefore the frame buffer bit map size, is 1152 pixels wide. This value represents the limitofthe scan line length forthe particulardisplay system, the maximum count value for counter 36, and the number of cycles counter 30 will advance before holding.A 20 bit counter38 is loaded from the base counter 30 outputs, and the outputs of the counter38, as will be described, define the RAS and CAS addresses driving the accessed frame buffer memory.

In the event that no DMAtransfer is to take place, a system clock 39 increments the limit counter 36 from the initial value to its maximum count. Similarly, the system clock 39 simultaneously increments base counter 30 from the basevalue initially provided.

Once the limit counter reaches its maximum, it does not increment any further and precludes the base counter 30 from also doing so. Accordingly,thefinal base value is equal to the initial base value plus the range ofthe limit counter (i.e. 1152). The value con tained within 20 bit counter 38 is the original initial base address value since no DMA tra nsfer took place, thus 20 bit counter 38 was not incremented. Similarly, the value in width register 32 and 12 bitcounter 34 also remains the same since no DMAtransfertook place.

In the event a DMAtransferfrom memorytoframe buffer 18 isto occur, the initial base and width values are provided, as heretofore discussed. Accordingly, priortothe initiation ofthe DMAtransferthe initial base value is stored in base counter 30 and 20 bit counter 38 and the initial width value from width register 32 is provided to 12 bit counter 34. As illust- rated, 12 bit counter 34 is incremented on the completion of each memory cycle buy a signal provided along line 40. Every memory cycle increments the 12 bit width counter 34 as well as the 20 bit counter 38.

Accordingly 20 bit counter 38 outputs an incrementing frame buffer address for each new datum received over system bus 12. When 12 bit counter34 reaches the maximum predefined window width, a terminal count (TC) signal is provided on line 42 which reloads a new base value into base counter 30.

As previously described, the new base address pro vided will bethe previous base address plusthe limit countervalue (i.e. 1152). The effect of loading this modified address into base counter 38, is to advance the counterto the starting address of the next scan line within the defined window. In addition, the assertion of TC signal 42 reloads the limit counter36 such that it once again will begin counting upto its limit. Moreover, TC signal 42 reloads the value ofthe width provided in width register32intotwelvebit counter 34, and causes its own deassertion. The sequence of operations described continues until the entire frame of data has been read and stored into frame buffer 18.

Accordingly, apparatus and methods have been described for direct memory access for displaying digital images in an animated form on a CRT. It will be noted that the present invention has been described with particular reference to Figures 1 through 4, however, it is contemplated that many changes and modification may be made, by one of ordinary skill in the art, to the materials and arrangementofelements of the invention without departing from the spirit and scope of the invention.

Claims (31)

1. An apparatus for transferri ng data from astorage device to a display, comprising: display means for displaying data, said display means including a display having a plurality ofselec- tablyenabled display elements; frame buffer means coupled to said display means for storing data to be displayed, said frame buffer means including at least one bit map comprising a plurality of data bits, said bits representing the state of a display element on said display; storage means for storing data to be displayed, said data stored as frames in said storage means and defined by unique address locations;; controller means coupled to said storage means and said frame buffer means for reading a frame of said data from said storage means and transferring said data to selected locations in said frame buffer means, said locations being defined by a width value and an origin point, said controller means sequentially reading said data beginning from a base address such that data is transferred in the order in which it will be read from said frame bufferfor display; whereby data is transferred at high speed to said display.

2. The apparatus as defined by claim 1,wherein said display elements are organized into scan lines, and said data in said storage means is read by said controller means one scan line at a time.

3. The apparatus as defined by claim 2, wherein said selected locations in said frame buffer comprise a rectangular array, said array locations being a subset of said bit map.

4. The apparatus as defined by claim 3, wherein said locations defining said rectangular array are read by said controller means in the order in which said data is read from said storage means.

5. The apparatus as defined by claim 4, wherein said controller means reads successive frames of said stored image and transfers each of said frames of data to said rectangular array separated by a time S8TN w

6. The apparatus as defined by claim 4, wherein said width value and base address is defined bya user.

7. The apparatus as defined byclaim2,wherein said controller means includes a buffertotemporarily store each of said frames priorto transferto said frame buffer means.

8. The apparatus as defined byclaim 1,wherein said data to be displayed comprises a digital image.

9. The apparatus as defined by claim 4, wherein said controller means includes: base counting means for receiving said base value; limit counting means coupled to said basecounting means for counting up to a holding limitvalue and then precluding said base counting means from further counting; width counting means for receiving said width value; address output counting means coupled to said base counting means and said width counting means, said address output counting means providing RAS and CAS output signals, defining said unique address locations in said storage means; system clock means coupled to said base counting means for incrementing said base counting means and said limit counting means;; memory cycle signal generation means coupled to said width counting means for providing a memory cycle signal to increment said width counting means and thereby increment said RAS signal.

10. The apparatus as defined byclaim 9,wherein said width counting means outputs a terminal count (TC) signal upon reaching said width value, said TC signal reloading said width value into said width counting means, reseting said limit counter and providing a new memory base address to said base counting means.

11. The apparatus as defined by claim 10, wherein said base counting means includes a 20 bit counter.

12. The apparatus as defined by claim 11, wherein said width counting means includes a 12 bit counter coupled to a width register.

13. The apparatus as defined byclaim 12, wherein said address output counting means includes a 20 bit counter.

14. The apparatus as defined by claim 13, wherein said controller means, storage means and frame buffer means are coupledto one anotheralong a bus.

15. In a computer display system including display means having a display with a plurality ofselec- tively enabled display elements, an improved method for transferring data from a storage device to said display, comprising the steps of: storing data to be displayed in storage means, said data being organized into frames and defined byuni- que address locations;; reading a frame of data from said storage means and transferring said data to selected locations in a frame buffer coupled to said display means, said frame buffer including at least one bit map comprising a plurality of data bits, said bits representing the state of a display element on said display, said locations in said frame buffer being defined by a width value and origin point, said frame being read sequentially from a base address such that data is transferred in the order in which it will be read from said frame buffer for display; whereby data is transferred at high speed to said display.

16. The method as defined by claim 15, wherein said display elements are organized into scan lines and said data stored in said storage means is read one scan line at a time.

17. The method as defined byclaim 16,wherein said selected locations in said frame buffer comprise a rectangular array, said array locations being a subset of said bit map.

18. Themethodasdefined byclaim 17,wherein said locations defining said rectangular array are read by said controller means in the order in which said data is read from said storage means.

19. The method as defined by claim 18, wherein said data is read in successive frames and transferred to said frame buffer means separated by a time "T".

20. The method as defined by claim 19, wherein said width value is defined by a user.

21. The method as defined by claim 20, further including a buffer to temporarily store each of said frames prior to transfering said frame of data to said frame buffer means.

22. The method as defined by claim 21, wherein said data to be displayed comprises a digital image.

23. The method as defined by claim 18, wherein said reading step is completed by a controller means including: base counting means for receiving said base value; limit counting means coupled to said base counting means for counting upto a holding Iimitvalue and then precluding said base counting means from further counting; width counting means for receiving said width value; address output counting means coupled to said base counting means and said width counting means, said address output counting means providing RAS and CAS output signals, defining said unique address locations in said storage means;; system clock means coupled to said base counting means for incrementing said base counting means and said Iimitcounting means; memory cycle signal generation means coupled to said width counting means for providing a memory cycle signal to increment said width counting means and thereby increment said RAS signal.

24. The method as defined by claim 23, wherein said width counting means outputs a terminal count (TC) signal upon reaching said width value, said TC signal reioading said width value into said width counting means, reseting said limit counter and providing a new memory base address to said base counting means.

25. The method as defined by claim 24, wherein said base counting means includes a 20 bit counter.

26. The method as defined by claim 25, wherein said width counting means includes a 12 bit counter coupled to a width register.

27. The method as defined by claim 26, wherein said address output counting means includes a 20 bit counter.

28. The method as defined by claim 27, wherein said controller means, storage means and frame buf ferarecoupledtooneanotheralong a bus.

29. The method as defined by claim 28, wherein said frame buffer comprises a plurality of bit maps, such that the contents of each of said bit maps is alternatively displayed while the contents of another bit map is updated.

30. A direct memory access apparatus for displaying graphic information substantially as hereinbefore described with reference to the accompanying drawings.

31. A method for transferring data from a storage device to said display substantially as hereinbefore described with reference to the accompanying drawings.