GB2175470A - Synchronizing video sources - Google Patents

Abstract

A video overlay controller accepts video inputs from diverse sources such as video disk players, video tape players, computer video generators, and the like, and provides synchronizing signals which stably lock the video sources to each other for simultaneous display. Synchronization is achieved within eight field times at most. Both interlaced and non-interlaced sources may be mixed for display. Color graphics adapter 12 is synchronized with a video disk player 10 by control of clock pulses provided by an oscillator 124 to the adapter for setting its operating frequency. The clock pulse frequency is controlled (i) in a horizontal sync section 102 wherein the oscillator 124 is controlled by a phase comparator 122 receiving the adapter horizontal sync signal CGAHSYNC and a horizontal reference signal NREF; (ii) in a vertical sync section 100 wherein the oscillator output can be so gated as to halve the effective frequency if the adapter vertical sync signal CGAVSYNC is detected as having more than a certain misalignment (one-half scan line) with the disk vertical sync signal NTSCVSYNC. <IMAGE>

Description

SPECIFICATION Video overlay controller Backgroundofthe Invention A. Fieldofthelnvention The invention related to video overlay controllers and, more particularly, to apparatus for synchronizing the video signal from separate video sources.

B. PriorArt Video overlay controllers control the simultaneous display ("overlay") of video signals from two or more sources. An important characteristic of such controllers is the synchronization of the video signals from the separate sources so that the resultant composite display provides a stable picture to the viewer.

One technique for providing such synchronization is described in U.S. Pat. No. 4,346,407, issued Auk.24, 1982 to R. H. Baer. In the circuit of that patent, separate synchronizing loops are provided for establishing frequency and phase coherence between the signals to be synchronized. With this arrangement, long waiting times (up to over 900 field periods or 15 seconds) can be required in orderto establish synchronization. Further, the sources to be synchronized must be ofthe same scan type, i.e., both interlace or both non-interlaced.

BriefSummaryofthe Invention A. Objects ofthe Invention Accordingly, it is an object of the invention to provide an improved video overlay controller.

Further, it is an object of the invention to provide a video overlay controllerthat rapidly achieves synchronization between two or more video sources that are to be overlaid.

Yet another object ofthe invention is to provide a video overlay controllerthat is operable with video sources of different scan types.

B. BriefSummary ofthe Invention in accordance with the present invention, a video overlay controller synchronizes a local source of video, such as computer-generated video, with an external video source, such as a video disk, by separately locking the vertical and horizontal synchronizing signals of one source (e.g.the local source) to the corresponding signals of the othersource (e.g. the external source) in such a manner as to achieve both horizontal and vertical synchronization essentially simultaneously and independently, and within no morethan eightfieldtimes (i.e., approximately 1,7 second) at most. When the two video sources are then overlaid on a video displayforsimultaneous display, the resultant composite image is highly stable both vertically and horizontally.

Vertical synchronizing circuitry measures the time ofoccurrence of the vertical synchronizing signals of the local source with respect to that of the external source and, ifthe difference exceeds a defined amount (specifically, one-halfthe duration of a horizontal scan), activates scan correction circuitry which brings the time difference to within one-ha If the horizontal scan time. Horizontal correction circuitry simultaneously reduces errors of less than one-half scan time essentiallyto zero. The horizontal and vertical synchronization are accomplished in a manner that is essentially independent of each other. Thus, once vertical synchronization is achieved, continued operation to achieve horizontal synchronization does not interfere with or otherwise affect the vertical synch ronization.

The controller ofthe present invention accepts inputs from an external source such as a video disk player, tape player, computer video generator, orthe like, as well as from one or more internal video sources such as a video display controller or a color graphics adapter. The scanning format ofthe sources may differ. Thus, video disk players typically provide outputs in accordance with NTSC standards; these provide for interlaced scanning. Video display processors may accomodate either interlaced or noninterlaced scanning, while color graphics adapters, such as the IBM Color Graphics Adapter, typically provides non-interlaced scan. In the present invention, because of the manner in which synchronization is achieved, both types of sources may be mixed without special precautions.

Detailed Description ofthe Invention Theforegoing andotherandfurtherobjectsofthe invention will be more readily understood from the following detailed description of the invention, when taken in conjunction with the accompanying drawings, in which: Fig. lisa blockand line diagram of video overlay controller in accordance with the present invention; and Fig. 2 is a sequence oftiming waveforms illustrating the operation ofthe circuit of Fig. 1 in achieving synchronization.

In Fig. 1, a synchronizing circuit in accordance with the present invention receives inputs from three sources, namely, a video disk player 10, a color graphics adapter 12, and avideo display chip 14. The video disk 10 provides as output a standard (NTSC) composite video signal including both video and synchronizing components. The composite (vertical and horizontal) synchronizing signals are separated in a sync separator 15, and the resultant composite sunchronizing signal (NTSCCYYNC) is fed via a lead 16 to a multiplexer 18. This signal typically is adapted for an interlaced scan. In contrast, the color graphics adapter (e.g., a standard IBM Color Graphics Adapter) may utilize a non-interlaced scan.Despite this difference in the characteristics ofthe signals, the circuit of the present invention readily accomodatesthese diverse sources to provide a clock signal for the computer-generated graphic display that is synchro nized with the particular source that is selected for the external graphics.

Avertical synchronizing signal (NTSCVSYNC) is derived in a known mannerfrom the composite signal via a circuit 20 that may simply comprise an integrator followed by a Schmitt trigger; the resultant is applied to a multiplexer22 via a lead 24. The color graphics adapter 12 provides a vertical synchronizing signal (CGAVSYNC) on a lead 26, and a horizontal synchro nizing signal (CGAHSYNC) on a lead 28. These signals are applied to multiplexer 18 via an OR gate 30 (which combines them to form a composite synchronizing signal) and a lead 32, and to multiplexer 22 via a lead 33. Finally,the video display processor 14 provides a composite synchronizing signal on a lead 34 which is applied directly as an inputto the multiplexer 18.A vertical synchronizing signal VDPVSYNC is derived from the composite signal via an integrator36 and is applied to the multiplexer 22 via a lead 38.

Multiplexers 18 and 22 each select one ofthe inputs applied to them and provide the selected inputs as outputs on leads 40,42, respectively. The selection is performed in accordance with the state of switching inputs CGAENABLE and CLKREL applied to control terminals 44,44' and 46,46', respectively. These signals select output from the video disk, the colour graphics adapter, orthe video display controllerfor overlay with respect to each other. The output of multiplexer 18, which is applied to lead 40, is a composite synchronizing signal derived from one of the sources, while the output of multiplexer22,which ofmultiplexer22, which is applied to lead 42, is a vertical synchronizing signal selected from the same source.

The output of multiplexer 22 is applied to a missing pulse detector 50 which comprises first and second monostable multivibrators 52,54 ("one-shots"), respectively. The normal (O) output of multivibrator 52 is coupled to the negative transition input of multivibrator 54. The normal (Q) output of multivibrator 54 is fed backto the negative transition input of multivibrator 52. RCtiming networks 56,58 control the duration ofthe output pulses ofthe multivibrators 52,54, respectively.

The multivibrators 52 and 54 respond to positive transitions in the input driving signal to provide outputs of controlled duration. The duration ofthe respective outputs of the multivibrators 52/54 is such thatthe trailing edge ofthe output of multivibrator 54 normally coincides in time with the leading edge ofthe positive-going input to multivibrator 52. When this is the case, the multivibrator 52 is triggered at both its inputs atthe same time, and the second input (from multivibrator54) is redundant, although harmless.If, however, the input to the positive transition input is missing from the input pulse train (due, for example, totheabsenceofserrations marking the horizontal pulses embedded within the composite synchronizing pulse),the trailing edge ofthe output of multivibrator 54triggers the multivibrator 52 atthetime it would havebeentriggeredhadtheinputsignal been a standard composite synchronizing signal. Multivibrator52then provides an output pulse atthe appropriate time, despite the absence of the normal input pulse.

The resultant output is then coupled via a lead 60to a monostable multivibrator 62 which provides an output of precisely defined duration for use as the horizontal synchronizing pulse in the video display device. It is also applied via a lead 64to the input of a flip-flop 66, as well as to the positive transition input of a monostable multivibrator 68 whose output pulse duration is set by an RC circuit 70 to provide a pulse having a 50% duty cycle atthe horizontal line frequency. Flip-flop 66 is clocked from the output of multipolexer 22 on lead 42. The output of flip-flop 66 comprises a vertical reference pulse (VREF) which triggers a monostable multivibrator 67 to form a vertical reset pulse which is applied to the processor 14via a lead.

The non-inverting (Q) output of multivibrator 68 is passed through a delay 74 which horizontally aligns the rasterwith the overlay, and is then applied via a lead 75 to a phase comparator 76. Comparator76 receives a second input comprising the video display processor composite sync signal VDPCSYNCfrom processor 14via a lead 77, and supplied an outputto processorl4viaalead8l foruseasahorizontal reference signal bythe processorto lock its horizontal frequency outputto HREF. The inverting output of multivibrator 68 is applied to the negative transition input of a monostable multivibrator78 having an RC network 80 for setting the time constant of the resultant pulse, as well as to a lead 82 for use as a horizontal gating signal (H30) and to the clock input of a D-type fl ip-flop 84.The output of multivibrator 78 is applied to a lead 86 for use as a horizontal blanking signal.

In accordance with the present invention, vertical and horizontal synchronization of the computergenerated display (which is controlled by eitherthe color graphics adapter or by the video display processor) is attained for the color graphics adapter by means of two separate and essentially non-interacting control sections, namely, a vertical sync section 100 and a horizontal sync section 102, and forthe video display processor by the HREF and VREF signals described above. The section 100 includes the flip-flop 84which resets a flip-flop 104through a differentiator 106. Flip-flop 104 is clocked from a flip-flop 108 which receives a data (D) input comprising the vertical sync signal CGAVSYNCfrom the color graphics adapter 12 via lead 26 and a delay circuit 110.Flip-flop 108 is clocked by the horizontal syncsignal CGAHSYNC from adapter 12 via lead 28. The output of flip-flip 104 derives the data (D) input of a flip-flop 112 which also is clocked bythe horizontal syncsignal CGAHSYNC from adapter 12 and is reset by the clock release signal CLKREL.

As will shortly be seen below, the output offlip-flop 112 is a pulse whose duration is a measure ofthe misalignment between the vertical synchronizing signal NTSCVSYNC of the disk 10 and that ofthe adapter 12 (CGAVSYNC). This pulse is applied to a flipflop 11 4whose output in turn is applied to a J-K flip-flop 11Gwhich derives an OR gate 118. Flip-flops 1 14and 116 are clocked from the output ofthe horizontal synchronizing section 102 which is formed from a monostable multivibrator 120, a phase comparator 122, and a voltage controlled oscillator 124.

Multivibrator 120 is triggered from the horizontal synchronizing signal CGAHSYNC which is applied to its positive-transition input, and applies its output to phase comparator 122. The latter also receives an input comprising the horizontal reference signal HREF from lead 76. The difference between these signals drives oscillator 124. The output of oscillator 124 is also applied through the gate 118, togetherwith the output of flip-flop 116. The resultant output of 118 is applied via a lead 126 to the clock input (CLK) of the color graphics adapterto setthe fundamental operating frequency ofthe latter.

Turning now to fig. 2, the achievement of vertical synch rnnization will now be described in detail.

Assume that computergenerated video (whose display isto be controlled by the color graphics adapter 12) isto be overlaid on the output ofthe disk 10. In that case, the multiplexers 18 and 22 are enabled to select their inputs from the disk 10. The composite synchronizing signal (NTSCCSYNC) from the disk 10 is then used to derive the horizontal synchronizing signal 202 (H30) via the missing pulse detector 50 and flip-flop 68.

The first horizontal pulse 202 after the vertical pulse 200 (NTSCVSYNC) triggers multivibrator 84 which then provides an output pulse 204 at its 0 output, and the inverse 206 at its complementary output Q. The leading edge of pulse 206 is differentiated in differentiator 106 to form a trigger 208 which resets flip-flop 104. Pulse 208 forms the end of a "window" 210 which extends for one-halfthe horizontal sync period on either side ofthe preceeding horizontal synchronizing pulse embedded in NTSCCSYNC.

Assume now that the operation ofthe adapter 12 is such that its vertical synchronizing signal 220 (CGAV SYNC) occurs atthetime shown in Fig. 2 in relation to the disk vertical synchronizing signal 200; thus, it falls within a half-scan line of the video vertical synchronizing signal, NTSCVSYNS. Note that this lies within the "window" 210. (The leading edge ofthe horizontal synchronizing signal (CGAHSYNC) of the adapter is slightly displaced from alignment with that of the vertical signal in orderto avoid ambiguity when the horizontal signal is used to clockthevertical signal in theflip-flop 108).Thefirst horizontal signal 222' occurring after the vertical signal 220 setsflip-flop 108.

The output 224 ofthis flip4lop in turn triggers flip-flop 104.The latter remains "set" until the arrival ofthe reset pulse 208 from flip-flop 84. The resultant output of flip-flop 104 is shown at 226 in Fig. 2. The output (226) offlip-flop 104 is applied as inputtoflip-flop 112 but fails to set this flip-flop since it terminates before the subsequent clock input 222 to the flip-flop 112.

Thus, the output offlip-flop 112 remains at the "low" or "reset" level as shown at 228 in Fig. 2. Accordingly, flip-flop 114 remains reset, as does flip-flop 1 16 whose output is shown at 230 in Fig. 2. The output of OR gate 118 is then supplied solely by oscillator 124 as shown at 232 in Fig. 2.

Now assumethat the vertical synchronizing signal CGAVSYNC occurs at an earlier time as shown at 240 in Fig. 2. Atthefirst horizontal synchronizing signal CGAHSYNC (shown at 242' in Fig. 2) following the vertical signal,flip-flop 108 is set (signal 244, Fig. 2) and flip-flop 104 is then set (246, Fig. 2) from flip-flop 108. As was previously the case, flip4lop 104 is reset by the pulse 208. However, priortothis reset, the horizontal pulse 242" sets flip-flop 112 (waveform 248, Fig. 2) from flip-flop 104 as shown at 248 in Fig. 2. This in turn setsflip-flop 114 and then flip-flop 116 (waveform 250, Fig. 2) on the next clock pulse from oscillator 124.Flip-flop 116 then toggles between the "set" and "reset" states in responseto successive clocking signal from the oscillator 124.

When in the "set" state, the output of flip-flop 116, when applied to gate 118, effectively masks the output of oscillator 124, as shown at 252 in Fig. 2. When reset, it allows the oscillator output to pass through the gate without interference. Thus, the effective output of gate 118 (waveform 252, Fig. 2) is a clock signal that is at one-halfthe frequency of the oscillator output as long as flip-flop 114 is set. Accordingly, the next horizontal synchronizing pulse, which would normally occur at 242c as shown in Fig. 2, is delayed and occurs instead atthe time shown at 242d. When it does occur, it terminatestheoutputofflip-flop112andthusof flip-flops 114 and 116.Accordingly, the output of oscillator 124 passes through gate 1 18withoutinter- ruption, and thus at its normal rate. The phase misalignment of the adapter vertical synchronizing signal with respect to the disk vertical synchronizing signal is thus effectively halved during each field time, until itisbroughtwithinonehalfscan line ofthe disk synchronizing signal, at which time further correction is made by the horizontal correction circuitry only. In this manner, vertical synchronization is rapidly achieved, and within no morethan eight field times, at most (since eight halvings arethe maximum required to cover a phase misalignmentofonefullfield).

Further, it is accomplished essentially independently ofthe horizontal synchronization, since vertical phase correction is accomplished using onlyfull multiples of scan lines. Thus, horizontal phase correction can proceed concurrentwith vertical phase correction, and the time required to achieve synchronization is thereby further reduced. Further, the shift in the effective clock rate in the vertical circuitry during vertical phase correction serves to accommodate the non-interlaced color graphics adapter to the interlaced video disk output, and interlaced and non-interlaced sources are thus handled by the circuit of the present invention.

Returning now to the horizontal synchronizing section 102 in Fig. 1,theoscillator 124 provides the basic timing frequency for the adapter 12, as previously noted. In one physical embodimentofthe present invention, this oscillator was set to operate at a frequency of 14.34965 megahertz. The instantaneous frequency ofthe oscillator is established by the output of phase comparator 122 which in turin is dependent on the difference between the time of occurrence of the horizontal synchronizing signal CGAHYNC as applied to junction 122 via the one-shot 120, and the horizontal reference signal HREF. Anytime difference between these signals causes the oscillator 123 to speed up orslowdown asappropriateandthus bring the two signals into synchronization. Thus, both vertical and horizontal synchronization are rapidly achieved, and in a manner that is essentially independent of each other.

CONCLUSION Fromtheforegoing itwill be seen that I have provided an improved video overlay controller. The controller synchronizing signaisthat locks the diverse sources to each other within at most eight display field timesto provide an unusually stable display. Both interlaced and non-interlaced sources may be mixed for display.

Claims (9)

1. A video display controller, comprising: A. means for receiving primary and secondary video signals containing horizontal and vertical syn chronizing signalsforcontrolling a rasterscan display, B. means forforming from said primary video signal a primary reference signal synchronized with said primary horizontal synchronizing signal and occurring in specified relation to said primary vertical synchronizing signal, C. means forforming from said secondary video signal a secondary reference signal synchronized with said secondary horizontal reference signal and occur ring in specified relation to said secondary vertical synchronizing signal, and D. controlling means selectively responsive to said primary and secondary reference signals for controlling the instantaneous rate atwhich said secondary synchronizing signals are generated.

2. Avideo display controlleraccording to claim 1 in which the means forforming said primary reference signal comprises means responsive to the occurrence of a primary horizontal horizontal synchronizing signal subsequentto the occurence of a primary vertical synchronizing signal.

3. Avideodisplaycontrolleraccordingtoclaim 1 in which said controlling means responds to said primary and secondary reference signals only when the time difference therebetween is greaterthan a predefined amount.

4. Avideodisplaycontrolleraccordingtoclaim 1 in which said controlling means responds to said primary and secondary reference signals only when the time difference therebetween is greaterthan the time ofapproximatelyone-half horizontal scan line.

5. A video display controller according to claim 1 in which said controlling means comprises (1) an oscillatorforsupplying timing pulses to a masterclockfrom which the timing relationships of said secondary synchronizing signals are derived, and (2) means responsive to said primary and secon- dary reference signalsforgenerating a gating signal whose duration is indicative ofthetime difference between said reference signals, (3) means responsive to said gating signal for selectively limiting the application of said timing pulsestosaidclockwhensaidgating exceedsa predetermined duration.

6. Avideo display controller according to claim 1 in which said controlling means includes means for adjusting the vertical phase of said secondary video signal by integral numbers ofscan lines.

7. Avideo display controller according to claim 6 in which said controlling means further includes means for generating secondary horizontal synchro- nizing signals concurrent with secondary vertical synchronizing signals to thereby concurrently provide vertical and horizontal synchronization.

8. Avideo display controller, comprising A. means for extracting vertical and horizontal synchronizing signals from a first video source that is to serve as a master source, B. means including a controllable clock generator for generating vertical and horizontal synchronizing signalsfor controlling the display of a second video source synchronously with said first source, C. means for generating a first signal indicative of the misalignment ofthe vertical synchronizing signal of said second source with respect to that of said first source, and D. meansforming a vertical correction circuit responsiveto said first signal for applying vertical correction signals to said clock only when said first signal exceeds a predetermined amount

9. Avideo display controller substantially as described herein with reference to the accompanying drawings.