GB2152310A - Apparatus for effecting conversion between digital and analogue electrical signals - Google Patents
Apparatus for effecting conversion between digital and analogue electrical signals Download PDFInfo
- Publication number
- GB2152310A GB2152310A GB08334645A GB8334645A GB2152310A GB 2152310 A GB2152310 A GB 2152310A GB 08334645 A GB08334645 A GB 08334645A GB 8334645 A GB8334645 A GB 8334645A GB 2152310 A GB2152310 A GB 2152310A
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- United Kingdom
- Prior art keywords
- converter
- digital
- tertiary
- dac
- binary
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-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/78—Simultaneous conversion using ladder network
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
A converter for effecting conversion between digital and analogue electrical signals has a radix that is an odd integer greater than 2, preferably 3. In the preferred case the converter is based on a 2R/3R, 3R ladder network. The input for a digital to analogue converter may be derived by a circuit (Fig. 4) receiving sixteen-bit binary words and providing tertiary words in the (decimal) range 55,805- 121,340. <IMAGE>
Description
SPECIFICATION
Apparatus for Effecting Conversion Between Digital and Analogue Electrical Signals
This invention relates to apparatus for effecting conversion between digital and analogue electrical signals, that is it relates to a digital to analogue converter, for convenience referred to hereinafter as a DAC, and to an analogue to digital converter, for convenience referred to hereinafter as an ADC.
Conventional DACs receive a binary input signal having the number of bits required by the particular application, and operate on the principle of an R/2R ladder network to produce a current output signal that is the analogue of the input signal. The output current given by the ladder network itself is normally unidirectional, but it is well known that a bidirectional output can be obtained by using an appropriate resistor and operational amplifier in conjunction with the ladder network.
A bidirectional output is required in many fields where DACs find application, for example in an audio reproduction system in which the signals to be reproduced are stored in binary form. One such system is the so-called compact disc system, which holds a recording in 16 bit binary code.
Accurate audio reproduction is most difficult at low amplitudes, i.e. around the region where the output voltage from the DAC is zero. It is unfortunate that with conventional DACs producing bidirectional output the zero output point is the point at which all bits of the binary input signal change, and the zero output point thus occurs in the most inaccurate transfer region of the DAC. For example, a perfect 16 bit DAC has a signal to noise ratio of 96 dbs and at high output levels distortion due to switching in the ladder network is not discernible. However, at low output levels switching distortions do become discernible, and it is at just these levels that the highest incidence of switching occurs. This will be apparent from Table 1, which shows a 16 bit bidirectional binary input signal expressed in hexadecimal form and the corresponding output voltage from a conventional
DAC.At the zero output level the input signal changes from 7FFFto 8000, and thus all switches in the ladder network are required to change.
To achieve quality audio output from a conventional 16 bit DAC the first resistor in the ladder network is required to be accurate to 1 part in 215(32768). This is extremely difficult to achieve, and manufacturers of compact disc reproduction systems in practice use additional circuitry in order to compensate for distortion caused by the DAC at low output levels.
One known form of ADC effectively incorporates a
DAC and operates in each conversion time interval by sampling the analogue signal at the start of the interval, holding the sample, applying a sequence of digital input signals to the DAC, using a comparator to compare the DAC output with the sample and taking as the digital output signal that digital input signal that is current when the comparator shows identity between its two inputs. With a bidirectional analogue input there is again maximum switching activity in the DAC around the zero level of the input switch, and thus the highest potential inaccuracy in the region where maximum sensitivity could be required.
The object of the invention is to provide a DAC or an ADC that is significantly more accurate in the low amplitude region of a bidirectional analogue signal.
According to this invention there is provided a converter for affecting conversion between digital and analogue electrical signals, the converter having a radix that is an odd integer greater than two. The convertor may be either digital to analogue, or analogue to digital.
The conventional DAC and known ADC aforementioned each have a radix of two, that is they operate on the binary system, to base 2. It is this that determines that the centre point of the digital range is the point of maximum incidence of switching when producing a bidirectional analogue output signal, or when responding to a bidirectional analogue input signal. Using a convertor operating on an odd rather than an even radix enables the centre point of the range to be located at the point of minimum incidence of switching, i.e. where only the least significant digit of the digital signal changes.
Thus, the maximum accuracy is achieved at low analogue signal levels, exactly where it is most needed. It is obviously preferred that the zero level analogue signal coincides with the centre point of the digital range, although even if it is off centre it will often be possible to obtain more accurate conversion than with a conventional base 2 convertor.
Preferably a convertor according to the invention has a radix of three, that is it operates on the tertiary system to base 3. Table 2 is similarto Table 1, but shows the relationship between an 11 digit tertiary input signal and the corresponding bidirectional output voltage from a system centred on the digital range. It will be noted that in the region of zero output only the least significant digit of the tertiary input changes. Further, when the output swing is less than one-third full-scale (-9.5 dbs in an audio application) the most significant digit does not change; when the output swing is less than oneninth full-scale (-19 dbs) the most significant two digits do not change. Similarly, each time that the output reduces by a further 9.5 dbs one less significant digit changes.The consequence of this is that in audio reproduction from a digital signal source an 11 digit tertiary DAC of modest performance will produce better overall results than a 16 bit binary DAC of better nominal performance.
Accordingly, a tertiary DAC is very suitable for use in a compact disc or other binary audio reproduction system. Similarly, in the making of digital recordings, a tertiary ADC can produce more accurate reproduction of low amplitude sound inputs. Uses of DACs and ADCs according to the invention are not, of course, limited to audio application, and they will find use where a digital signal must be converted to an analogue a.c. signal having high sensitivity in the low amplitude output regions or where accurate binary representations of the low amplitude range of a bidirectional analogue input are required.
It is not essential that the convertor be a tertiary convertor, and the invention encompasses converters having a radix of five, seven or even higher. However, the tertiary convertor is preferred, as this can be manufactured more cheaply than those of higher radix, and indeed its response to a given fractional swing of the output signal is better than that of a convertor with a higher radix. If the convertor has an odd radix of n then a swing of 1/n in the audio signal causes a change in the most significant digit of the digital signal; thus, lower values of n give better response.
Preferably a tertiary DAC according to the invention operates on the principle of a 2R/3R,3R ladder network wherein each stage of the ladder has two output resistors, neither, one or both being switched to the output as determined by the associated tertiary input digit. A convenient method of expressing each digit in a tertiary word is to use two binary bits for each digit. Thus, each tertiary digit may be expressed as one of the three forms 00, 10 (or 01) and 11, and such expression affords a simple method of controlling switching of the two output resistors in each stage of the 2R/3R,3R ladder netork.
Similar principles may be adopted in a DAC having a radix higher than three.
In a digital electrical system signals are, of course, generally handled in binary form. In order to apply such signals to a DAC having an odd-number radix for analogue conversion it is necessary that the signals be converted from binary to the radix on which the DAC operates. Similarly, if the ADC converts an analogue input signal into a digital signal of odd radix it will be necessary to convert the digital signal into binary form. Circuits for converting digital signals from one base to another are known, and such conversion presents no problem to those skilled in the art. It should be mentioned however, that it is preferred that the centres of the binary signal range and of the odd-numbered radix signal range should coincide.
An example of a DAC in accordance with the invention will now be described and contrasted with the prior art with reference to the accompanying drawings in which: Figure 1 is an example of an existing DAC;
Figure 2 shows a circuit for obtaining a bidirectional output signal from a DAC;
Figure 3 shows an example of a DAC in accordance with the invention; and
Figure 4 is a block diagram of a circuit used to convert binary signals to tertiary signals.
The conventional method adopted to perform digital to analogue conversion is to use an R/2R ladder network as shown in Figure 1. The two outputs (I" 12) have to be at ground or virtual ground. The current flowing through the A0 switch is -Vref/2R, through the Al switch is -Vref/4R, and through the An switch is -Vref/2'"'"R. The output current at 1, is therefore,
-V refxlnput code
Rx216
and
V ref l2=I1 R
Due to the switches used within the DAC the output
current is normally unidirectional. To obtain a
bidirectional output the configuration shown in
Figure 2 is used, the block marked DAC comprising the ladder network of Figure 1. Resistor R, supplies
current equal to
V ref
2R
hence the output voltage will, in theory, be as
shown in Table 1.
However, as discussed above, the problem with a
binary DAC as shown in Figure 2 is that the most
inaccurate part of the transfer characteristic is
around zero output, where all the bits change.
Accordingly, poor differential linearity and
monotonicity occur at low output levels.
Figure 3 shows a ladder network used in a specific
example of an eleven digit tertiary DAC, according to the invention, i.e. a DAC having a radix or base of 3. Each stage of the network (corresponding to one
input digit) comprises two parallel output resistors
of values 3R, each resistor being connectable to output lr or 12 at ground or virtual ground through an associated switch. Each stage is connected to the
next through a resistor of value 2R.The current flowing through each of the a and b switches for
digit 0 is-V ref/3R through each of the a and b
switches for digit 1 is -V ref/9R and for digit n is -V ref/3(n+')R. The output current I, is therefore,
V refxlnput code
Ii
Rx3" and
V ref 12=11 R
In order to obtain a bidirectional output from the
DAC the circuit of Figure 2 is used, the block marked
DAC then comprising the network of Figure 3. In
practice, the circuit, including the 2R/3R,3R ladder
network, will be embodied in a microchip.
The tertiary DAC thus described will provide an analogue output in response to a tertiary input. The most convenient way of controlling the DAC is to express each digit of the tertiary input in two bit binary form, and use the binary form to operate the two parallel output switches in each stage of the ladder network. The logic for this is shown in Table 3. Thus, in each stage n either none, half or all of the potential maximum current from the stage -2V refl 3(n+ R can be switched to the conductor Ii or 12.
Reference is again made to Table 2, which shows the output from the tertiary DAC described above.
As already explained, in the region of the zero output only the least significant digit changes, i.e.
switching only occurs in the last stage of the ladder network. The significant advantages of this form of operation have already been explained and it will be apparent that for a given tolerance in the values of the resistors used in the ladder network of a tertiary and binary DAC, the monotonicity and differential linearity of the tertiary DAC will be greatly superior to that of the binary DAC in the region of zero output.
It has already been stated that in a digital electrical system signals are usually in binary form. To use them as input signals for a tertiary DAC they must be converted to tertiary form, and desirably the conversion is done so that each tertiary digit is expressed in two-bit binary form in order that the switches in the respective stages of the DAC may be operated in accordance with the logic shown in
Table 3. The numeric range of a tertiary word is not directly equivalent to that of a binary word, e.g., a sixteen bit binary word (range 65535) requires an eleven digit tertiary word (range 0--177146) to express it.In order to obtain maximum advantage from the use of a tertiary DAC the centres of the binary and tertiary ranges should coincide, thus in the example given binary 1000000000000000 must equal tertiary 11111111111, and the tertiary range actually used will thus be 55805121340.
There are several ways of performing a binary to tertiary conversion such that the requirements described above are met. A block diagram of one suitable circuit for performing a sixteen bit binary to eleven digit tertiary conversion is shown in Figure 4; as with the DAC itself the circuit may be embodied in a microchip.
In this circuit, the following sequence of events occurs for each individual conversion: 1. The counter and shift register are cleared and the binary register is loaded with the binary input numberto be converted.
2. The counter selects the binary equivalent of 55805 from the code converter and applies it on bus 1 to the logic unit 2. The binary input number is applied to the logic unit on bus 3, and the unit adds together the two numbers, the result is loaded on bus 4 into the binary register. This action centres the ranges of the binary input and the tertiary output.
3. The counter is incremented and selects from the code converter the binary equivalent of 3'0, which is supplied on bus 1 to logic unit 2. The logic unit subtracts this from the contents of the binary register, supplied to the unit on bus 3.
4. If the result of this subtraction is positive a one is entered into the shift register, and the result of the subtraction is loaded on bus 4 into the binary register. If the result is negative a zero is entered into the shift register and the binary register retains the result obtained from stage 2.
5. Step 4 is repeated to give a second input of 1 or 0 to the shift register. The input to the shift register thus represents the most significant digit of the tertiary word in the two bit binary form given in
Table 3.
6. The counter is incremented and selects from the code converter the binary equivalent of 39, which is supplied on bus 1 to the logic unit 2. The logic unit subtracts this from the contents of the binary register, supplied to the unit on bus 3.
7. Steps 4 and 5 above are repeated and the second most significant tertiary digit is thus obtained and loaded in two bit binary form into the shift register.
8. The procedure in steps 6 and 7 above is repeated for binary equivalents of 3" selected from the code converter as n reduces from 8 to 0, so producing the loading into the shift register the two bit binary code for each tertiary digit in reducing order of significance.
At the end of this sequence the shift register contains the binary input signal in tertiary form.
Each tertiary digit represented in two bit binary code, and with the tertiary output and binary input ranges centred. The shift register content may be applied as the input signal to an 11 stage tertiary
DAC as shown in Figures 2 and 3, controlling the switches in each stage of the DAC to produce the required analogue output.
Compact discs are presently coded in 16 bit binary form, and accordingly the converter and DAC described above are suitable for use in the audio reproduction of such discs, and will give a varying response over the whole of the binary signal range.
A response that is clipped at the highest and lowest parts of a 16 bit binary signal (range 065535) could be obtained by converting to a 10 digit tertiary signal (range 0--59048). Alternatively, the binary signal could be multiplied by
59048
65535 (or 7/8 as a close approximation that is more easily effected) and the result converted to a 10 digit tertiary signal.
Either course may achieve some cost saving while sacrificing some fidelity at maximum amplitude without affecting it at low amplitude.
Other applications may require conversion of binary input signals having more or less than 16 bits. In each case conversion can be effected into tertiary code having a sufficient number of digits, and the tertiary signal used to operate a tertiary DAC having the required number of stages. The tolerance to which the DAC is manufactured may, of course, be selected as desired for the particular application.
It will be understood that a tertiary DAC as described may be incorporated into an ADC. In one example, an ADC operates on the principle of sampling and holding an analogue input signal, and comparing the held sample with the output from the
DAC as the input thereto varies until the comparator shows identity. At that time the DAC input is taken as the tertiary output signal that corresponds to the analogue input. A suitable conversion circuit may then be used to convert the tertiary signal to binary form for processing or storing as required.
Only one form of conversion circuit from binary to tertiary has been described and it will be apparent that other circuits for effecting this conversion, and that from tertiary to binary can be designed. Indeed, the conversion could be effected by a suitable ROM storing ail required outputs and selecting the appropriate output in response to a given individual input.
The foregoing discussion has been in terms of tertiary DACs and ADCs, but it will of course be understood that similar principles apply to DACs and ADCs having radices greater than 3, and to conversion circuits for use in converting a binary signal to and from the appropriate base.
Claims (7)
1. A converter for effecting conversion between digital and analogue electrical signals, the converter having a radix that is an odd integer greater than two.
2. A converter according to claim 1 in which the zero level analogue signal from orto the converter coincides with the centre points of the range of digital signals to or from the converter.
3. A converter according to claim 1 or claim 2 in which the converter has a radix of 3.
4. A converter according to claim 3 designed to operate on the principle of a 2R/3R,3R ladder network wherein each stage of the ladder has two output resistors, neither, one or both such output resistors being switched to the output as determined by an associated tertiary input digit.
5. A converter according to any one of the preceding claims, which is a digital to analogue converter.
6. A converter according to any one of claims 1 to 4, which is an analogue to digital converter.
7. A converter for effecting conversion between digital and analogue electrical signals, substantially as herein described, with reference to Figures 2 and 3 of the accompanying drawings.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB08334645A GB2152310A (en) | 1983-12-30 | 1983-12-30 | Apparatus for effecting conversion between digital and analogue electrical signals |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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GB08334645A GB2152310A (en) | 1983-12-30 | 1983-12-30 | Apparatus for effecting conversion between digital and analogue electrical signals |
Publications (2)
Publication Number | Publication Date |
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GB8334645D0 GB8334645D0 (en) | 1984-02-08 |
GB2152310A true GB2152310A (en) | 1985-07-31 |
Family
ID=10553945
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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GB08334645A Withdrawn GB2152310A (en) | 1983-12-30 | 1983-12-30 | Apparatus for effecting conversion between digital and analogue electrical signals |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0251758A2 (en) * | 1986-06-30 | 1988-01-07 | Fujitsu Limited | Digital-to-analog conversion system |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB734829A (en) * | 1948-08-17 | 1955-08-10 | Emi Ltd | Improvements relating to computing apparatus |
GB1178268A (en) * | 1966-05-18 | 1970-01-21 | Fujitsu Ltd | Analog to Multi-Valued Code Conversion System. |
GB1219148A (en) * | 1968-04-22 | 1971-01-13 | Int Standard Electric Corp | Non-linear decoder for ternary codes |
GB1220962A (en) * | 1968-04-22 | 1971-01-27 | Int Standard Electric Corp | Improvements to ternary coders |
GB2077536A (en) * | 1980-06-04 | 1981-12-16 | Robinson Alan Keith | Digital to analog converter |
-
1983
- 1983-12-30 GB GB08334645A patent/GB2152310A/en not_active Withdrawn
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB734829A (en) * | 1948-08-17 | 1955-08-10 | Emi Ltd | Improvements relating to computing apparatus |
GB1178268A (en) * | 1966-05-18 | 1970-01-21 | Fujitsu Ltd | Analog to Multi-Valued Code Conversion System. |
GB1219148A (en) * | 1968-04-22 | 1971-01-13 | Int Standard Electric Corp | Non-linear decoder for ternary codes |
GB1220962A (en) * | 1968-04-22 | 1971-01-27 | Int Standard Electric Corp | Improvements to ternary coders |
GB2077536A (en) * | 1980-06-04 | 1981-12-16 | Robinson Alan Keith | Digital to analog converter |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0251758A2 (en) * | 1986-06-30 | 1988-01-07 | Fujitsu Limited | Digital-to-analog conversion system |
EP0251758A3 (en) * | 1986-06-30 | 1990-08-29 | Fujitsu Limited | Digital-to-analog conversion system |
Also Published As
Publication number | Publication date |
---|---|
GB8334645D0 (en) | 1984-02-08 |
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732 | Registration of transactions, instruments or events in the register (sect. 32/1977) | ||
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