GB2034114A - Method of manufacturing a V- groove IGFET - Google Patents

Abstract

In a method of manufacturing a V-groove insulated gate field effect transistor, the required substrate is prepared by introducing impurity material into a surface of a semiconductor wafer (1) of one conductivity type to form adjacent the surface a first layer (3) of the other conductivity type, depositing on the first layer a further layer (5) of material of the one conductivity type, the part (5A) of which further layer adjacent the first layer being relatively highly doped due to out-diffusion from the first layer, and introducing impurity material into said further layer to form a region (7) of the other conductivity type within the part of the further layer not relatively highly doped. A V- groove (9) is then formed extending through the region and further layer into the first layer, and an insulating layer (11) with an overlying conducting layer (13) is formed in the groove (9). Connections (15, 17) are provided to layers (13, 17) and to region (7). <IMAGE>

Description

SPECIFICATION Transistors This invention relates to transistors.

The invention relates particularly to methods of manufacturing V-groove, insulated gate, fieldeffect transistors.

As is described, for example, in United Kingdom patent specification No. 1,488, 15 1, such transistors are conventionally produced on a substrate comprising an n-type wafer, a p-type layer on a surface of the wafer and a diffused ntype region which extends into the p-type layer.

The required V-groove, gate insulating layer, electrode structure and electrical connections are then formed, the n-type wafer and region respectively constituting the source and drain, and the part of the p-type layer adjacent the V-groove constituting the channel of the completed transistor. It will be appreciated that the p-type layer is critical in determining the transistor characteristics. In producing the substrate, the ptype layer may be formed by thermal deposition onto an n-type wafer, or by out-diffusing into an overlying thermally deposited layer p-type impurity from a wafer initially containing both ntype and p-type impurity or by out-diffusing into an overlying thermally deposited layer p-type impurity introduced into an n-type wafer by diffusion or ion implantation before formation of the overlying layer.

Of these various alternative processes, that involving out-diffusing p-type impurity from a wafer initially containing both n-type and p-type impurity is preferred. This is because control of the growth of a p-type layer on an n-type wafer by thermal deposition is difficult and thermally depositing a layer of material onto a wafer surface previously subjected to diffusion or ionimplantation followed by out-diffusion of impurity in the wafer into the layer either involves a risk of discontinuities at the interface between the wafer and layer if ion implantation is used, or presents the problem of accurately controlling the diffusion.

Unfortunately, however, suitable wafers containing both n-type and p-type impurity, i.e.

double-doped wafers, for use in the preferred alternative process are not readily commercially available.

Whilst V-groove, insulated gate, field effect transistors normally have an n-type source and drain, it will be appreciated that similar remarks to the above apply to such transistors of the opposite conductivity type, i.e. such transistors having a ptype source and drain.

It is an object of the present invention to provide a method of manufacturing a V-groove insulated gate field-effect transistor wherein one or more of the above described difficulties are overcome.

According to the present invention, a method of manufacturing a V-groove, insulated gate, fieldeffect transistor comprises the steps of: introducing impurity material into a surface of a semiconductor wafer of one conductivity type thereby to form a first layer of semiconductor material of the other conductivity type adjacent said surface; depositing on said first layer a further layer of semiconductor material of said one conductivity type, the part of which further layer adjacent said first layer being relatively highly doped with material of said one conductivity type due to out-diffusion from said first layer; introducing impurity into said further layer to form a region of said other conductivity type within the part of said further layer not relatively highly doped; forming a groove which extends through said region and said further layer into said first layer; forming a layer of electrically insulating material in the groove: providing an electrical conductor overlying a portion of the insulating layer adjacent said relatively highly doped part of said further layer; and providing electrical connections to said conductor, said region, and said first layer.

The impurity introduced into said surface of the seminconductor wafer is preferably introduced by diffusion.

It will be understood that the term V-groove is intended to include any indentation of suitable shape for formation of an insulated gate, field effect transistor on a wall thereof.

One method in accordance with the invention will now be described by way of example with reference to the accompanying cirawings in which Figures 1 to 5 illustrate various stages in the method.

Referring to Figure 1 the starting material is a wafer of p-type semiconductor material, for example, boron-doped silicon 1.

Using any suitable standard diffusion technique, an n-type impurity, for example antimony, is introduced into the wafer 1 via one of its main faces to form a layer 3 of n-type conductivity adjacent that main face of the wafer (see Figure 2).

Using any suitable standard thermal deposition technique, an epitaxial p-type layer 5 is then grown on the layer 5 (see Figure 3).

During formation of this layer 5 p-type impurity out-diffuses from the layer 3 so that the part 5A of layer 5 adjacent layer 3 is relatively highly doped with p-type impurity.

Using any suitable standard diffusion or ion implantation technique an n-type impurity is then introduced into a region of the layer 5 from its exposed surface, thereby to form an n-type region 7 in the layer 5, which extends part-way only through the less highly doped part of 5 B of the layer 5 (see Figure 4).

In the substrate thus formed one or more Vgroove insulated gate field-effect transistors are then fabricated using conventional techniques, a brief description of the necessary steps being given below, with reference to a single transistor.

Referring to Figure 5, firstly, a V-groove 9 is etched in the substrate formed as described above, the V-groove extending centrally through the region 7, through the layer 5 and into, but not through the layer 3. The V-groove 9 is suitably of square cross-section so that the groove 9 is in the form of an inverted pyramid.

A thin layer 1 1 of insulating material, for example, silicon oxide, is then formed all over the surface pf the groove 9, and a layer 13 of electrically conductive material, for example doped polycrystalline silicon, is formed on the surface of the insulating layer 11.

Leads 15 are then provided to the conductive layer 13 and the region 7. These leads are shown diagrammatically in Figure 4, but in practice are provided in conventional manner by selective removal of parts of an evaporated layer of metal, for example aluminium, laid down on a layer of insulating material, for example silicon oxide, in which apertures are provided to permit the required electrical contact between various parts of the transistor and remaining parts of the metal layer.

Finally a lead 17 is provided to the back of the wafer 1, and an electrical connection 19 is established between the wafer 1 and the layer 3, the head 17 thus effectively constituting an electrical connection to the layer 3. This connection is suitably made adjacent the edge of the substrate 1, 3, 5 and where several V-groove transistors are formed on the substrate, a single connection serves for all the transistors, the wafer 1 and layers 3 and 5 being common to all the transistors, although normally each transistor will he formed in a separate n-type region 7.

In operation the layer 3 constitutes the source of the transistor, the region 7 constitutes the drain of the transistor and the part 5A of the layer 5 adjacent the V-groove 9 constitutes the channel region of the transistor. The remainder of layer 5 adjacent the V-groove 9 constitutes a drift region.

The conductive layer 13 constitutes the gate electrode of the transistor.

It will be appreciated that in a method according to the invention the starting material is a single-doped wafer of readily available type.

Furthermore, the problems associated with controlling the growth by thermal deposition of a layer of one conductivity type on a wafer of the opposite conductivity type, and the problems associated with thermal deposition and subsequent out-diffusion on a surface previously subjected to diffusion or ion implantation are avoided. The former problems are avoided because it is the part 5A only of layer 5 which is critical in determining the transistor characteristics, and part 5A is produced by out diffusion. The latter problems are avoided because the form of layer 3 is not critical so that the diffusion used to form it need not be carefully controlled, and because layer 3 is formed by diffusion, not ion implantation. However, it will be appreciated that ion implantation might be used ta form layer 3 if the risk of surface discontinuities were small.

It will be appreciated that whilst in the particular embodiment of the invention described above, by way of example, the whole of one main surface of the wafer is processed to produce a substrate for V-groove transistor fabrication, in other embodiments of the invention only part of the area of a wafer face or two or more discrete areas of a wafer face may be so processed leaving the remaining area of the wafer face available for the fabrication of other semiconductor devices by other techniques.

Claims (5)

1. A method of manufacturing a V-groove, insulated gate, field-effect transistor comprising the steps of: introducing impurity material into a surface of a semi-conductor wafer of one conductivity type thereby to form a first layer of semiconductor material of the other conductivity type adjacent said surface; depositing on said first layer a further layer of semiconductor material of said one conductivity type, the part of which' further layer adjacent said first layer being relatively highly doped with material of said one conductivity type due to out-diffusion from said first layer; introducing impurity into said further layer to form a region of said other conductivity type within the part of said further layer not relatively highly doped; forming a groove which extends through said region and said further layer into said first layer; forming a layer of electrically insulating material in the groove; providing an electrical conductor over-lying a portion of the insulating layer adjacent said relatively highly doped part of said further layer; and providing electrical connections to said conductor, said region, and said first layer.

2. A method according to Claim 1 wherein the impurity is introduced into said surface of the semi-conductor wafer by diffusion.

3. A method according to Claim or Claim 2 wherein said electrical connection to said first layer is provided by providing an electrical connection to the part of the wafer into which impurity has not been introduced to form said first layer and an electrical connection between said part of the wafer and said first layer.

4. A method of manufacturing a V-groove transistor substantially as hereinbefore described with reference to the accompanying drawing.

5. A V-groove transistor manufactured by a method according to any one of the preceding claims.