GB2090701A - Improvements in or relating to input protection for MOS integrated circuits - Google Patents
Improvements in or relating to input protection for MOS integrated circuits Download PDFInfo
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- GB2090701A GB2090701A GB8134626A GB8134626A GB2090701A GB 2090701 A GB2090701 A GB 2090701A GB 8134626 A GB8134626 A GB 8134626A GB 8134626 A GB8134626 A GB 8134626A GB 2090701 A GB2090701 A GB 2090701A
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- 230000015556 catabolic process Effects 0.000 claims abstract description 42
- 239000012535 impurity Substances 0.000 claims abstract description 17
- 230000010354 integration Effects 0.000 claims abstract description 10
- 238000009413 insulation Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- 150000002500 ions Chemical class 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 238000002513 implantation Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 230000008021 deposition Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000001681 protective effect Effects 0.000 description 6
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 230000012447 hatching Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000021715 photosynthesis, light harvesting Effects 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 229910018125 Al-Si Inorganic materials 0.000 description 1
- 229910018520 Al—Si Inorganic materials 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Protection Of Static Devices (AREA)
- Amplifiers (AREA)
Abstract
An input protection device T1, RB against accidental over-voltages is provided for MOS integrated circuit devices of low supply voltage and high integration density including IGFETs M, with gate oxides 8 having a thickness not exceeding 500 ANGSTROM . The protection device comprises a lateral bipolar transistor T1 with its emitter 4 connected to earth and its collector 5 connected to the input I and to the gate electrodes G of the IGFETs.The base 3 region is strongly doped by ion implantation with impurities having a concentration greater than that in the other integrated circuit regions 1, 2 of the same polarity. In this manner, the breakdown voltage across the protection device is less than the breakdown voltage across the rest of the circuit. <IMAGE>
Description
SPECIFICATION
Improvements in or relating to input protection for MOS integrated circuits
This invention relates to a protection circuit and device against accidental input over-voltages for MOS (metal-oxide-semiconductor) integrated circuits of high integration density and low supply voltage which comprise insulated-gate field-effect transistors (IGFET), with gate insulation oxides having a thickness equal to or less than 500 .
MOS devices have an extremely high input impedance. In this respect, the input resistance is typically greater than 1014 ohms, and the input capacitance is typically of the order of 10-12F.
For this reason, they are particularly sensitive to the accumulation of static charges. This drawback is becoming increasingly more evident as the integration density of MOS devices increases, with shorter channels, less deep junctions and thinner gate insulators. As electric fields of an order of magnitude of 107v1cm cause breakdown of the silicon oxide, the gate oxides used in high integration density devices, which are particularly thin, are subject to this drawback even at voltages of 25-30 V.
During the manufacture, checking, assembly and other operations relating to the device, it is difficult if not impossible to avoid over-voltages of this order of magnitude due to the accumulation of electrostatic charges. The electrostatic charges, which are induced accidentally in particular because of careless handling by the operators, create very high electric fields which lead, in unpredeterminable zones, to the breakdown of the bipolar junctions present in the circuit, and of the IGFET gate oxides, this probability being greater the smaller the thickness of the oxides.
A protection device against input over-voltages for an MOS integrated circuit which comprises IGFETs must attenuate any over-voltages to a value less than the breakdown voltage of the IGFET gate oxides, and less than the breakdown voltage of the bipolar junctions present in the circuit.
Input over-voltage must not damage the protection device, even if repeated with time. The protection device must therefore dissipate the least possible energy during discharge, and the inevitable dissipation must take place in the most uniform manner in the various points, so minimising the thermal effects related thereto. The input protection device for an integrated circuit device must not degrade its quality and/or its speed of operation, it must be of small size, using a minimum number of elements and occupying the minimum possible topological area of the chip of the integrated circuit into which it is incorporated.
A known input protection device for MOS integrated circuit devices is constituted simply by a diode, of which the cathode is connected directly to the signal input terminal and to the gate of the IGFETs present in the circuit, whereas the anode is connected to the circuit earth terminal (Figure 1A) of the accompanying drawings, the breakdown voltage of the diode being less than the breakdown voltage of the gate oxides.
During normal operation, the diode does not conduct as it is reverse-biased. However, when an excessive positive voltage is applied to the input terminal, the diode breaks down, so conducting reversely.
Consequently, the resultant voltage applied to the gates, even in the case of over-voltage, should remain at the most equal to the diode breakdown voltage, i.e. less than the breakdown voltage of the gate oxides.
In reality, this type of protection device does not sufficiently protect the gate oxides from breakdown, because the dynamic impedance of a diode is much higher during reverse operation than during forward operation. This is because when under reverse breakdown operating conditions, very high currents (20-30 A) flow, and the voltage across the diode does not remain fixed at the breakdown voltage, but increases as the current increases, and thus the breakdown threshold value for the gate oxides can easily be exceeded.
However, the behaviour of the protection device comprising a diode is good from the point of view of energy dissipation within the protection device itself.
One improvement of the aforesaid protectiondevice comprises the addition of a resistor (generally diffused) in series between the input terminal and the gate to be protected, before the diode which is in parallel with the circuit (Figure 1 B) of the accompanying drawings.
The purpose of this resistor, indicated by Rs, is preciselyto limit the maximum current flowing through the protection diode. Compared with the single diode, the energy dissipation in the protection device is slightly greater, but the attenuation of the inputvoltages is better, with consequent better protection for the gate insulators against the danger of breakdown.
However, even the protection device comprising a diode plus resistor has drawbacks, namely it also attenuates the input signals and leads to disadvantages in high-speed operation, and in addition the maximum possible over-voltage attenuation is still not sufficient for protecting gate oxides having a thickness less than 500 .
The method for protecting MOS integrated circuits by means of a diode or diode plus resistor is analysed in the article by M. Lenzlinger entitled "Gate protection of MIS device", IEEE Trans. on Electron Devices, vol.
ED-18, April 1971, pages 249-257.
The article by F.H. De La Moneda et al., entitled "Hybrid Protective Device for MOS - LSI Chips" IEEE Trans, on Parts, Hybrids and Packaging, vol, PHP-12, No.3, September1976, pages 172-175, describes protection devices constituted by a lateral NPN transistor with its collector and emitter connected electrically to the input and substrate respectively, with its base inaccessible and with a gate, connected to the substrate, on the oxide which covers the input junction.
A device of this type with "thin oxide" has excellent characteristics with regard to attenuating over-voltages, but is particularly subject to second breakdown and to the descrutive events associated therewith. However, a lateral transistor with "thick oxide" cannot be used for MOS devices of high integration density because it attenuates the over-voltages to values which are still too high for the very thin gate oxides used.
According to the invention, there is provided an MOS integrated circuit of low supply voltage and high integration density, comprising a first signal input terminal, a second terminal for connection to earth, a third terminal for connection to a power supply, at least one IGFET transistor with gate insulation oxide having a thickness not greater than 500 A, and a protection device against input over-voltages comprising a lateral bipolar transistor with emitter and collector regions doped with the same type and same concentration of impurities as the source and drain regions of the IGFET transistor, the emitter region being electrically connected to the earth terminal and the collector region being electrically connected to the input terminal and to the gate electrode of the IGFET transistor, the impurity concentration in the base retion of the lateral transistor being much higher than in the other regions of the same polarity of the integrated circuit, the extension of the base region and the concentration of impurities therein being such as to provide the breakdown voltage and the triggering voltage of negative resistance phenomena of the lateral transistor at a value lower than the breakdown voltage of the gate insulating oxide and lower than the breakdown voltage of bipolar junctions included in the integrated circuit, and such as to provide the sustaining voltage of the lateral transistor at a value higher than the integrated circuit supply voltage.
It is thus possible to provide an input protection device and circuit for MOS integrated circuits of low supply voltage and high integration density and comprising IGFETS, which enables input over-voltages to be attenuation to voltage values such as not to cause breakdown of gate insulating oxides having a thickness equal to or less than 500 A, as required by the most advanced integration techniques, without drawbacks which in any way prejudice the operation of the integrated circuit protected.
The invention will be further described, by way of non-limiting example, with reference to the accompanying drawings in which:
Figure 1A shows the circuit diagram of an input protection device of known type, comprising a single reverse-biased diode connected to the input in parallel with the circuit to be protected;
Figure 1B shows the circuit diagram of an improvement to be protection device of Figure 1A, comprising the addition of a resistor in series with the input;
Figures 2a-2B show the circuit diagrams of two different embodiments of an input protection device of known type comprising a lateral NPN transistor with the gate above the input junction connected electrically to the substrate, and with respectively thin and thick oxide between the gate and junction;;
Figure 3 is a greatly enlarged plane section through the structure of an input protection device according to the invention;
Figure 4 shows one of the possible circuit diagrams which can represent an input protection device according to the invention; and
Figures 5, 6, 7, 8, 9 and 10 are greatly enlarged sections through part of an integrated circuit device comprising an input protection device according to the invention, and at least one IGFET, illustrating production thereof.
The same reference letters and numerals are used on the various drawings for corresponding parts.
The structure shown in Figure 3 comprises a monocrystalline silicon substrate 1 doped with P-type impurities, in which there are formed two regions 4 and 5 strongly doped with N-type impurities (this doping is indicated in the Figure by N+), separated by a region 3 strongly doped with P-type impurities (p++). The regions 4,3 and 5 constitute two parallel bipolar junctions indicated by 24 and 25, disposed close together.
The zones adjacent to the structure formed by the regions 4, 3 and 5 which form part of the so-called field, indicated by 2 in the figure, are doped with P-type impurities, but at a concentration greater than the substrate 1 and less than the region 3 (in the figure the doping in the zones 2 is indicated by P+). The regions 2 and 3, indicated by hatching of lesser and greater density respectively, are completely covered by a layer 9 of silicon dioxide. The oxide layer is superposed by a further layer of protective insulating material known as "P-Vapox", which completely covers the oxides and the diffusions, except in the electrode contact areas.
The electrodes 10 and 11 of the regions 4 and 5 are connected respectively to earth and to the connection means between the input and the circuit to be protected.
The structure of Figure 3 can be represented by the circuit shown in Figure 4.
The pair of parallel bipolar junctions 24 and 25 is represented by a transistor indicated by T1, of which the regions 3, 4 and 5 constitute the base, emitter and collector respectively.
The emitter is connected electrically to earth, and the collector is connected to the input terminal I and to the gate G of the IGFETs to be protected. The base of T1 corresponds to the region 3, without any electrode, and thus in the circuit diagram it is connected to earth through the resistor RB, which represents the resistivity of the block of semiconductor material.
In Figure 4, a single IGFET M1 is shown, to represent the entire integrated circuit to be protected.
Under normal operating conditions, i.e. when only the signal is present at the input, the transistor T1, of which the base-emitter junction is not biased, does not conduct. However when an accidental over-voltage is present at the input 1. such as can be caused by an accumulation of electrostatic charges, the collector-emitter voltage exceeds the transistor breakdown voltage, and there is an avalanche effect due to the electrons accelerated by the strong electric field generated. The transistor T1 breaks down, and the collector current increases rapidly. The collector current produces a voltage drop across the ohmic base resistance (rbb), of the transistor such as to directly bias the emitter junction.Charges are then triggered by the emitter region to increment the total collector current, for equal collector-emitter voltages.
The lateral transistor thus has "negative resistance" characteristics.
Such "negative resistance" phenomena are triggered at a collector-emitter voltage value (LVcEo) which is slightly higher than the breakdown voltage, and lead to a sudden reduction in the voltage VCE to a value Vs which is less than the breakdown voltage.
This collector-emitter voltage value remains approximately constant as the collector current further increases within a wide range of current values. Passage between the emitter and collector of a limit-less current for a constant collector-emitter voltage is known as the sustaining phenomenon.
As the gates of the IGFETs of the protected circuit are connected to the collector electrode of T1, even for an input over-voltage they will be subjected to a voltage which does not exceed the maximum voltage VCE ofT1, this being the triggering voltage LVCEO of the negative resistance phenomena.
A protection device according to the invention, shown with its circuit diagram in Figures 3 and 4, is integrated into a monolithic block of semiconductor material together with the MOS circuit to be protected.
Essentially, it is constituted by a lateral NPN transistor (T1), with its emitter and collector doped with
N-type impurities simultaneously and identically with the source and drain regions of the IGFETs of the MOS circuit, and with its base strongly and deeply doped with acceptor ions (P-type impurities) by ion implantation.
After suitable masking, the ion implantation enables a protection zone to be created which has different breakdown characteristics than the rest of the integrated device, thus determining for the protection device the very low breakdown voltage value necessary to prevent breakdown of the gate oxides of thickness equal to or less than 500 A in the case of input over-voltage, while maintaining higher breakdown voltages for the protected circuit in order to prevent difficulties during normal operation.
The concentration of base acceptor ions, which is much higher than in the other zones of the integrated circuit, determines the breakdown voltage value of the lateral transistor, and this value must be less both than the breakdown voltage of the gate oxides and than the breakdown voltage of the bipolar junctions of the integrated circuit.
The triggering voltage LVCEO for the negative resistance phenomena must also be kept lower than the breakdown voltage for the oxides and lower than the breakdown voltage for the junctions. It can be controlled by implanting acceptor ions into the base zone 3, as a function not only of the ion concentration as for the breakdown voltage, but also of the depth of implantation and width of the zone concerned with this implantation, i.e. the distance between the two bipolar junctions of the lateral transistor. The dose of acceptor ions implanted into the base also determines the value of the sustaining voltage Vs at which the VCE of the transistor stabilises for high collector current values, and which is less than the breakdown voltage.
It is very important for the voltage Vs to be greater than the supply voltage of the integrated device of which the protection device forms part. Otherwise, having exceeded the breakdown voltage because of a non-dangerous input over-voltage, the power supply unit would provide sufficient energy to cause breakdown of the device.
Typical values of one embodiment of the protection device according to the invention for integrated MOS devices of high integration density, with a supply voltage of 5 V, and comprising IGFETs with gate insulators of 500 A are as follows:
- breakdown voltage across the protection device: 15 V (breakdown voltage across the rest of the
circuit: 30-35 V)
- triggering voltage for negative resistance
phenomena (distance between the junctions: 4Fm) 17V
- sustaining voltage: 9-11 V
From the energy dissipation aspect, a protection device according to the invention constituted by two parallel bipolar junctions, of which one is connected to earth and which are separated by a heavily doped zone, shows very good behaviour particularly when very high currents flow into the protection device.If the current exceeds certain threshold values when under the sustaining condition, instability phenomena usually occur known as the second breakdown, with destructive effects for the device itself.
In a protection device according to the invention, the current is distributed uniformly along the entire protection device, thus limiting the current density at individual points to non-dangerous values.
The total energy dissipated in the protection device is the usual value for known protection devices with lateral bipolar transistors, and is thus fairly low relative to other types of protection devices.
A manufacturing process for MOS integrated circuit devices comprising N-channel IGFETs which is suitable for the simultaneous formation of the protection device according to the invention without the quality and speed of the integrated circuit device being prejudiced, can be effected by a modification of the process known to experts of the art as the Planox process.
This modification consists of two additional operations, one of masking and one of ion implantation.
With reference to Figures 5,6,7,8,9 and 10 which show a plan view of the section through part of the integrated device with an input protection device according to the invention during the various manufacturing stages, the process thus modified comprises the following operations::
- formation (by high temprature oxidation) of a protective layer 21 of silicon dioxide on the major surface of a silicon wafer 1 doped with P-type impurities;
- deposition of a layer 22 of silicon nitride (Si3N4) on the oxidised surface (Figure 5);
- formation, by means of photoresist 23, of a first protective mask on certain zones of the silicon nitride layer;
- chemical attack of the parts not protected by the photoresist layer, so that the nitride layer remains only in the protected zones;
- ion field implantation, in the manner known to experts of the art, of a P-type doping agent, with energy sufficient to pass only through the silicon dioxide layer but insufficient to pass through the superposed layers of silicon dioxide, nitride and photoresist. In Figure 6 the regions doped in this manner are indicated by hatching and with the symbol P+.
In the preferred embodiment of the invention, acceptor ions are implanted with implantation energy of 120
KeV and a doping level of about 8.1012 ions/cm2;
- removal of the protective photoresist mask followed by deposition of a new protective layer 24 of photoresist (Figure 7) to form a second protective mask;
- ion implantation of P-type acceptor ions having energy sufficient to pass through the layer of silicon dioxide but insufficient to pass through the layer of photoresist; this implantation is carried out in region 3 which was already concerned in the preceding field implantation, through an aperture in the photoresist mask; in zone 3, indicated by denser hatching and with the symbol P++, a P-type impurity concentration is obtained which is much higher than in the other P zones of the integrated device;
- in the preferred embodiment of the invention, ion implantation is used with implantation energy of 120 Key, to obtain a doping level ofabout2.1013ions/cm2; region 3 has a constant width of between 4 and 10 Fm; - removal of the second protective mask of photoresist;
- high temperature oxidation, for a time sufficient to form a thick layer (9) of silicon dioxide on the silicon zones (Figure 8) not covered by nitride;
- chemical attack of the silicon nitride, which is removed using known selective chemical attack methods;
- gate oxidation.A thin oxide layer is created to constitute the dielectric 8 of the gate of the IGFETs included in the semiconductor device;
- deposition of a layer 18 of polycrystalline silicon;
- masking and chemical attack of the polycrystalline silicon. The polycrystalline silicon which is not removed constitutes the self-aligned mask necessary for the next operation;
- delimitation of the gate oxide of the IGFETs and chemical attack of the oxide not protected by the polycrystalline silicon;
- masking, deposition and high temperature diffusion of N-type impurities into the semiconductor substrate to form the source region 6 and drain region 7 of the IGFETs included in the circuit; ;
The two N-type regions 4 and 5 of the input protection device are formed simultaneously by the same operations, and these form with the region 3, which is heavily doped with P-type impurities, two bipolar junctions which are close together (4-10 um) and parallel (Figure 9);
- deposition of a protective layer 15 of "P-Vapox" (Figure 10);
- opening of the contacts 10, 11, 12, 13 and 14 in the P-Vapox;
- deposition and delineation of the interconnecting Al-Si layer;
- covering with final passivation and opening of the contact areas (pad).
Although only one embodiment of the invention and only one embodiment of the constructional process has been described and illustrated, it is apparent that numerous modifications are possible without leaving the scope of the invention.
Claims (2)
1. An MOS integrated circuit of low supply voltage and high integration density, comprising a first signal input terminal, a second terminal for connection to earth, a third terminal for connection to a power supply, at least one IGFETtransistorwith gate insulation oxide having athickness not greater than 500 A, and a protection device against input over-voltages comprising a lateral bipolar transistor with emitter and collector regions doped with the same type and same concentration of impurities as the source and drain regions of the IGFETtransistor, the emitter region being electrically connected to the earth terminal and the collector region being electrically connected to the input terminal and to the gate electrode of the IGFET transistor, the impurity concentration in the base region of the lateral transistor being much higher than in the other regions of the same polarity of the integrated circuit, the extension of the base region and the concentration of impurities therein being such as to provide the breakdown voltage and the triggering voltage of negative resistance phenomena of the lateral transistor at a value lower than the breakdown voltage of the gate insulating oxide and lower than the breakdown voltage of bipolar junctions included in the integrated circuit, and such as to provide the sustaining voltage of the lateral transistor at a value higher than the integrated circuit supply voltage.
2. An MOS integrated circuit substantially as hereinbefore described with reference to and as illustrated in Figures 3 to 10 of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT26063/80A IT1150062B (en) | 1980-11-19 | 1980-11-19 | INPUT PROTECTION FOR MOS TYPE INTEGRATED CIRCUIT, LOW POWER SUPPLY VOLTAGE AND HIGH INTEGRATION DENSITY |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2090701A true GB2090701A (en) | 1982-07-14 |
| GB2090701B GB2090701B (en) | 1984-09-26 |
Family
ID=11218547
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8134626A Expired GB2090701B (en) | 1980-11-19 | 1981-11-17 | Improvements in or relating to input protection for mos integrated circuits |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS57112076A (en) |
| DE (1) | DE3145592A1 (en) |
| FR (1) | FR2494501B1 (en) |
| GB (1) | GB2090701B (en) |
| IT (1) | IT1150062B (en) |
| NL (1) | NL189789C (en) |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2128829A (en) * | 1982-09-22 | 1984-05-02 | Rca Corp | Protection circuit for integrated circuit devices |
| GB2133926A (en) * | 1982-11-18 | 1984-08-01 | Nec Corp | Protection circuit |
| GB2151846A (en) * | 1983-12-16 | 1985-07-24 | Hitachi Ltd | A high voltage destruction-prevention circuit for a semiconductor integrated circuit device |
| DE3616394A1 (en) * | 1985-05-30 | 1986-12-04 | Sgs Microelettronica S.P.A., Catania | PROTECTIVE ELEMENT AGAINST ELECTROSTATIC DISCHARGE, ESPECIALLY FOR BIPOLAR INTEGRATED CIRCUITS |
| DE3615049A1 (en) * | 1986-05-03 | 1987-11-05 | Bosch Gmbh Robert | Voltage-protected semiconductor arrangement |
| US4725915A (en) * | 1984-03-31 | 1988-02-16 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit |
| US4742015A (en) * | 1984-03-07 | 1988-05-03 | Telefunken Electronic Gmbh | Method for producing a protective arrangement for a field-effect transistor |
| US4875130A (en) * | 1988-07-06 | 1989-10-17 | National Semiconductor Corporation | ESD low resistance input structure |
| US4893157A (en) * | 1984-08-24 | 1990-01-09 | Hitachi, Ltd. | Semiconductor device |
| US5077591A (en) * | 1986-09-30 | 1991-12-31 | Texas Instruments Incorporated | Electrostatic discharge protection for semiconductor input devices |
| US5139959A (en) * | 1992-01-21 | 1992-08-18 | Motorola, Inc. | Method for forming bipolar transistor input protection |
| US5189588A (en) * | 1989-03-15 | 1993-02-23 | Matsushita Electric Industrial Co., Ltd. | Surge protection apparatus |
| US5212618A (en) * | 1990-05-03 | 1993-05-18 | Linear Technology Corporation | Electrostatic discharge clamp using vertical NPN transistor |
| US5272097A (en) * | 1992-04-07 | 1993-12-21 | Philip Shiota | Method for fabricating diodes for electrostatic discharge protection and voltage references |
| US5428498A (en) * | 1992-09-28 | 1995-06-27 | Xerox Corporation | Office environment level electrostatic discharge protection |
| US5545910A (en) * | 1994-04-13 | 1996-08-13 | Winbond Electronics Corp. | ESD proctection device |
| US5591661A (en) * | 1992-04-07 | 1997-01-07 | Shiota; Philip | Method for fabricating devices for electrostatic discharge protection and voltage references, and the resulting structures |
| US5886386A (en) * | 1994-01-28 | 1999-03-23 | Sgs-Thomson Microelectronics S.A. | Method for making a bipolar transistor for the protection of an integrated circuit against electrostatic discharges |
| WO2010112281A1 (en) | 2009-04-01 | 2010-10-07 | Austriamicrosystems Ag | Integrated esd protection circuit |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60207383A (en) * | 1984-03-31 | 1985-10-18 | Toshiba Corp | Semiconductor device |
| FR2575333B1 (en) * | 1984-12-21 | 1987-01-23 | Radiotechnique Compelec | DEVICE FOR PROTECTING AN INTEGRATED CIRCUIT AGAINST ELECTROSTATIC DISCHARGES |
| IT1186227B (en) * | 1985-12-03 | 1987-11-18 | Sgs Microelettronica Spa | INPUT OVERVOLTAGE PROTECTION DEVICE FOR A MOS TYPE INTEGRATED CIRCUIT |
| US4739437A (en) * | 1986-10-22 | 1988-04-19 | Siemens-Pacesetter, Inc. | Pacemaker output switch protection |
| JPS63198525A (en) * | 1987-02-12 | 1988-08-17 | 三菱電機株式会社 | Overvoltage protector |
| EP0688054A3 (en) * | 1994-06-13 | 1996-06-05 | Symbios Logic Inc | Electrostatic discharge protection for integrated circuit semiconductor device |
| EP0851552A1 (en) * | 1996-12-31 | 1998-07-01 | STMicroelectronics S.r.l. | Protection ciruit for an electric supply line in a semiconductor integrated device |
| JP2013172085A (en) * | 2012-02-22 | 2013-09-02 | Asahi Kasei Electronics Co Ltd | Method of manufacturing semiconductor device and semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1179388A (en) * | 1967-11-02 | 1970-01-28 | Ncr Co | Electrical Protective Circuit for Metal-Oxide-Semiconductor Transistors |
| US3739238A (en) * | 1969-09-24 | 1973-06-12 | Tokyo Shibaura Electric Co | Semiconductor device with a field effect transistor |
| JPS5410836B1 (en) * | 1970-06-26 | 1979-05-10 | ||
| JPS526470B1 (en) * | 1971-04-20 | 1977-02-22 | ||
| NL176322C (en) * | 1976-02-24 | 1985-03-18 | Philips Nv | SEMICONDUCTOR DEVICE WITH SAFETY CIRCUIT. |
-
1980
- 1980-11-19 IT IT26063/80A patent/IT1150062B/en active
-
1981
- 1981-11-16 NL NLAANVRAGE8105192,A patent/NL189789C/en not_active IP Right Cessation
- 1981-11-17 GB GB8134626A patent/GB2090701B/en not_active Expired
- 1981-11-17 DE DE19813145592 patent/DE3145592A1/en active Granted
- 1981-11-18 JP JP56183933A patent/JPS57112076A/en active Pending
- 1981-11-19 FR FR8121665A patent/FR2494501B1/en not_active Expired
Cited By (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4484244A (en) * | 1982-09-22 | 1984-11-20 | Rca Corporation | Protection circuit for integrated circuit devices |
| GB2128829A (en) * | 1982-09-22 | 1984-05-02 | Rca Corp | Protection circuit for integrated circuit devices |
| GB2133926A (en) * | 1982-11-18 | 1984-08-01 | Nec Corp | Protection circuit |
| GB2151846A (en) * | 1983-12-16 | 1985-07-24 | Hitachi Ltd | A high voltage destruction-prevention circuit for a semiconductor integrated circuit device |
| US4742015A (en) * | 1984-03-07 | 1988-05-03 | Telefunken Electronic Gmbh | Method for producing a protective arrangement for a field-effect transistor |
| US4725915A (en) * | 1984-03-31 | 1988-02-16 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit |
| US4893157A (en) * | 1984-08-24 | 1990-01-09 | Hitachi, Ltd. | Semiconductor device |
| DE3616394A1 (en) * | 1985-05-30 | 1986-12-04 | Sgs Microelettronica S.P.A., Catania | PROTECTIVE ELEMENT AGAINST ELECTROSTATIC DISCHARGE, ESPECIALLY FOR BIPOLAR INTEGRATED CIRCUITS |
| DE3615049A1 (en) * | 1986-05-03 | 1987-11-05 | Bosch Gmbh Robert | Voltage-protected semiconductor arrangement |
| US5077591A (en) * | 1986-09-30 | 1991-12-31 | Texas Instruments Incorporated | Electrostatic discharge protection for semiconductor input devices |
| US4875130A (en) * | 1988-07-06 | 1989-10-17 | National Semiconductor Corporation | ESD low resistance input structure |
| US5189588A (en) * | 1989-03-15 | 1993-02-23 | Matsushita Electric Industrial Co., Ltd. | Surge protection apparatus |
| US5212618A (en) * | 1990-05-03 | 1993-05-18 | Linear Technology Corporation | Electrostatic discharge clamp using vertical NPN transistor |
| US5139959A (en) * | 1992-01-21 | 1992-08-18 | Motorola, Inc. | Method for forming bipolar transistor input protection |
| US5591661A (en) * | 1992-04-07 | 1997-01-07 | Shiota; Philip | Method for fabricating devices for electrostatic discharge protection and voltage references, and the resulting structures |
| US5272097A (en) * | 1992-04-07 | 1993-12-21 | Philip Shiota | Method for fabricating diodes for electrostatic discharge protection and voltage references |
| US5428498A (en) * | 1992-09-28 | 1995-06-27 | Xerox Corporation | Office environment level electrostatic discharge protection |
| US6265277B1 (en) | 1994-01-28 | 2001-07-24 | Sgs-Thomson Microelectronics S.A | Method for making a bipolar transistor for the protection of an integrated circuit against electrostatic discharges |
| US5886386A (en) * | 1994-01-28 | 1999-03-23 | Sgs-Thomson Microelectronics S.A. | Method for making a bipolar transistor for the protection of an integrated circuit against electrostatic discharges |
| US5545910A (en) * | 1994-04-13 | 1996-08-13 | Winbond Electronics Corp. | ESD proctection device |
| WO2010112281A1 (en) | 2009-04-01 | 2010-10-07 | Austriamicrosystems Ag | Integrated esd protection circuit |
| DE102009015839A1 (en) * | 2009-04-01 | 2010-10-14 | Austriamicrosystems Ag | Integrated ESD protection circuit and use of a bipolar transistor |
| DE102009015839B4 (en) | 2009-04-01 | 2019-07-11 | Austriamicrosystems Ag | Integrated ESD protection circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2494501A1 (en) | 1982-05-21 |
| DE3145592A1 (en) | 1982-07-15 |
| DE3145592C2 (en) | 1993-04-29 |
| NL8105192A (en) | 1982-06-16 |
| NL189789C (en) | 1993-07-16 |
| GB2090701B (en) | 1984-09-26 |
| IT8026063A0 (en) | 1980-11-19 |
| NL189789B (en) | 1993-02-16 |
| IT1150062B (en) | 1986-12-10 |
| JPS57112076A (en) | 1982-07-12 |
| FR2494501B1 (en) | 1985-10-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PE20 | Patent expired after termination of 20 years |
Effective date: 20011116 |