GB1598919A - Digital motor speed regulation - Google Patents

Description

PATENT SPECIFICATION

( 21) Application No 40474/79 ( 22) Filed 12 Dec 1977 ( 62) Divided out of No 1598918 ( 31) Convention Application No 749641 ( 32) Filed 10 Dec 1976 ( 31) ( 32) ( 33) ( 44) ( 51) ( 11) 1 598 919 ( 19) Convention Application No 749648 Filed 10 Dec 1976 in United States of America (US)

Complete Specification published 23 Sept 1981

INT CL 3 H 02 P 5/16 ( 52) Index at acceptance G 3 R A 34 B 389 B 424 B 436 B 58 BN 34 ( 72) Inventors PAUL JOHN ROUMANIS and DAVID LINDSAY LIPPITT ( 54) DIGITAL MOTOR SPEED REGULATION ( 71) We, GENERAL ELECTRIC COMPANY, a corporation organized and existing under the laws of the State of New York, United States of America, of 1 River Road, Schenectady 12305, State of New York, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:-

The present invention relates generally to digital motor speed regulator systems providing a method of controlling the flow of power from an AC source to a load such as a DC motor.

Motor control systems of the type described herein, frequently use power amplifiers having control rectifiers which vary the flow of electrical energy between an alternating current source and a drive motor Control rectifiers are well known in the art, and they generally consist of a family of devices which present a relatively high impedance to the flow of electrical energy until they are forward biased by a firing signal applied to a gate electrode At the time of conduction, the control rectifiers normally provide a very low impedance to the flow of current and normally continue to conduct current until they are back biased and/or the level of the current flowing through the rectifiers is decreased below a minimum holding level necessary to keep these rectifiers conducting The family of control rectifiers being discussed generally includes semiconductor devices such as silicon control rectifiers (thyristors) and other devices such as ignitrons and thyratrons.

In systems of the type being described, the amount of power transferred to a system load or DC motor is controlled by varying the duration of conduction of the controllable rectifiers Generally speaking, the duration of conduction of the controllable rectifiers is a function of the point during the AC wave form in which they are initiated into conduction This point is referred to as the firing angle.

In the past, systems for controlling the conduction of controllable rectifiers have generally been accomplished using analog control devices to perform the regulating functions required and converting the analog signal into digital values to fire the rectifiers In these types of systems, the firing circuits act in response to an input signal indicative of desired power to generate a firing pulse at the appropriate firing angle Generally speaking, the firing angle is directly proportional to the input signal Analog systems of the prior art generally operate in response to an input signal whose magnitude indicates the desired firing angle.

In recent years however, with the development of digital techniques and hardware, engineers have become interested in utilizing digital circuitry in these types of control systems The application of digital techniques to such control systems is particularly advantageous where the system requires that degree of accuracy, reliability or drift free operation, which is available only with digital circuitry.

Hence, it is becoming fairly common to replace elements of an analog system with functionally equivalent digital circuitry.

One such known digital control system for controlling the conduction of controllable rectifiers is disclosed in our U.S Patent 3,601,674 entitled -Control System for Firing SCR's in Power Conversion Apparatus".

2 1 9 1 2 In that patent, a digital control system is disclosed for controlling the flow of power through controllable rectifiers from a multiphase AC source to a load That system includes a firing circuit for each phase, where in each firing circuit comprises a reversible counter and a digital comparator.

Phase detection logic is incorporated which examines the three phases of the AC source so as to synchronously initiate a control interval for an appropriate rectifier by presetting a predetermined positive or negative digital number into the reversible counter associated with each phase The reversible counter then counts down, if the preset number is positive, or up if the preset number is negative, during the control interval During counting, a digital speed error signal, derived from a previous comparison of a digital command with a digital feed-back signal, indicative of motor speed, is continuously compared with the contents of the reversible counter by the digital comparator When the error exceeds the contents of the reversible counter, a firing pulse is generated which is supplied to a positive or negative poled rectifier, firing the respectively poled rectifier in accordance with the positive or negative number.

Another prior art system of the digital type has been described in two papers, the first by R D Jackson and R D Weatherby entitled "Direct Digital Control of Thyristor Converters" in "IFAC Symposium on Control and Power Electronics and Electrical Drives", October, 1974, held in Dusseldorf, Germany preprint Volume I, pages 431-441, and the second paper by F.

Fallside and R D Jackson, entitled "Direct Digital Control of Thyristor Amplifiers" in the proceedings of the Institute of Electrical Engineers, entitled "Control and Science".

Volume 116, No 5, pages 873-878, May, 1969.

In the above mentioned papers the authors describe a study of a laboratory system of the direct digital control type to demonstrate the feasibility of direct digital control of controllable amplifier such as silicon control rectifiers In this system a programmed digital computer is employed to control the firing of rectifiers through an interface apparatus to control a resistive capacitive load by the generation of firing pulses generated from the computer The digital computer computes the firing angle which specifies a time to fire a particular rectifier The system is synchronized to the zero crossings of the phase voltages of the AC source, such phase crossings generating command signals for a sample hold circuit of an analog to digital converter which measures the system load output voltage.

At the end of the analog to digital conversion a pulse is generated from the converter as an interrupt signal to the computer This pulse starts the firing angle calculation Subsequent to the initiation of the interrupt signal, the computer then reads the analog to digital converter at a specified time after the phase crossover instant The computer then proceeds to calculate the firing angle or firing instant for the rectifier utilizing what the authors describe as a given firing law In this calculation a control signal or value is developed which is continuously compared with a linear lookup table containing values defining the firing law until a match exists between the control signal and the contents of the table When a comparison is reached, a firing pulse is generated by setting up the address of the rectifier to be fired and strobing a firing signal to the rectifier.

While the authors did demonstrate the feasibility of direct digital control of controllable rectifiers, they also recognize that various practical difficulties were experienced in setting up a system of this type This was apparent in the most obvious implementation in these experiments of the use of lookup tables which takes a considerable amount of computer time and severely restricts the amount of additional computation time which may be done by the computer in operating a real time system of this type.

Further, it is to be recognized that direct digital drive control systems must sample the load output voltage at a specified instant in time as related to a detected phase interval of the AC source, then perform the necessary firing angle calculations and fire a selected rectifier within that detected interval, and at a time early enough in the specified interval in order to accurately and fully control the retardation of the firing angle to obtain maximum transfer of power to the load.

The above described systems did not function to perform as a total motor speed control system for controlling a variable speed reversible drive motor In analog systems the manner of controlling the speed of a DC motor, when operating in either continuous or discontinuous current mode, is well known as is the manner of reversing the direction of the motor It is also known that one of the criteria for reversing the direction of a DC motor is that the motor current be zero at the time of reversal In analog systems, in order to make this reversal, it is first necessary to detect when the current is zero and then to wait a specified safe period before reversing the motor Additionally, it is also known in analog motor drives systems, that it requires 1 598 919 1,598,919 two feed-back loops in the system, one to control the motor when it is in continuous current mode operation and one to control the motor when it is in discontinuous current mode operation These two loops provide separate gains to the system dependent upon the mode of operation.

This method of operation in analog control systems has proven to be somewhat unsatisfactory in DC motor drives systems, particularly wherein it is desired to achieve a high degree of constant motor speed operation under very light load conditions.

Thus, it is desirable to provide a DC motor speed drive and regulator system which enhances the overall operation of the system by providing a regulator which measures system parameters and accurately calculates motor speed, determines the mode of operation of the system, and promptly sets system gains, determines the motor direction of rotation and changes the direction of motor rotation instantaneously without a delay if required to do so.

According to the invention, there is provided a method of controlling a controllable rectifier connected between an AC source and a DC motor m a system of the type including a data processor programmed to calculate a firing angle to develop a firing pulse to fire the controllable rectifier to regulate the speed of the DC motor, comprising the steps of:

a) reading into the processor parameters corresponding to desired motor speed; b) directing the processor to: read a value corresponding to motor current; compare the value with a stored value corresponding to a predetermined current; establish a continuous or discontinuous current mode of operation according to the result of the comparison; select a system gain corresponding to the establish mode of operation; read, after a predetermined delay, a value corresponding to actual motor voltage; calculate a value for determining the firing angle as a function of the difference between the desired motor speed and the actual motor speed, the difference between the previously read motor current and the last read motor current, and the previously calculated firing angle determining value; read a first value corresponding to phase interval of the AC source from zero-crossings of the AC source; read a second value which is synchronized with the first value and represents an increment of time within the phase interval; calculate a time to use the firing angle determining value by comparing the second value with a predetermined constant proportional to system calculation time; calculate the firing angle determining value as a value proportional to required motor terminal voltage which is dependent on the selected system gain; derive an address of a rectifier to be fired from the first value; repeatedly compare the value of the calculated time to use the firing angle with the second value; and repeatedly incrementally changing the firing angle when the calculated time and the second value correspond; c) generating a firing pulse and sending it to the rectifier whose address has been calculated when the repeatedly incremented firing angle reaches a predetermined value; and d) repeating steps b) and c).

In order that the invention may be clearly understood, a preferred embodiment thereof will now be described by way of example only with reference to the accompanying drawings, in which:Fig 1 is a major block diagram of a regulating and control system encompassing the present invention.

Fig 2 is a simplified block diagram of a representative data processor for carrying out the invention.

Fig 3 illustrates in major block diagram form the regulator and rectifier control and rectifier of Fig 1 as connected to the data processor and load or DC motor.

Fig 4 is a detailed logic diagram of the 95 processor/system interface of Fig 3 showing its interconnection between the data processor and the other logic blocks of the regulator and rectifier control.

Fig 5 is a detailed logic diagram of the 100 system block of Fig 3.

Fig 6 is a timing diagram useful in the understanding of the operation of the system clock and the regulating and control system of the present invention 105 Fig 7 is a detailed logic diagram of the tach pulse counter and logic of Fig 3.

Fig 8 is a timing diagram useful in understanding the operation of the tach pulse counter and logic of Fig 7 110 Fig 9 is a detailed logic diagram of the firing logic of Fig 3.

Fig 10 is a timing diagram illustrating the timing of the firing logic of Fig 9 and is helpful in understanding the operation of 115 the present invention.

Figs 1 l A and 1 l B taken together with Fig 11 A placed at the top of Fig hl B illustrate in detailed logic diagram and schematic form the SCR select and drive 120 direction logic, rectifiers and the analog to digital converter of Fig 3 and the interconnections thus between.

Fig 12 shows curves helpful in understanding the operation of the present 125 invention.

Fig 13 is a bar chart flow diagram helpful in understanding the sequence of operation of the invention.

1,598,919 Figs 14 through 24 are flow charts useful in understanding the method of operation of the regulating and control system of the present invention.

In describing the overall operation of the invention, reference is now made to Fig I of a regulating and control system illustrating in major block diagram form the major functional blocks making up the present system In that figure a data processor shown generally as microprocessor 10 contains a program for controlling the overall operation of the system by reading parameter inputs to the microprocessor from a conventional DC motor 12 via a regulator and rectifier control 14 The program in the processor 10 controls the reading of these various inputs and contains a program for calculating the firing angle for the proper firing of rectifiers or thyristors commonly referred to as SCR's in a conventional 3-phase bridge rectifier 16 The regulator and rectifier control 14 provides a common interface between the processor 10 and the remainder of the control system Under control of the processor 10, the rectifier control 14 reads input signals from a speed reference 18 via a plurality of input lines, such signals being representative of a digital reference for which the motor is to run at in revolutions per minute, signals representative of an on/off power state of the motor and operator signals which are set designating the direction in which the motor 12 is to run These latter signals are provided via a plurality of conductors 20 designated Speed Ref Additional inputs to the processor 10, via the regulator control 14, are Speed signals from the DC motor 12 on a plurality of conductors 22 from a sensor on the motor 12 representative of the speed at which motor is running in rpm's Motor amperes is also measured by the microprocessor via the regulator and control 14 from current provided to the processor from the motor via a plurality of conductors 24 The regulator and control 14, under control of signals from the processor 10 provides control signals to the rectifier 16 and receives data from the processor to control the firing of the SCR's in the rectifier at the proper time to control the DC motor As will subsequently be described, the rectifier 16 is a forward/reverse bridge rectifier which can be enabled to reverse the direction of voltage and current through the motor 12 thus controlling its speed and reversing its direction.

The microprocessor 10 illustrated in Fig.

1 may be any one of a number of general purpose microprogrammed digital computers presently available on the market today One such computer suitable for application in the present invention is a micro computer sold by the Intel Corporation designated the Intel 8080.

Another ideally suited microprocessor, and that which is utilized in practicing the present invention, is a general purpose 70 microcoded digital computer sold by General Electric Company as a model CRD 8 Micro Computer System.

Referring to Fig 2, there is depicted the CRD 8 Microprogram digital computer 75 illustrating the main components of that computer The main control unit of the computer is comprised of a microcode control ROM 26 which is programmed with a microcode consisting of micro 80 instructions stored in the ROM The micro instructions, designated as enables to register, memory, and I/O channels on a plurality of conductors 28, control the fetching and interpretation of instructions 85 stored in a main memory or store 30, by first recognizing the instruction and then effecting the branching to a sequence of micro instructions in the control ROM that perform the actions called for by the 90 instruction The address of the next instruction to be interpreted by the micro code ROM is contained in a program counter register (PC) 32 Preceding the interpretation of each instruction, the micro 95 code ROM increments the contents of the program counter PC to point to the following instruction.

The micro code in the micro code ROM interprets sub-routine calls by placing the 100 address of the subroutine in a program counter save register (PCS) 34 and then interchanging the rolls of the program counter PC with the program counter save register PCS Subroutine returns are 105 interpreted by again interchanging the rolls of these latter two registers to thereby cause the instruction following the subroutine call to be interpreted next When an external interrupt occurs to the processor, the 110 processor interchanges the rolls of the program counter PC 32, the program counter save register PC 534, a page register (Page) 36 with an interrupt program counter 38, an interrupt program counter save register 115 (IPCS) 40, and an interrupt page register (IPAGE) 42 Interrupt returns are interpreted by the micro code in the micro code ROM by interchanging the roles of these registers back to their original roles 120 External interrupts provided to the processor may be enabled or disabled under program control by setting or resetting an interrupt enable flip flop not shown When an external device desires to interrupt the 125 processor, that device puts a request on the interrupt line If this request is present, and the interrupt enable flip flop is set, and the processor is executing an interruptable instruction, then the processor will start 130 1,598,919 processing the interrupt at the completion of the current instruction Once interrupt processing begins, the interrupt program is responsible for notifying the external input device to remove its request from the interrupt line The memory of the processor is divided into pages with a specified number of words per page Through the use of the page register 36, an instruction can access data anywhere in the memory by merely specifying an address relative to the head of the current data page (page pointed to by the page register).

Data in main memory 30 can also be accessed directly by loading an address of the data word into one or three general purpose registers designated RI, R 2 and R 3 respectively These registers can also be used to store data The collection of the three general purpose registers and the additional registers 32 through 42 are referred to as scratch pad memory.

In addition to the scratch pad registers, the processor also contains an accumulator 44, an instruction register 46 and a memory address register MAR 48, the latter for addressing the main memory 30 During operation of the processor, the instruction register 46 always contains the instruction which the microcode ROM last fetched from main memory and is currently interpreting The main memory address register 48 always contains the address in main memory that will be accessed by the next memory read or write instructions.

Arithmetic and logical operations are performed by an arithmetic and logical unit ALU 50 Input signals to the ALU are provided from the accumulator 44 and from a bidirectional data and control bus 52.

Data is transferred within the processor along the bus 52 This bus allows data to be transferred from either main memory 30, a selected scratch pad register, or an input channel 54 to either the instruction register 46, the memory address 48 or the ALU 50 If an input/output instruction is in the instruction register, and if that instruction specifies an output operation is to be performed, the processor places the contents of the ALU 50 on the output data channel via an output channel 56 and notifies the input/output (I/O) device involved to receive the data.

If a read operation is specified, the processor notifies the I/O device involved to place data in the input channel 54 As shown in Fig 2, the input/output devices involved in the present system are contained in the regulator and control 14 as previously described and duplicated in Fig.

2.

The processor 10 also includes a clock generator designated processor clock 58 which generates a basic clock signal at a representative repetition rate of 4 167 megahertz As shown in Fig 2, the basic clock signal is provided to the processor 10 to control the clocking of information and instructions through the processor and also to the system to serve as a basic synchronizing pulse for clocking information into and out of the regulator and rectifier control While the processor clock 58 was utilized in the present system to provide system clock pulses, it will be appreciated by those in the art that a basic clock signal could likewise be provided from an external source to the processor to serve the same function.

Reference is now made to Fig 3 which depicts largely in major block diagram form the blocks making up the regulator and rectifier control 14 Additionally, for clarity and simplification purposes in Fig 3, various ones of the components previously described in connection with Figs 1 and 2 are illustrated wherein like numbers are attached to those components as previously described As illustrated, the processor 10 provides the basic clock signals to a system clock 60 in the regulator control 14 The system clock 60 also receives a 3 phase 60 hertz power line signal from an external power source, not shown, and provides clock pulses to the system for use in synchronizing overall system operation with the 3-phase 60 hertz power line for controlling the firing of the SCR's to control the motor 12.

The regulator in control 14 also includes as a part thereof, a program 62 which communicates with the processor 10 to control the operation of the regulator in control 14 to ultimately provide the proper firing pulses to the thyristors or SCR's to control the DC motor While the program 62 may be contained in the main memory 30 of Fig 2, it is to be understood that the program 62 is considered a part of the regulator and rectifier control since it performs the specified logic functions essential to the operation of the overall control of the system.

Still referring to Fig 3, the previously mentioned speed reference 18 is shown as digital switches (rpm) and on/off and fwd/rev switches 18 ' in Fig 3, providing inputs to the processor 10 via a processor/system interface 64 A digital speed reference representative of the desired motor speed in rpm's is provided from the switches 18 via a plurality of conductors 66 and is read into the processor and stored in the main memory or program 62 under control of the processor In a similar fashion, signals representative of the motor on/off switch and a switch representative of the desired forward or reverse direction of the motor are provided to the processor from the 1,598,919 on/off and fwd/rev switches to 18 ' via the processor system interface 64 on conductors 68 Communication between the processor 10 and the processor system interface 64 is via a plurality of conductors comprised of data input/output lines and control lines As will subsequently be described, clock pulses from the system clock 60 are also provided over these lines to the processor during the operation of the system.

A firing logic 72 is employed in the regulator and control 14 to receive information representative of a desired firing angle, for firing the SCR's to control the motor This information is provided from the microprocessor via the processor system interface 64 on conductors 74 The firing logic 72 issues basically 3 signals, one is an interrupt signal on a conductor 76 to the processor 10 The interrupt signal can either circumvent or go through the interface 64 Another one of these signals is a convert signal on a conductor 78 to an analog/digital converter 80 to trigger that converter to convert the 3-phase analog motor current to a count proportional to DC amperes for transmission to the processor via conductor 24 and the interface 64 Additionally, the firing logic 72 generates a firing pulse on a conductor 82 to an SCR select and drive direction logic 84.

The SCR select and drive logic 84 receives digital information from the processor 10 via the interface 64 on a plurality of conductors 86 This information is representative of words or addresses to cause the proper selection of the thyristors to be fired and to select a particular one of two bridges (forward or reverse) in the rectifier 16 to control the motor direction.

The operation of the firing logic and the SCR select and drive direction logic will subsequently be described.

The aforementioned speed signals on conductors 22 are provided from a tach pulse counter and logic 88 of Fig 3 which receives pulses from a conventional digital tachometer 90 A particular tachometer suitable for use in the present invention is available from the Avtron Corporation as a model K 827 This tachometer generator is an optical device employing two rotating discs with slots which cause 1200 pulses per motor revolution to be generated by each of the discs The output signal from each of the discs is essentially a square wave with 1200 counts per tachometer shaft revolution.

These pulses from the two discs are displaced by a 90 degree phase relationship so that motor direction can be detected by detecting the displacement of the phases of the pulses provided from the tachometer on conductors 92 to the tach pulse counter 88.

The manner of detection will be 65 subsequently described in connection with the description of the tach pulse counter logic 88.

The aforementioned rectifier 16 of Fig 1, as shown in Fig 3 is comprised of a block 70 designated by thyristors (SCR's) 94 and forward (fwd) and reverse (rev) pulse amplifiers 96 and 98 respectively SCR select or address and drive direction select signals are provided to the amplifiers 96 and 75 98 via a plurality of conductors 100 from the SCR select and drive direction 84 During the operation of the system, address information loaded into the SCR select and drive direction from the microprocessor 80 causes the proper one of the forward or reverse amplifiers 96 and 98 to be selected to apply a firing pulse to the thyristors 94 when the firing logic generates the firing pulse on conductor 82 The output firing 85 pulses from the forward and reverse pulseamplifiers 96 and 98 are provided to the SCR's 94 via conductors 102 and 104 respectively The power to drive the SCR's and thus the DC motor 12 is provided via a 90 3-phase 60 hertz power line 106 to the SCR's 94 When the SCR's are fired, pulses are provided via conductors 108 to apply current to the DC motor 12 to drive the m'qtor 95 An overall understanding of the operation of the present invention can best be appreciated by a detailed description of each of those logic blocks previously described in the regulator and rectifier 100 control 14 of Fig 3 The first of these blocks to be described is the processor system interface as depicted by Fig 4 As shown in the left hand portion of Fig 4, all of the input and output signal lines to the 105 processor system interface shown to the left of the dashed lines collectively comprise the conductors 70 as previously described in connection with Fig 3 All information transferred from the processor 10 into the 110 system interface 64 comes from the output channel 56 as previously described in connection with Fig 2 Basically, the processor 10 transfers two types of commands or instructions to the system 115 interface These instructions will direct the system interface to either write certain data from the processor into specified registers in the system, such as the firing logic and SCR direction logic, or to read information 120 from various ones of the addressed input devices shown in the right hand portion of Fig 4.

Instruction data is provided to the system interface from the output channel 56 of the 125 processor via conductors 110, 112, 114, and 116 The signals on conductors 112, 110 and 114 are representative of instruction register bits from the processor 10 When the 1,598,919 processor issues a read command to the system interface, instruction register bits IRI through IR 3 on conductors 112 are decoded in a BCD to decimal converter serving as a decoder to generate a read pulse designated READ from an output terminal 6 of 118 The read pulse is generated whenever the instruction register bit IR 4 in conductor 114 is a binary zero and converted to a binary 1 through an inverter 120 to enable a NO Rgate 122 when a binary I read instruction register (IR) signal is issued by the processor When gate 122 is enabled its output applies a binary 0 clock pulse to a D input terminal of decoder 118, thus generating a READ pulse as shown on conductor 124 The read pulse is applied to two logic elements in the interface, first to a D input terminal of a second BCD decimal converter serving as a decoder 126 and to an enable (EN) input terminal of an eight bit multiplexer 128.

The decoders 126 and multiplexer 128 receive on conductor 110 the instruction register bits IR 5 through IR 7 When these bits are decoded by a decoder 126 as a read device zero command, the decoder generates an RDVO signal at its zero output terminal on a conductor 130 as shown in Fig 4 The RDVO signal is provided to the firing logic 72, the purpose of which will subsequently be described Further, whenever a READ command is issued by the processor, the instruction register bits IR 5 through IR 7, applied to an SEL input of the multiplexer 128, are decoded to route the data from one of the input devices on the right hand portion of Fig 4 to the data processor via a common time-shared bus 132 carrying input information designated IDO-ID 7 to the input channel 54 of the processor 10 (see Fig 2).

Whenever the processor issues a write command, the instruction is decoded in decoder 118 in the manner as previously described for the READ pulse to thus generate a write pulse at an output terminal 7 on a conductor 134 The write pulse on conductor 134 is applied to decoder 136 and logic driver 138 The decoder 136 also receives the instruction register bits IR 5 through IR 7 on conductors 110 to thus decode those bits to generate one of two output signals (WDVI or WDV 3) in accordance with the binary bit configuration These latter two signals, carrying the designations WDVI, WDV 3 for write device, are provided to the firing logic and to the SCR select and drive direction logic, the purpose of which will subsequently be described The write pulse applied to a C or clock input terminal of driver 138 allows data on a plurality of conductors 140 to be clocked from the processor output channel 56 to the firing logic and the SCR Select and Drive direction logic as signals WDBO-WDB 7.

Reference is now made to the input device blocks 18, 60, 80 and 88 in the right hand portion of Fig 4 It will be noted that 70 each of those devices is designated as having a unique input device number, such as input device 1 for the system clock 60.

These device numbers correspond to the address of that particular device as 75 presented to the system interface by the processor when it is desired to read information through the multiplexer 128 into the processor from any one of the devices For example, if the data processor 80 issues a read command to generate a read pulse on conductor 124, with an address on conductors 110 specifying the address for device 1, the system clock input data bits IDIBO through IDIB 7 will be channelled 85 through the multiplexer 128 onto the input data bus 132 and transferred into the data processor memory All input data transfer to the processor from the input devices are handled in the manner as just described for 90 the system clock 60, with the exception that the specific address provided to the 8 bit multiplexer 128 will channel the information into the processor from the addressed device 95 Reference is now made to Figs 5 and 6, wherein Fig 5 is a detailed block diagram of device 1, System clock 60, and Fig 6 is a timing diagram helpful in understanding the operation of the system clock The 3-phase 100 system power-line voltage is applied to three conventional squaring amplifiers 142, generating corresponding square wave output signals designated 01, 02, and 03 on conductors 144, 145 and 146 respectively 105 The three signals, 01 through 03, are applied to the corresponding inputs of a D Terminal of a conventional D TYPE FlipFlop of three similar phase zero crossing logic or edge detectors 148, 150 and 152 110 Since each of the edge detectors 148 through 152 are similar, only edge detector 148 is shown in detail in dashed lines in Fig.

5.

Each of the edge detectors function in the 115 following manner, as will be described for edge detector 148 When the 01 signal on conductor 144 goes positive, the D input terminal of a FA 01 Flip-Flop is enabled to achieve a set state upon the application of 120 the basic clock signal from the processor to a CLK input terminal of that flip-flop.

When the basic clock signal goes positive, the FA 01 Flip-Flop is set causing its Q output terminal to go to a binary 1 state, 125 generating an IDIBO signal on conductor 154 The IDIBO signal is applied as one input to a negative exclusive OR gate 156 and to a D Terminal of a second flip-flop designated FB 01 Upon the occurrence of 130 1,598,919 the next basic clock signal, the FB 01, FlipFlop will achieve a set state causing its Q output Terminal to go to a binary 1, thus causing the exclusive O Rgate 156 to generate an output pulse 01 ZROX on a conductor 158, as shown in Fig 5 The FA 01 and FBOI Flip-Flops form essentially a two-bit shift register whose outputs are gated to the gate 156 The FA O I input synchronizes the square wave from the 01 input to the system clock Thus, it can be seen that the output W 1 ZROX of the exclusive O Rgate 156 will produce one pulse at the basic clock pulse width each time the input sine wave goes through zero crossing at approximately every 2 7 millisecond period The 01 ZROX signal is connected to the input of an O Rgate 160 in conjunction with signals 02 ZROX and 03 ZROX from their corresponding edge detectors 150 and 152 on conductors 162 and 164 respectively.

Each of the signals 01 ZROX through 03 ZROX correspond to phases A, B and C of the input line voltage.

The output of O Rgate 160 is applied to a K input Terminal of a ZROX JK Flip-Flop 166 Flip-Flop 166 also receives at a CLK input terminal, the basic clock signal to trigger that flip-flop to cause it to set or reset in accordance with the state of the input signal a pplied to its K terminal from O Rgate The ZROX Flip-Flop generates a ZROX, or zero crossing signal at its Q output terminal which applied to the tach pulse counter and logic and two two counters, 168 and 170 By referring to the timing diagram of Fig 6, it can be seen that the ZROX flip-flop 166 produces the ZROX signal having a pulse 1 basic clock width wide for each phase voltage crossing of the input voltage, or 6 pulses for 360 degrees of power-line voltage cycle.

Referring now to Figs 5 and 6, it can be seen that the three signals, IDIBO through IDIB 2 (combined to form conductors 172) can be utilized by the data processor to define any 60 degree interval within a 360 degree phase cycle of the input line voltage.

This is illustrated in Fig 6 by referring to the 03 (I Dl B 2) square wave showing the various degrees of the input sine wave and the various zero crossings at the 60 degree intervals As can be seen by the inter relationships between the IDIBO through IDIB 2 signals, it is a relatively easy matter to decode those signals to define which interval of six intervals in a 360 degree cycle is present at any given time For example, assuming that the first interval is from zero to 60 degrees, when IDIBO is a binary 1, IDI Bl is a binary zero, and IDIB 2 is a binary I, and by decoding those three binary bits it can be designated as the first interval of the 360 degree cycle A similar decoding can be performed for the 60 to 120 degree intervals, the 120 to 180 degree intervals etc.

Referring now, again to Fig 5, there is shown the two previously mentioned counters 168 and 170 in conjunction with a 70 divide by 45 Counter 174 The 4 167 megahertz basic clock is applied to the input of the divide by 45 Counter 174, which divides the basic clock pulses down to produce an 11 micro second pulse duration 75 signal on a conductor 176 As shown in Fig.

5, the 11 micro second pulse on conductor 176 is applied to an andgate 178 and also to the firing logic on a conductor 180 Further, as indicated on conductor 180, the 11 micro 80 second pulse is approximately equal to one quarter of an electrical degree of the power line voltage applied to the squaring amplifiers 142 The 11 micro second pulses are applied, via andgate 178, to a divide by 8 85 counter 168 to produce an 88 micro second time base, the pulses each of which correspond to approximately 2 electrical degrees of the power line voltage The 88 micro second pulse is applied via conductor 90 182 to the firing logic, to a NO Rgate 184, and to counter 170 Counter 170 is a divide by 32 counter and further divides the 88 micro second pulses by 32 So long as counter 170 is not at a count of 31, 95 NO Rgate 184 applies a CT 31 stop clock binary I signal on conductor 186 as a second input to andgate 178 to allow the 11 micro second pulses to pass through that gate to counter 168 When counter 170 reaches a 100 count of 31, in conjunction with a binary 1 ( 88 micro second) pulse, NO Rgate 184 is enabled to apply a binary zero inhibit signal to gate 178, thus inhibiting the counters 168 and 170 from counting beyond 31 The 105 counter comprised of counters 168 and 170, will remain at a count of 31 until the next zero crossing or ZROX signal is generated from flip-flop 166 to reset the counters to zero as shown by the timing relationships in 110 Fig 6 Thus, it can be seen that the counter will count from zero to 31 between each zero crossing of the input voltage It will be noted, as stated in Fig 5, that the output signals IDIB 7 through IDIB 3 from counter 115 on conductors 188, define the time within the 60 degree interval as defined by the signal IDIBO through IDIB 2 The IDIB 3 through IDIB 7 signals are combined with the IDIBO through IDIB 2 signals to 120 form conductors 190 for application to the processor system interface 8 bit multiplexer 128 as shown in Fig 4.

It can now be seen that when the processor 10 reads the system clock that it 125 can determine the 60 degree interval of a 360 degree cycle of the input wave by looking at bits IDIBO through IDIB 2 while simultaneously determining the number of 2 degree increments ( 88 micro second pulses) 130 9 1,598,919 9 of the power line phase voltage which have passed since the last zero crossing (ZROX).

Reference is now made to Figs 7 and 8, wherein Fig 7 is a detailed block diagram of the tach pulse counter and logic, and Fig 8 is a timing diagram, helpful in understanding the operation of that logic.

As previously described in connection with Fig 3, the tachometer used in the present embodiment generates two square wave output signals with each output signal generating 1200 counts per tachometer shaft revolution These two signals are applied on conductor 92, as shown in Fig 7, as two input signals TACH Input 1 to an operational amplifier 192 and a TACH Input 2 signal to a D Input terminal of a Tach Rev Flip-Flop 194 Referring to Fig 8, the timing relationships showing the 90 degree phase displacement between the TACH Input 1 and TACH Input 2 signals is shown The TACH Input 1 signal is applied, via amplifier 192, to a D Input Terminal of type D edge-triggered TACH Flip-Flop F/Fl, also receiving at its CLK terminal, the basic clock signal from the processor As shown in Fig 8, TACH Flip-Flop F/F 1 merely toggles from the set to reset state in accordance with the state of the TACH Input 1 signal each time the basic clock signal from the processor triggers that FlipFlop The TACH FIFI has its Q output terminal connected to the D Input Terminal of a second flip-flop designated tach F/F 2 which also receives the basic clock at a CLK input terminal These two Flip-Flops essentially constitute a two bit shift register which functions in a manner similar to that previously described for the edge detector flip-flops of Fig 5 in the system clock The output of the TACH Flip-Flops F/F 1 and F/F 2 are applied via conductors 196 and 198 to a negative exclusive O Rgate 200 The O Rgate effectively differentiates the TACH Input 1 pulse, applied via conductor 196 and 198 to produce one pulse at a clock width of the basic clock for each transition of the TACH I Input signal Since the TACH Input 1 signal produces 1200 pulses per revolution of a tachometer shaft, the output of the exclusive O Rgate 200 will produce 2400 pulses per revolution of the tachometer shaft generating a tach input X 2 signal as shown on conductor 202 and illustrated in Fig 8.

The TACH Input X 2 signal, on conductor 202, is applied to a CLK input terminal of tach pulse counter 204 to cause the counter to accumulate the tach pulses read from the tachometer The tach input X 2 signal is also applied to a preset LSB input terminal of counter 204, the purpose of which will be subsequently described It will be noted that the ZROX signal from the system clock is also applied to a preset input terminal of Counter 204 and also to a CLK input terminal of a tach pulse latch 206 It will be recalled from the previous description of the system clock, that whenever one of the input phase voltages 70 passes through zero to neutral crossing that a ZROX signal is generated Thus, it can be seen that the tach counter 204 is reset to a binary zero state whenever a zero crossing pulse occurs As such, it is evident that the 75 tach pulse counter 204 accumulates counts representative of motor revolutions per each 60 degree interval of 60 cycle input.

As shown in Fig 8, the tach pulse counter 204 is always reset to a zero state upon the 80 occurrence of the ZROX signal It is also significant to note, as illustrated in Figs 7 and 8 that the contents of the tach pulse counter 204 are transferred to the tach pulse latch 206 upon the occurrence of the ZROX 85 signal Though not illustrated in Figs 6 and 7, it is to be understood that the contents of the tach pulse counter are transferred into the Tach Pulse Latch on the leading edge of the ZROX signal and then 90 the tach pulse counter is reset on the trailing edge of that signal.

Reference is now made back to the preset LSB input terminal of counter 204 The purpose of applying the tach input X 2 95 signal to this latter terminal, is to preset the least significant bit of the tach pulse counter to a binary 1 in the event that a tach pulse occurs at a time of the ZROX signal or zero crossing Should there be a simultaneous 100 occurrence of the ZROX signal, and a tach input X 2 signal, the presetting of the least significant bit assures that any count that occurs during the zero crossing is not ignored, but is instead recorded in the 105 tachometer pulse counter Once the contents of the tach pulse counter are loaded into the tach pulse latch 206, that information in the form of signals ID 3 BO through ID 3 B 7 is available on conductors 110 22 for the processor to read the motor revolutions per 60 degrees when the processor addresses Device 3.

Also shown in Figs 7 and 8 is logic for detecting the direction of motor rotation 115 The direction of motor rotation is detected by a Tach REV Flip-Flop 194 receiving the Tach input 2 signal at its D input terminal.

The operation of Flip-Flop 194, is shown in Fig 8, which illustrates the operation of that 120 flip-flop when the motor is running in both the forward and reverse directions It will be noted, that when the motor is running in the forward direction, the Tach Input 1 signal always preceeds the Tach Input 2 signal by 125 degrees As shown in Fig 8, when the motor is running in the forward direction, the Tach REV Flip-Flop 194 will never achieve the set state due to the fact that the Tach 1 Input signal which triggers the Flip 130.

1,598,919 1,598,919 10 Flop 194 via conductor 208, always goes set, prior to the tach input 2 signal ever achieving a binary I state Thus, the edge triggered Flip-Flop 194 will never set In the reverse direction, however, referring to the right-hand side of Fig 8, it will be noted that when the Tach input 2 signal preceeds the Tach Input 1 signal by 90 degrees, the Tach Rev Flip-Flop 194 will achieve a set state when the Tach Flip-Flop I achieves a set state When the REV Flip-Flop achieves a set state its Q output terminal generates a binary 1 IDOB 4 signal on one of the conductors 22 to the processor system interface When the Tach Input 2 signal preceeds the Tach Input 1 signal, the binary I signal of IDOB 4 notifies the data processor that the motor is running in a reverse direction.

Reference is now made to the firing logic of Fig 9, which illustrates that logic in block diagram detail Fig 10 should also be referenced in conjunction Fig 9, which is a timing diagram showing the timing interrelationships between the various signals within the firing logic 72 As previously described, the primary purpose of the firing logic is to provide a firing pulse on conductor 82 to the SCR select and drive direction logic 84, as shown in Fig 3.

Additionally, the firing logic generates a convert pulse to the A to D converter on conductor 78 It is through the operation of the firing logic, that the processor is signalled from an interrupt signal on a conductor 210 of Fig 9 to begin the process of calculating the firing angle for generation of the firing pulse to fire an SCR at the proper time.

In describing the operation of the firing logic, reference is also made at this time, to Fig 4 It will be recalled from the previous description that the processor must generate a write command and a device address to send a command to that device.

For the firing logic, the decoder 136 generates a write device 1 (WDVI) signal as shown in Figs 4 and 10 As shown in Fig 10, when the WDVI signal goes from a binary I to a binary zero state, the WDV 1 signal on conductor 212 causes a Load Counter Flip-Flop 214 to receive the binary zero signal at a CLR Input Terminal causing that flip-flop to reset Simultaneously, the WDVI signal is inverted through an inverter 216 to a binary 1, applying an enable signal to an EN input terminal of a write data latch 218, thus loading the data (WDBO-WDB 7) on conductors 220 from the drivers 138 of Fig 4.

Referring now to Figs 9 and 10, it will be noted that the occurrence of the first 88 micro second pulse appearing on conductor 182 after the WDVI signal clocks the load counter Flip-Flop 214, causing that counter to now achieve a set state generating a binary 1 signal at its Q output terminal on a conductor 222 The binary I signal on conductor 222 is applied to an inverter input load terminal of a down 70 counter 224 As shown in Fig 10, the load counter Flip-Flop, when in the set state, and in conjunction with the 88 micro second pulse, loads the down counter 224 with either a TIMTGO or 20 second delay signal 75 The TIMTGO signal is a binary configuration of bits loaded into the down counter from the data processor, representative of, or proportional to the firing angle of the SCR's If a TIMTGO 80 signal is not loaded into the down counter, then a data word representative of a 20 degree delay is loaded A more detailed description of the purpose of the TIMTGO and 20 degree delay signals or values will 85 subsequently be described.

Reference is now made back to Fig 9 to an Andgate 226 Andgate 226 is enabled by a binary 1 output from a Q output terminal of a first detector flip-flop 228 With flip 90 flop 228 in the reset state, the first 11 micro second pulse on conductor 180, applied to gate 226, causes the contents of counter 224 to be clocked or counted via conductor 230 and an inverter 232 applying the 11 micro 95 second pulse to a CLK terminal of the down counter The timing for the clocking of the down counter 224 is shown on the 11 micro second line and on the down counter line of Fig 10 The down counter will continue to 100 count down to a specified value until a 14 count decoder 234 recognizes a count of 14 via a plurality of conductors 236 from the counter At a count of 14, and with an 11 micro second pulse from gate 226, decoder 105 234 generates a pulse to fire a convert oneshot multivibrator 238 One shot 238 generates an 8 micro second convert pulse on conductor 78 which is applied to the analog digital converter 80 of Fig 3 at the 110 time illustrated in Fig 10 This pulse starts the analog digital converter to perform an A to D conversion of motor current on conductors 24 for subsequent use by the processor 115 The down counter will continue to count down to a specified value of zero as shown in Fig 10 When the down counter gets to the count of zero, as detected by a zero count decode 240 via conductors 242 from 120 the down counter, the zero count decode 240 generates a pulse on a conductor 244 which is applied to a D Terminal of the detector Flip-Flop 1, 228 Upon the appearance of the next basic clock signal 125 applied to the CLK Terminal of flip-flop 228, the flip-flop will set causing a binary zero signal to now be applied to Andgate 226 to inhibit the 11 micro second clock pulses being fed to the down counter 224 This is 130 lo 1,598,919 1,598,919 shown by the note, "Stop Down Counter" in Fig 10 When the detector Flip-Flop 228 goes to a set state, its O output terminal goes a Binary 1 to simultaneously enable one input to an Andgate 246 and apply a binary 1 set signal to a D terminal of a second detector Flip-Flop 248 It will be noted, as shown in Fig 10, that Andgate 246 is enabled at the instant Flip-Flop 228 goes into the set state, due to the fact that flipflop is reset at that time The output of Andgate 246 now applies a trigger signal to a J input terminal of an interrupt flip-flop 250 effecting the generation of the interrupt signal to the data processor The interrupt signal causes the data processor to go into an interrupt subroutine to start calculations of the firing angle for subsequent firing of the SCR's.

It will be noted, that the first basic clock signal, following the setting of flip-flop 228, will set flip-flop 248, causing its Q output terminal to go to a binary zero thus disabling Andgate 246 This causes the generation of a short pulse to be applied to the INT Flip-Flop 250 as indicated by the overlap between the DET FFI and DET FF 2 signals in Fig 10 It is also to be noted, that simultaneously with the setting of the interrupt Flip-Flop 250, that the output signal from Andgate 246 is applied to a firing pulse (FP) one-shot multi vibrator 252 to apply a 23 micro second firing pulse on conductor 82 to the SCR select and drive direction logic 84 The generation of the firing pulse is shown in Fig 10, at which time an SCR pair is fired simultaneously with the generation of the interrupt signal.

The firing logic will remain in the present or preset state until receipt of another WDV 1 signal on conductor 212 causes a loading of new data into the down counter 224 in the manner just described.

When the down counter is loaded with new data, the zero count decode now applies a reset signal on conductor 244 to Flip-Flop 228, allowing that Flip-Flop to now achieve a reset state and simultaneously reset Fli -Flop 248 When Flip-Flop 228 resets its 5 output signal on conductor 254 goes to a binary 1, now enabling Andgate 226 to allow counter 224 to count after it is loaded As shown in Fig.

10, at some time subsequent to the firing of the SCR pair, the Data Processor must send a RDVO Read Device zero signal on Conductor 130 to a clear CLR Input terminal of the interrupt Flip-Flop 250 to reset that Flip-Flop in preparation to sending another interrupt to the Processor immediately upon the generation of a firing pulse to the SCR's.

Reference is now made to Fig 's l IA and JIB with Fig IIA on top of Fig Ii B to form one Figure depicting the detailed logic of the select and drive direction 84 and, an electrical schematic of the SCR forward and reverse drive bridges The analog to digital converter 80 is also shown receiving analog motor current via a conductor 256 70 from a conventional 3-Phase bridge summing rectifier circuit 258 In Fig l IA, the 3-Phase 60 Hertz line voltage is applied as O A, OB and OC on conductors 106 to respectively associated anodes and 75 cathodes of the forward and reverse SCR bridges, each comprised of six SCR's designated Pl through P 3 and NI through N 3 as illustrated in Fig 1 l A The operation of the forward and reverse SCR bridges will 80 not be described in detail here as they are conventional bridge firing networks well known in the art for controlling a DC motor One such conventional bridge is manufactured and sold by General Electric 85 Company as a Siltrol 1, known as 1 C 3610 integrated static conversion and control equipment for adjustable speed drives.

Three current transformers, designated 260, 262 and 264 are each respectively 90 associated with one of the phase line voltages O A through O C These transformers provide alternating current inputs into the 3-Phase bridge summing rectifier 258 via the respective leads, wherein the output of the 95 rectifier to the converter 80 is the average of the three input currents As previously mentioned, the analog to digital converter is conventional in design, one such converter being manufactured as a model 100 ADC-8 QU by Analog Devices Inc This particular converter is a complete high speed successive approximation 8 bit converter which converts the input analog signal on conductor 256 to a digital value 105 upon the reception of an input command designated the convert pulse on conductor 78 In this particular converter, 7 bits of the 8 bit output denote current magnitude and the 8th bit denotes the polarity of the 110 current It will be recalled from the previous discussion of the firing logic of Fig 9, that when the down counter reaches a count of 14, that the firing logic generates an 8 micro second convert pulse to the A to D 115 converter on Conductor 78 It is this convert pulse which starts the A to D converter 80 to convert the motor analog current on 256 to a digital value for subsequent transfer to the data processor 120 via the processor interface as data bits ID 5 BO-ID 5 B 7 on conductor 24.

As shown in Fig 4, the transfer of the motor current on conductor 24 is accomplished when the A/D converter 80 125(Device 5) is addressed via the 8-Bit multiplexer 128 to transfer data to the processor over bus 132 The addressing of the A/D converter is accomplished by the data processor loading a proper address in 130 a 11 12 1,9,1 12 bits IR 5 through IR 7 and applying those bits to the SEL terminal of the multiplexer 128, along with the READ pulse to the Enable input terminal of the multiplexer The proper binary bit configuration of bits IR 5 through IR 7 will channel the motor current reading from the A/D converter 80 through the multiplexer on bus 132 for transfer to the data processor.

Reference is now made to Fig 11 B to the SCR select and drive direction logic 84 The primary purpose of the Select and Drive direction logic is to receive a data word or address from the data processor via conductors 266 on the right data lines 266 (WDBO-WDB 7) from the driver 138 of Fig 4 This data word is a binary bit configuration loaded into an SCR steering or selection register 268 by a WDV 3 signal on a conductor 270 from the decoder 136 of Fig 4 When the processor sends a write command addressing write Device 3, the WDV 3 signal on Conductor 270 goes to binary zero and is inverted to a binary I through an inverter 272 to thus apply an enable load signal to register 268 to load an SCR pair address into the register Each of the stages or bits of the register 268, except for one, has its output connected to a corresponding one of a plurality of AN Dgates 274, 276, 278 and 280 It will be noted that the output signal from each of the AN Dgates is designated with a signal corresponding to one of the SCR's in each of the forward and reverse bridges For example, an output Pl from AN Dgate 274 corresponds to the Pl SCR in each of the forward or reverse SCR bridges Whenever it is desired to fire a specific pair of SCR's in one of the bridges, a binary word or address is placed in register 268 to enable the particular AN Dgates ( 274-280) to allow them to provide their appropriate control signals to corresponding forward reverse (FWD/REV) drive switching amplifier circuits.

These FWD/REV drive circuits are of conventional design and are designated 282, 284, 286 and 288 Each circuit corresponds to a like numbered SCR in each of the forward and reverse drive bridges For example, the Pl FWD/REV drive 282 is connected via conductors 290 and 292 to the respective gate electrodes of the Pl SCR in each bridge Similar connections are made to the P 2 gate electrodes from drive 284 and to the N 2 and N 3 gate electrodes from drives 286 and 288 It will be noted in Fig I l B, that only four of the AN Dgates generating the Pl through N 3 signals and the drive circuits associated with each of the Pl through N 3 SCR's are shown The AN Dgate and drive electronics for SCR's P 3 and N 3 have been shown coming out in dashed lines from the select register 268 for simplicity purposes.

It is significant to note that one bit of the firing register 268 generates a FWD/REV signal on a conductor 294 to each of the FWD/REV drive circuits 282 through 288.

The drive circuits 282 to 288 are conventional driver or switching circuits of well known design capable of receiving logical inputs to switch their output signals selectively between one of the two lines coming out of each of the drive circuits For example, in the operation of the drive circuit 282, to activate or fire the Pl SCR of the forward bridge, a binary 1 signal is applied from register 268 as one input to Gate 274, and upon occurrence of the firing pulse on conductor 82 from the firing logic, gate 274 is enabled passing the pulse through drive Pl to the forward SCR P 1 On the other hand, if the FWD/REV bit is a binary 0, drive 282 will be activated to transfer the firing pulse on conductor 292 to SCR Pl of the reverse SCR's In the present embodiment and in the operation of the SCR's of the rectifier 94, it is desirable to always fire SCR's in pairs, such as Pl and N 2 in the Forward or Reverse bridges The word loaded into Register 268 will always have two binary bits corresponding to the SCR's to be fired For example, the binary I to fire SCR Pl would activate Gate 274 and a binary 1 to fire SCR N 2 would activate gate 280, the other gates remaining disabled or inactivated.

In order to more fully understand and appreciate the overall operation of the system of the present invention, it is first considered advantageous to describe how the firing angle for firing the SCR pairs is derived in the system.

Reference is now made to Fig 12 which depicts the interrelationship between the 3Phase power line input voltages, O A, O B and 0 C and a representation of the manner in which the firing angle, designated FINVAL, for the SCR pairs is developed to generate a variable value representative of a signal TIMTGO standing for Time To Go, which is a calculated value proportional to the firing angle It is well known in the art that the firing angle for controlling SCR rectifiers of the type utilized in the present invention, is measured from the phase-tophase crossing to the point of firing of the SCR pairs In the present invention, the value of the firing angle, FINVAL, to develop a motor terminal voltage equal to VT is obtained by a table look-up in memory having the representation as shown by Table 1 That which is stored in memory, as the firing angle, is shown in the righthand column as FINVAL counts.

The FINVAL table is computed from the relation FINVAL= 245 8 INVERSE COS OF 1,598,919 3 VT over 7 r VLN where 245 8 equals the number of eleven micro second pulses applied to the down counter to count that counter down per electrical radian VLN is defined as the voltage from line to neutral of the input power line voltage.

TABLE 1

VT Vs FINVAL COUNTS Motor Term Voltage Finval Counts -272 715 -256 671 -240 640 -224 615 -208 592 -192 572 -176 553 -160 530 -144 519 -128 503 -112 487 -960 472 -800 457 -040 443 -480 428 -320 414 -160 400 0 386 372 320 358 480 343 329 800 314 960 300 112 284 128 269 144 253 236 176 218 192 199 203 179 224 157 240 132 256 101 272 57 Referring now back to Fig 12, that Figure shows the derivation on the TIMTGO equation, TIMTGO being a value proportional to firing angle which is loaded into the down counter 224 of Fig 9 to fire the proper SCR pair at the correct time By definition, TIMTGO=FINVAL-(NEWTIM+ 1)x 8-Tn.

In its most simplified form, the method or sequence for loading the down counter with TIMTGO is explained by the following steps:

1 The processor computes the value of FINVAL, the firing angle, which is the current regulator output.

2 The processor next reads the system clock, (device 1) as previously described in connection with Figs 4 and 5 to establish or define the 600 interval in the input power cycle, and to further define a time within that interval, and then it calculates the value of NEWTIM and TIMTGO.

3 Next the processor reads the system clock repeatedly until the value of the clock equals NEWTIM and then proceeds to load the down counter with TIMTGO.

NEWTIM is the value calculated by the processor which is utilized by the program to specify at which time TIMTGO is to be loaded into the down counter so that the down counter will begin counting at the proper time Loading at the time specified by NEWTIM ensures that the program is synchronized with the firing of the SCR rairs.

The previously mentioned CRD 8 processor utilizes a 300 nano second memory which allows step 2 to be performed in approximately 120 micro seconds This 120 micro second period is slightly less than the time duration of two of the 88 micro second pulses as developed by the 360 system clock of Fig 5 Therefore, if TCLOCK is the time represented by bits ID 1 83 through IDIB 7 of the system clock at the beginning of the previously mentioned Step 2, and if NEWTIM is given by NEWTIM=TCLOCK+ 2 (processor calculation time for NEWTIM and TIMTGO) Step 2 will always be completed in time to load the down counter 224 before the system clock transition at NEWTIM+ 1 The + 1, which is appended to NEWTIM in Fig.

12, is shown to indicate the 88 micro second clock period required to load the down counter from the processor It will be recalled from the description of the system clock of Fig 5 that the counter 170 counts from 0 to 31 from zero crossing to zero crossing (ZROX) It is possible for the counter to stay at a count of 31 for an interval equal to 32 count, making the last count of counter 170 longer than the previous counts In this case, if NEWTIM is equal to or greater than 31, one 11 micro second or fast pulse must be added to Tp since the 31st interval of the system clock is longer Further, if NEWTIM is greater than 31, the system must be corrected for the reset of the system clock at the next zero crossing (ZROX).

Still referring to Fig 12, 13 FINVAL=Tp+(NEWTIM+ 1)+TIMTGO.

In the present embodiment, FINVAL, T, and TIMTGO are expressed in fast counts or 11 micro second pulses and NEWTIM+ I 120 1,598,919 14 1,598,9-914 is expressed if slow counts or 88 microsecond pulses Thus, to convert to equivalent values, FINVAL=Tp+ 8 (NEWTIM+ I)+TIMTGO.

The multiplication factor of 8 is to equalize NEWTIM+ 1 with Tp and TIMTGO, since it takes 8 fast counts ( 11 micro second pulses) to 1 slow count ( 88 micro second pulses).

Continuing to develop the TIMTGO equation, and substituting the value of TCLOCK for NEWTIM in the equation, gives TIMTGO=FINVAL-Tp-8 (TCLOCK+ 3).

It will be recalled, that it takes approximately two slow clock pulses to read the 3600 system clock and to calculate NEWTIM and TIMTGO Therefore, this time must be compensated for in NEWTIM by adding plus 2 Thus, if TCLOCK is the time read by the processor, adding the 2 slow clock pulses of dead time to compensate for the calculation time, then NEWTIM+ l=TCLOCK+ 3 as shown in the above equation for TIMTGO.

To equalize TIMTGO since T, is in slow clock pulses TIMTGO=FINVAL-Tp-8 x TCLOCK-24.

Note: see 8 (TCLOCK+ 3) above, 3 slow pulses equal 24 fast pulses.

Referring still to Fig 12, T is defined as the angle from the phase to phase crossover that defines zero firing angle for the SCR to be fired, to the most recent phase to neutral cross over Another way of stating this is to look for the most recent phase to neutral crossing in the zero degree to 360 degree cycle and subtract from that angle the reference from the cell pair to be fired, this will give Tp For example, if the most recent phase to zero crossing is O C going negative at 60 as shown in Fig 12, and if the SCR pairs PI/N 2 are being fired, then the reference angle is 30 ( 60 -30 =T) Where the 300 is the angle between O A to 'C crossing and the O C to neutral crossing If we let T + 24 equal TABTP, thenTIMTGO=FINVAL-8 x TCLOCK-TABTP-CORR, where CORR is the correction for the previously mentioned long thirty first pulse of the system clock.

In the operation of the program, the value of TABTP is obtained from a lookup table as illustrated by Table 2 Referring to Table 2, it will be noticed that the TABTP Table is comprised of eleven entries in fast counts representative of degrees which serve as an offset in the TIMTGO equation to compensate for the actual time interval at the time in which the system clock is read by the computer.

Referring now to Fig 6 and Table 2, it will be noted that the system clock bits I Dl BO through IDI B 2, which are the three most significant bits, can be decoded into 600 intervals having numbers 1 through 6 desigr ated KOCT as shown in Fig 6 and in the left column of Table 2 Referx'ing now to the second column from the left of Table 2, it will be noticed that a table designated TABIPH, representative of the Phase 0 crossing numbers, are stored in sequential locations, in memory designated PHA 1 through PHA 6, each corresponding to one of their respective phases as also indicated in Table 2.

At the time of reading of the system clock, the computer will utilize the KOCT number to address the corresponding one of the PHA locations in TABIPH as indicated in Table 2 Thus, for example, it can be seen that KOCT 5 of Fig 6 and in the left hand column of Table 2, is equal to Phase 0 crossing PHAI or O A, KOCT 4 is equal to Phase 0 Crossing PHA 2 or O C etc.

The processor also includes an SCR pair to be fired counter designated in a column PH of Table 2 The PH counter is incremented or updated a specified amount during the program each time an SCR pair is fired Thus, firing takes place in a specified sequence To obtain the proper TABTP value for the calculation of TIMTGO, the address developed from the difference between the PHA and PH (PHA-PH) values is utilized to develop an address to the TABTP table It will also be noted that the SCR pair counter PH always specifies a particular pair of SCR's to be fired For example, when the SCR pair counter PH is at a 1, the SCR pair P 1/N 2 will be fired, whereas if the counter is at 6, pair P 3/N 2 will be fired, etc.

It will further be noted, that there are 6 address entries of each of the TABTP locations in memory, each of those 6 addresses being representative of one of the six zero crossings in a complete cycle of the input voltage It will also be noted that each of the SCR pairs gets fired once each 600, or six firings in each 360 cycle of the input sinewave It will further be noted that the PHAO crossing number does not always correspond to the PH counter value This is due to the fact that any given cell pair can be fired at any 600 interval during a 3600 cycle period It is this difference between the PHA numbers and the PH counter numbers which allow the derivation of the addresses to the TABTP table to extract from the table the proper count number in fast counts for insertion into the TIMTGO equation.

1,598,919 TABLE II

PHA-PH TABTP TABLE

A"' TABTPTABLE {",,,on 'l-o (' nt-o AIXL t I tn A K r Ii A = ADDfltb L t JI'1 s UL O 1-OA I PI/N 2 = O 4 2-0 C 2 P 1/N 3 = O 6 3 O B 3 P 2/N 3 = O -105 =-30 2 4 O A 4 P 2/N 1 = O 3 5-0 C 5 P 3/NI = O 1 6-0 B 6 P 3/N 2 = O 2 Pl/N 3 -1 3 P 2/N 3 -1 4 P 2/NI -1 -362 =-90 O P 3/NI -I 6 P 3/N 2 -1 1 P 1/N 2 3 P 2/N 3 -2 4 P 2/NI -2 P 3/NI -2 -619 =-180 6 P 3/N 2 -2 I P 1/N 2 4 2 PI/N 3 4 4 P 2/NI -3 P 3/N 1 -3 6 P 3/N 2 -3 1 P 1/N 2 3 667 =+ 180 2 PI/N 3 3 3 P 2/N 3 3 P 3/N 1 -4 6 P 3/N 2 -4 1 P 1/N 2 2 2 PI/N 3 2 410 =-+ 90 3 P 2/N 3 2 4 P 2/N 1 2 I A 4 2 O C 6 3 B 2 4-0 A 3 5 O B I 6 O C = J 1 = 1 1 = 1 = 1 153 =+ 30 Prior to preceding with a description of the program for controlling the overall operation of the regulating and control system of the present invention, reference is now made to Fig 13 which shows in simplified bar chart form, the overall system operation to develop the value TIMTGO proportional to firing angle to fire the SCR pairs in the rectifier 16 of Fig I To understand the operation of Fig 13, it is considered advantageous to make an assumption at first that some SCR pair in the rectifier has just fired As previously described, whenever an SCR pair is fired, the INT Flip-Flop 250 of Fig 9 generates an interrupt signal to the processor This interrupt causes the processor to branch to an interrupt subroutine which effectuates the reading of the analog to digital converter 80 into the computer As shown at this time, the processor loads the down counter with a count proportional to a 20 delay The present invention is capable of operating in either continuous or discontinuous current mode and the purpose of loading the 20 delay into the down counter 224 of Fig 9 is to allow the processor time to determine the mode Qf operation in which the regulator is to operate and to set gains or constants for either continuous or discontinuous mode operation in the proper manner The INTV.

v nt"r TABPH 0-0 XING DPT A SCR PAIR CTR.

DW FWD/REV SCR PAIR FITD ET' 0 1 2 3 4 r-f/i NZ PI/N 2 P 1/N 3 P 2/N 3 P 2/N 1 P 3/N 1 1,598,919 16 1,598,919 16 manner in which this is done will subsequently be described in connection with the program.

Still referring to Fig 13, it will be noted that at a count of 14 in the down counter 224, as previously described, the convert pulse is sent to the A/D converter on conductor 78 to activate the converter to begin the analog to digital conversion At the termination of the 200 delay, or when the down counter 224 reaches the predetermined count of 0, the INT FlipFlop 250 again sends a second interrupt signal to the processor Upon receipt of the second interrupt signal, the processor interrupt subroutine now performs the calculations of the firing angle FINVAL to develop the TIMTGO value As can be seen in Fig 13, the entire reading and calculation of the firing angle takes place between the firing of successive SCR's.

Since there is an SCR firing every 600 of the input sine wave cycle, it can be seen that the entire calculation for firing angle to fire the next pair of SCR's is done in a 600 interval.

The 200 delay which has been selected is the maximum value which leaves time for the regulator calculations, (i e time to calculate the firing angle), and to still generate a positive TIMTGO when the phase advance rate is maximum.

The second current which is read by the processor is utilized in the regulator response calculations The advantages in performing the calculations in this manner are:

1 That the control time lag as seen by the overall regulator is minimized, thus maximizing the performance of the regulator.

2 The second current read will always have some finite value at all practical operating levels of the regulator so that the regulator can operate during the discontinuous current mode This is due to the fact that the second current reading is taken 200 after the first current reading.

3 And, as will subsequently be described, a single down counter such as down counter 224 of Fig 9 is required since counting is never started until after the previous SCR pair is fired.

Still referring to Fig 13, once the calculations are completed the processor loads the TIMTGO value into the down counter 224 of Fig 9, at which time that counter begins to count towards 0 The program then branches immediately to a READ TACH counter subroutine RDTACH, wherein the Tach pulse counter -8 is read by the processor and the value of t teed forward counter electromotive force t I calculated for use in calculating i Zoo lijld Motor Terminal Volts (VT).

Upon completing of the RDTACH 65 subroutine, the program branches back to the interrupt subroutine, wherein, that subroutine calculates a Rate of Change of Current Set Point (SPDESI) The program now goes into a loop and waits until the 70 firing counter achieves a count of 0, as shown in the top line of Fig 13, at which time the SCR pair is fired and an interrupt is again issued to the processor and the process just described is repeated 75 Reference is now made to Fig 14, which is a high level flow chart showing the overall operation of the regulating and control system of the present invention which is somewhat in more detail then that just 80 described in connection with Fig 13.

When the system is first started up, as shown in the left hand top block of Fig 14, the program generates a dummy interrupt to the system by loading a number 16 into 85 the down counter 224 of Fig 9 Also at this time, zeros are loaded into the SCR select register 268 of Fig 11 B The down counter will now begin to count down toward 0, and when it reaches 0, the INT flip-flop 250 of 90 Fig 9 generates an interrupt signal on conductor 210 to the processor The purpose of loading all zeros into the SCR select register is to prevent any SCR pair from being fired at this time 95 The processor now enters into the interrupt subroutine upon receipt of the interrupt The program now enters a Ist reading decision block determining if this is the first or second current reading from the 100 A/D converter 80 of Fig 3 Assuming that it is the first current reading, the program now goes through a yes branch into a block wherein the first current is read from the A/D converter The program further 105 determines, in this block, whether the system is in either the continuous or discontinuous current mode by comparing the value of the first current against a constant proportional to a predetermined 110 current The program then proceeds to set the previously mentioned firing angle for a delay The program proceeds to read the system clock bits IDIB O through IDIB 7 on conductors 90 of Fig 5 and to calculate 115 the value of NEWTIM Upon the completion of the NEWTIM calculation, the program continues to calculate TIMTGO, which at this time includes the delay The program then goes into a 120 loop and continues to read the system clock until NEWTIM is equal to the 5 least significant bits of the divide by 32 counter of Fig 5, designated IDIB 3 through IDIB 7 When these two values are equal, 125 the processor now loads the TIMTGO value proportional to firing angle into the down counter and proceeds to set a flag for the second reading.

1,598,919 16 A 1,598,919 The program now proceeds to check if a new tachometer reading is available in the Tach Pulse Counter Register If a new reading is available, it is read and added to the tachometer readings already accumulated in memory (CACTI) The program now checks to see if three successive readings have been accumulated.

If not, the program takes a no branch and enters back into the main program until another interrupt is received from the processor (i e when TIMTGO equals 0) At this time, the 1st reading decision block is again entered, and upon this entry, since the, flag for second reading has been set, the program will exit through the no branch of that last decision block and enter into a block wherein the processor will read the second current from the A/D converter.

After having read the second current, the program will now perform the regulator calculations to calculate FINVAL and TIMTGO Upon the completion of these calculations, the processor will now write the SCR pair address into the SCR select register 268 of Fig l IB At this point, the processor again goes into a loop to continue to read the system clock until the values of NEWTIM and IDIB 3-I Dl B 7 are equal.

When these values are equal,, the processor is told when to load TIMTGO into the down counter, which is done at this time.

The processor then proceeds to update the SCR pair address in the previously mentioned PH counter and proceeds to set the flag for the first current reading, so that upon the next pass through the program a first reading will be taken The program now proceeds back to again read the tachometer if a reading is available and then tests to see if three successive tachometer readings have been accumulated If three readings have not been accumulated and a Speed Regulator Request Flag (SPDFLG) is not set the program will continue through the loop just described entering back through the 1st reading decision block, out the YES branch and continue to perform the current regulator calculations as just described on the second reading If, after the previously mentioned check for a new tachometer reading, 3 successive readings are available, new values for motor speed (CACT), Smoothed Motor Acceleration (TACSMD), and Counter Electromotive Force (CEMF) are computed The Speed Regulator Flag (SPDFLG) is set to zero to cause a speed regulator calculation to be made At the completion of these calculations, if the flag is set for a second current reading, indicating that a first reading has just been made, the program branches back to the main program pending an interrupt from the firing logic INT FlipFlop 250 of Fig 9 as previously described.

However, if the flag is not set for the second reading a YES branch will be taken to a block to test for the time to perform the speed regulator calculation, the SPDFLG is incremented by I and then tested for the value of 2 If the test passes, the speed regulator calculation is entered If not, the main program is re-entered as before This procedure insures that the regulator and smoothing calculations will not be performed in the same interval between SCR firings This was done to prevent overloading the computer Upon completion of the speed regulator calculations, the program now enters back into the main program pending receipt of the interrupt from the firing counter.

With the broad background of the description of the system operation in regard to Figs 13 and 14, reference is now made to Figs 15 through 24, which show in detailed flow chart form the execution of the current regulator program for controlling the regulating and control system of the present invention Reference is first made particularly to Fig 15, which is a flow chart depicting the main program of the present invention Not shown in Fig 15 is a standard initialization routine which every program normally runs through to initialize all the various registers and storage locations in memory in preparation to running a program Since this type of initialization is well known in the art, it is not shown in Fig 15, whereas the program is assumed to start at an entry point designated BEGIN When the system is first started up, starting at BEGIN The processor first reads device 3, the tach pulse counter 88, as shown in Figs 4 and 7 The bits read by the computer are ID 3 BO through ID 3 B 7 on conductors 22 These bits are read through the 8 bit multiplexer 128 of Fig 4 in response to a read address as designated by bits IR 5 through IR 7 and a READ P pulse on the enable line to the multiplexer 128.

The processor then tests in a decision block TACH COUNT= 0 to determine if the motor is turning If the tach count reading (ID 3 80-1 D 3 B 7) is not 0, it indicates that CEMF is not 0 and that the motor is rotating, thus the program will take a no branch from that decision block and continue loop back to BEGIN until CEMF OR TACH COUNT is 0 When the TACH COUNT is 0, the program exits through a Y branch into the next action block, wherein the processor reads device 0 ( 18 ' of Fig 4).

ID 4 BO is the bit read at this time by the processor to read in the on/off switch to see if the motor has been turned on.

Additionally, the processor sends a read device 0 command to the processor system interface developing the RDVO signal on 18 1,598,919 lx conductor 130 to the INT flip-flop 250, thus resetting that flip-flop The INT flip-flop 250 is now in a state to generate an interrupt signal at the proper time during the operation of the system.

The program now proceeds into a decision block ON/OFF SWITCH ON In that decision block, if the ON/OFF switch just read from device 0 is not in the on state the program takes an N branch back to the beginning of the program and continue to loop in the program until the ON/OFF switch is turned on Assuming now that the ON/OFF switch is on, the program will exit through a Y branch, entering to an action block wherein, the processor transfers a write device 1 command along with data bits WDB 0-WDB 7 to the processor system interface of Fig 4, to cause the generation of the WDV 1 signal on conductor 212 to be sent to the firing logic of Fig 9 and load the count of 16 into the write data latch and into the down counter 224 in the manner as previously described.

The purpose of loading 16 into the down counter 224 is to create a dummy interrupt to the processor so that the processor can begin to execute the main program and all subsequent subroutines which are entered from the main program.

At this point, the down counter begins counting down while the program proceeds immediately to a START entry point as shown in Fig 15 The processor now sends a read device 6 command to the processor system interface to effect the reading of the speed reference change switch designated by bit ID 6 80 on conductor 66 as shown in Fig 4 The state of bit ID 6 80 is now interrogated by the processor to determine if the speed change switch is in the ON state The speed change switch is an operator controlled switch on a console, not shown, forming part of the speed reference switches 18 (input devices 6 and 7) which is actuated by an operator when he desires to change the speed reference input to the data processor to change the speed of the motor So long as this switch is in the ON state, the program will continue to exitthrough the Y branch of the CHANGE SPEED SW ON decision block and loop in the program back to the START point.

Let it now be assumed that the change speed switch is not on, thus the program will exit through a NO branch entering into an action block wherein the processor sends commands to the processor system interface to read devices 6 and 7 via conductors 66 into the processor In this instance, the previously mentioned speed reference switches, which are representative of motor RPM's speed set point (bits ID 6 B 3 through ID 6 B 7 and ID 7 80 through ID 7 B 7) are sorted in a memory location in the processor program 62 designated CHALF which is the storage location for the speed set point.

The program now proceeds to set the sign of location CHALF in accordance with the 70 setting of the FWD/REV switch by first sending a read device 0 signal to the system interface and reading in bit IDOB 5 from device 0 If IDOB 5 specifies that the motor is to run in the forward direction CHALF is 75 not changed, however, if IDOB 5 specifies that the direction of the motor is to run in reverse, then the 2 's complement of CHALF is taken and accordingly substituted for CHALF 80 The program now proceeds to determine if the ON/OFF switch is in the OFF position If the switch is in the OFF position, the program will exit through a Y branch and go back to begin wherein the 85 operations just described will be repeated.

Assuming, however, that the ON/OFF switch is not in the off position, the program will exit from that last decision block through a NO branch returning back to the 90 START entry point as shown in Fig 15 The program will now continue to loop from the START point down through the ON/OFF SWITCH OFF decision block until an interrupt signal is received by the data 95 processor from the INT flip-flop 250 in the firing logic 9.

As previously described in connection with the firing operation of logic, it will be recalled that when the down counter 100 achieves a count of 0, the INT flip-flop 250 is set to generate the INT signal on conductor 210 to the processor It is significant to point that the interrupt signal from the firing logic can occur at any time 105 during the execution of this latter loop, (i e.

between the START entry point and the ON/OFF SWITCH OFF decision block).

When the interrupt occurs, the processor will branch from the main program of Fig 110 into a start INTPT point of Fig 16, the beginning of the interrupt program As will subsequently be seen, at the termination of the interrupt program when all calculations have been completed, the interrupt 115 program will return back to the main program of Fig 15 at the point wherein the interrupt occurred.

Let it now be assumed that the processor has generated the interrupt signal on 120 conductor 210, causing the program to enter into START INTPT point of Fig.

16 The first operation by the processor is to store the current values of the various processor registers, namely those of the 125 scratch pad memory previously described in connection with Fig 2 This is a standard procedure in all operating programs when branching from one subroutine or program to another so that those values can be 130 1,598,919 189 19 1,9,1 19 restored later when return is made back to the program from which the branch was made.

The processor then proceeds to send a read device 0 command to the processor interface of Fig 4 to again read the ON/OFF switch bit IDOBO and to simultaneously reset or clear the interrupt flip-flop sending the RDVO signal to the firing logic from the decoder 126 of Fig 4 in the manner as previously described The ON/OFF switch is now tested to see if it is in the OFF state If the switch is in the OFF state, indicating that power should be removed from the motor, the program will exit through the Y branch and the previously stored registers will now be restored back to their original values and the program will return back to Fig 15 wherein the operations will take place as previously described Assuming at this time, however, that the ON/OFF SWITCH is not in the OFF state, the program will exit through an N branch into a 1st CURRENT READING (CURFLG= 0) decision block In this latter decision block, a test is performed to see if this is the first current reading The test here is performed on a variable flag in memory designated CURFLG for current first reading flag When the CURFLG is equal to 0 it indicates that this is the first current reading, when it is a binary I it indicates that it is the second current reading.

Assuming at this time that CURFLG is equal to 0, the program will exit through a Y branch and enter into an action block wherein the processor sends a read device 5 command to the processor system interface directing the reading of the analog to digital converter 80 to read bits ID 5 BO through ID 5 B 7 through the 8 bit multiplexer into the processor on input data lines IDO through ID 7 The value specified by the ID 5 BO-ID 5 B 7 bits is stored in a location in memory designated CRNT, which is a storage location for the measured motor current The program now proceeds into decision block wherein a constant value CURTOL stored in memory is compared against the absolute value of CRNT The value of CURTOL is a value proportional to I to 2 percent of the rated motor current and is utilized to test for discontinuous current operation If CURTOL is less than CRNT, the program exits through a Y branch going into discontinuous mode, whereas, if CURTOL is greater than CRNT it will be the continuous mode and the program exits through the N branch.

Let it at first be assumed that the motor is operating in the discontinuous mode Thus, exiting through the Y branch the processor will set a mode flag MODFLG in memory equal to a 1, indicating that the system is now in discontinuous current mode.

Stored in memory are four constants designated G 1 and G 2 There are two Gl's and two G 2 's, one pair are utilized when the system is in discontinuous mode and the other pair of G 1 G 2 's is utilized when the system is in continuous mode These constants, used for continuous and discontinuous current modes, are gain constants chosen to provide the overall gain required by the motor drive loop when operating in either one of the modes For example, in discontinuous mode the program will select the proper G 1 and G 2, wherein they will have gains of 32 and 0 respectively Also, in this latter action block, negative and positive upper and lower limits (VRLIMN and VRLIMP) are retrieved from memory and brought into the interrupt subroutine for subsequent use in establishing upper and lower limits for the motor voltage to be computed by the current regulator.

Upon the completion of these last operations the program will now enter into the connector B of Fig 17 Referring now to Fig 17, it will be noted that connector A from Fig 16 also comes into Fig 17 As previously described, if the system is in the continuous mode, entry will be into Fig 17 connector A At entry into connector A, the operations which take place in the first action block are the same as that described in the last action block of Fig 16, with the exception that the MODFLG is set equal to 0 for continuous mode operation The program will also select the proper GI and G 2 for continuous current mode operation (an example of the values of these gains would be Gl= 15 and G 2 = 11).

Upon entry into connector B of Fig 17, the processor now sets the firing angle to cause an interrupt 200 after the last SCR pair firing This is accomplished by setting the firing angle FINVAL in memory equal to FINVAL minus a count proportional to 400 Subtracting 40 from FINVAL causes an interrupt at the correct time for the second current reading If TIMTGO were calculated utilizing the old value of FINVAL, the SCR pair would be fired 600 late r By subtracting 40 from FINVAL the down counter value is set to create aninterrupt at 20 after the last SCR pair firing The program now proceeds into an action block wherein a location in memory DESI, designating desired current set point, is set equal to itself plus a calculated value SPDESI, indicative of a desired rate of change of current set point.

The program now goes to a connector E of Fig 20 entering into an action block wherein the processor now sends a read device one command to the processor interface to read the system clock bits IDIBO-IDIB 7 on conductors 190 as I 1,598,919 1,598,919 depicted in Figs 4 and 5 In the next action block the 600 interval, as specified by bits IDIB 0-I Dl B 2, are stored in location KOCT (see Table 2) and the time within the interval, represented by bits IDIB 3 through IDIB 7, are stored in a location in memory designated TCLOCK.

The processor now proceeds to calculate the value of NEWTIM by setting that location in memory equal to TCLOCK plus 2, which is the delay time previously described for the calculation in describing the derivation of the TIMTGO equation.

Also, at this time the long clock count correction CORR is set equal to 0 The program now proceeds into a NEWTIM> 30 decision block If NEWTIM is greater than 30, the program will exit through a Y branch setting the CORR bit to a 1 The program will now proceed into another decision block NEWTIM> 31 If the NEWTIM is at 32, or greater, the program will exit through a Y branch into an action block at the top right hand portion of Fig 20, wherein NEWTIM is set to either 0 or I by setting NEWTIM=NEWTIM-32 If NEWTIM happens to be 32, then it will be set to zero whereas if NEWTIM is equal to 3 (i e.

TCLOCK= 31 + 2 = 33) it will be set equal to 1.

Reference is now made back to the NEWTIM> 30 and NEWTIM> 31 decision blocks of Fig 20 If either of those decisions is negative, the program will exit through an N branch of the appropriate decision block and enter into an action block wherein the zero crossing number PHA in memory is used to calculate TIMTGO by using the value of KOCT as an address to the PH Table (TABPH) by setting PHA equal to TABPH (see Table 2) The processor now proceeds to calculate TIMTGO by setting TIMTGO equal to FINVAL the firing angle minus TABTP (the offset correction of Table 2 as addressed by the difference between PHA and PH) minus 8 times TCLOCK (the time interval just read) minus the value of CORR CORR will be either a zero or a one at this time, depending on whether NEWTIM was greater than or less than 31 The processor now enters into a CURFLG= 0 decision block where a test is again performed to see if this is the first current reading If CURFLG is not equal to 0, indicating that this is a second current reading, then entry into Fig 21 is at connector F entering an action block wherein the processor writes the SCR pair and bridge address to device 3, the SCR select and drive direction register 268 of Fig 11 B, by issuing a WDV 3 command over conductors 270 and sending the SCR pair and bridge address over conductors 266 as write data bits WDB O through WDB 7 from the driver 138 of the processor system interface 64 The SCR pair and bridge addresses come from a table in memory designated as OCTF, which contains 12 separate address entries, 6 for the forward SCR bridge and 6 for the Reverse SCR bridge The locations in the OCTF table are addressed by the contents of the PH counter, which specified the SCR pair to be fired, and the direction flag DIRFLG, which is a flag in memory that specifies whether to fire the forward or reverse bridge.

It will be recalled from the previous description, that the firing of the SCR's actually takes place after the calculation of TIMTGO has been performed (i e.

subsequent to the reading of the second current) thus, it is necessary to change the SCR pair and bridge address in order to fire the proper SCR's On the other hand, if it is a first current reading it is not desirable to change the SCR pair and bridge address as no firing is done at that time Therefore, if it is not the first current reading, entry is into Fig 21 at point G from Fig 20 and the SCR pair and bridge address update is bypassed.

The program now proceeds into a TIMTGO< 16 decision block If TIMTGO is less than 16, the program exits through a Y branch to an action block wherein the processor writes the number 16 to device I, the down counter, by the generation of the WDVI signal from the processor system interface along with the number 16 on the write data bus lines WDB O through WDB 7 as previously described The reason for testing for TIMTGO< 16 is that a minimum limit is placed on the value of TIMTGO to ensure that there is always at least 40 delay prior to the generation of an interrupt to the data processor so that a convert command will be sent to the A/D converter 80 to cause a new conversion to be made.

Still referring to Fig 21, if TIMTGO is not less than 16, then the program branches through a NO branch entering into a READ DEVICE 1 action block wherein the processor again reads the system clock bits I Dl B O through IDIB 7 The program now goes into a loop via a decision block ID 1 B 3-IDIB 7 =NEWTIM which exits through a NO branch back into the read device I action block and continues to circulate in that loop until the system clock equals NEWTIM When these two values are equal, it is time to load the down counter, and the program takes a Y branch entering in to an action block wherein, the processor now writes TIMTGO into the down counter 224 of Fig 9.

As was previously described, on the occurrence of the next 88 micro-second clock signal (see Figs 9 and 10) following the loading of the down counter, the down counter starts to count TIMTGO down toward 0 When the down counter reaches 0, the processor will again generate an interrupt signal on conductor 210 from Fig.

9, thus creating another interrupt for the processor as previously described.

Immediately upon transferring TIMTGO to the down counter, the processor now goes from connector H in Fig 21 to connector H in Fig 22 entering into a CURFLG= O decision block In this decision block a test is then performed to see if this is the first current reading If it is the first reading, the processor will exit through an N branch entering into an action block wherein, location CURFLG, the current reading flag, is set equal to I to designate that the second reading will be coming up on the next pass through the program On the other hand, if it is the first reading, the program will exit from CURFLG= 0 decision block through a Y branch entering an action block wherein, the sequence counter PH is set equal to PH+ 1, thus incrementing the SCR pair address so that the proper SCR pair will be fired on the next calculation of TIMTGO.

The processor now proceeds into the PH> 6 decision block If PH is greater than 6, the program will exit through a Y branch entering into an action block, wherein PH will now be set equal to 1 in preparation to firing the SCR cell pair corresponding to the PH address of 1 On the other hand, if PH is not greater than 6, PH is not changed and the program exits through a NO branch entering into an action block, wherein the CURFLG location is set equal to 0 in preparation for the first current reading on the next pass through the program The interrupt subroutine now calls a subroutine designated RDTACH as illustrated in Fig.

24.

Reference is now made to Fig 24, wherein the processor now enters into a START RDTACH entry point to the READ tachometer routine In RDTACH the processor first reads input device 1, the system clock, by reading in the three most significant bits (I Dl B 0-IDIB 2) of that clock It will be recalled that these bits define the 600 interval of the input voltage when the reading is taken by the processor.

The processor now enters into a PHOCT=IDIBO-IDIB 2 decision block In this decision block, a test is being performed to see if a phase to neutral zero crossing has occurred since the last pass through the subroutine This is performed by comparing the three most significant bits of the 3600 system clock (IDIB 0-IDIB 2) with location PHOCT which contains the reading or value of the 600 interval from the previous pass through the subroutine A change in I Dl BO-IDIB 2 65 means that a 0 crossing has occurred and that a new value should be stored in PHOCT to update that location for subsequent tests This is performed in an action block entere from a NO branch of 70 the PHOCT=IDIBO-ID 1 B 2 decision block, wherein PHOCT is set equal to ID 1 BO-IDI 1 82 On the other hand, if there has been no change in the zero crossing, then the program will exit through a Y branch and return back to Fig 22 from the point where it left off entering into a CURFLG= 1 decision block.

Referring back to Fig 24, let it now be assumed that a change has occurred in the zero crossing, thus changing the value of IDIBO-IDIB 2 As a result, the program will now exit from the PHOCT=IDIB 0-IDIB 2 decision block, set PHOCT as previously described and enter into an action block wherein the processor will now read device 3, the tach pulse counter, by reading bits I 1 D 3 80-ID 3 B 7 and IDOB 4 into the 90 processor Referring to Fig 7, it will be recalled that bit IDOB 4 was identified as that bit which specifies the direction the motor is running in Thus, in this action block, the value of the tach pulse counter is 95 read into the processor and the sign of that value is set in accordance with the state of IDOB 4 As such, the value of the tach pulse counter will represent either a positive or a negative number, indicating that the motor 100 is running in either the forward or reverse direction In the present system, the addressing of input device 3 through the 8 bit multiplexer of Fig 4 also causes bit IDOB 4 to be read through that multiplexer 105 and placed into the processor simultaneously with the ID 3 80 through ID 3 B 7 bits.

Still referring to Fig 24, the processor now proceeds to an action block wherein 110 the tachometer reading is added to the sum of the previous readings taken by adding ID 3 BO-ID 3 B 7 to a location CACTI, identified as a tach counter accumulator in memory This it can be seen, for each pass 115 through the RDTACH subroutine, that the tach readings from the tach pulse counter 88 are accumulated as a sum in location CACTI The processor now proceeds into the next action block, wherein a number of 120 readings counter CKNT in memory is updated or incremented by 1 by setting CKNT=CKNT+I.

1,598,919 -21 1,598,919 The purpose of the CKNT counter is to keep track of the number of accumulated readings in CACTI This is indicated by a decision block CKNT= 3 in the right hand top portion of Fig 24 which performs a test to see if there have been 3 readings accumulated If CKNT does not equal 3, the speed smoothing calculations are not performed, thus the program exits through a NO branch and returns back to the interrupt subroutine where it left off entering into the CURFLG=l decision block of Fig 22 as previously described.

Referring back to Fig 24, let it now be assumed that three readings have been accumulated, thus the program exits through a Y branch entering into a decision block wherein the unsmoothed motor speed is calculated This is accomplished by setting a location TEMP in memory equal to the sum of the accumulated tach pulses over the last two passes This is average motor speed The sum is accomplished by setting TEMP=CACT, a memory location which stores the old sum of the tachometer speed readings with location CACTI, which contains the sum of the new tachometer readings Also in this action block, location CACT is set equal to CACTI so that it reflects the sum of the old readings.

Further, CACTI is set equal to zero so that it can be initialized to accumulate the sum of the next readings on subsequent passes.

Further, a speed flag SPDFLG is initialized to a binary zero SPDFLG is utilized, as will subsequently be described, to tell the processor to either perform the speed regulator calculations or to skip the speed regulator calculations When SPDFLG is equal to zero, it indicates to the program to skip the speed regulator calculations The program now proceeds into the next action block of Fig 24, wherein the smooth speed is calculated This is accomplished by setting a location TACSMD=location TEMP-TACSUM.

Additionally in that action block, a location TACSUM is set equal to TACSUM+TACSMD Location TACSUM contains a value proportional to the smoother speed and TACSMD is speed rate which can be seen to be a derivative of TACSUM The program now proceeds to calculate the feed/forward counter electromotive force CEMF for subsequent use in calculating the motor terminal voltage VT CEMF is calculated by setting a location CEMF in memory equal to KV times location TEMP KV is a constant stored in memory having the value derived from the formula KV=CEMF (VOLTS divided by rpm.

With the speed calculations now complete, the processor now returns back to the interrupt subroutine in Fig 22 entering into the CURFLG=l decision block In this decision block, if CURFLG is equal to 1, indicating that this is the second current reading, then the program will not perform the current speed regulator calculations Thus, the program will take a Y branch entering into point J at the top of Fig 22, wherein the saved registers are restored as previously described and the program returned back to the main program at the point of interrupt in Fig 15 Let it be assumed however, that the CURFLG is not equal to 1, indicating that this is the first current reading, thus the processor now enters into a connector I of Fig 23, wherein the speed flag SPDFLG is set equal to SPDFLG+ 1 A test is now performed in a SPDFLG=l decision block to see if the speed flag is set If the speed flag is set, the speed regulator calculations are performed by the program exiting through a Y branch of that decision block entering into an action block to calculate speed error.

The speed error is calculated by setting a location ERRACT in memory, which is a location for storing speed error, equal to the contents of location CHALF, speed set point, minus the contents of location CACT, the old sum of the speed reading or the speed before smoothing Proceeding through the program, the processor now initiates the calculation of current setpoint by setting location ERRACT=G 3 x ERRACT-G 4 x TACSMD.

G 3 and G 4 are regulator gains adjusted 100 according to the particular drive motor to give the desired speed response Values of G 3 = 1 and G 4 = 16 were used in this embodiment.

The processor now continues to calculate 105 the current set point by setting a value TDESI=TDESI+ERRACT.

The program now continues into a TDESI>CURLMP decision block at the top of Fig 23 A maximum limit is placed on 110 the motor current in the present drive system, thus a test is performed to see if the value of TDESI, the calculated motor current, is greater than or less than specified current limits CURLMP and CURLMN 115 CURLMP is the positive current limit and CURLMN is the negative limit, as indicated in a TDESI<CURLMN decision block of Fig 23 If TDESI is greater than CURLMP, the program exits through a Y branch 120 entering into an action block where TDESI is set equal to the maximum current limit CURLMP On the other hand, if CURLMP 1,598,919 is not greater than TDESI, the program exits through an N branch into the TDESI<CURLM decision block If that test is positive, the program will exit through a Y branch, wherein TDESI is set equal to CURLMN On the other hand, if it is a negative test, the program will exit through an N branch entering to an action block wherein the current rate set point is now calculated The current rate set point is calculated by setting a location in memory designated SPDESI (current set point rate) equal to TDESI (calculated current set point) minus DESI (the current set point) and dividing the difference by 3 The divisor 3 being utilized to take into consideration the averaging of the current rate set point over 3 passes through the current regulator calculation program for each speed regulator calculation.

A current rate limit is also placed on the current rate set point SPDESI This is accomplished by the program now entering into an SPDESI>RTLMP decision block, wherein a test is performed to see if SPDESI is greater than RATLMP a positive rate limit If it is greater, then the program exits through a Y branch into an SPDESI=RATLMP action block establishing a maximum positive rate limit for SPDESI On the other hand, if SPDESI is less than RATLAMP, the program exits through an N branch entering into an SPDESI<RATLMN decision block In that decision block, if SPDESI is less than RATLMN, the program exits through a Y branch, thus setting SPDESI=RATLMN, establishing a minimum rate limit If SPDESI is not less than RATLMN, then the program exits through a NO branch, and enters into point J of Fig 22, wherein the previously saved processor registers are restored and the program returns back to the main program at the point of interrupt as previously described.

Still referring to Fig 23, reference is made back to the SPDFLG= 1 decision block of that Figure If SPDFLG is equal to I, it indicates that the speed regulator calculations are to be skipped over, thus the program exits from the block through an N branch entering back to point J of Fig 22 as just described.

* Reference is now made back to Fig 16 to the 1st CURRENT READING CURFLG= 0 decision block, wherein a test performed to see if the program is taking the first or second current reading If CURFLG is not equal to zero, it indicates that the first current reading has just been taken, as previously described, that the second current reading should be taken and the current regulator calculations performed.

Under this condition, the processor will now 65 exit through an N branch at connector C entering in to Fig 18.

The first operation to take place in Fig.

18, is for the processor to send a read device 5 command to read the analog to 70 digital current converter 80 and store bits ID 5 BO-ID 5 B 7 in location CRNT, the location for storing actual motor current.

The processor now enters into an action block and calculates the current error by 75 setting location IDIFF equal to location DESI, the current set point, minus CRNT the actual motor current A test is now performed in an IDIFF>+IDLIM decision block to determine if the current error is 80 greater than a positive current error limit as specified the constant+IDLIM If IDIFF is greater than +IDLIM, the program will branch through a Y exit entering to an action block where an IDIFF is set equal to 85 +IDLIM On the other hand, if IDIFF is not greater than +IDLIM, the program exits through an N branch entering into an IDIFF-IDLIM decision block In this block, the same type of decision is made to 90 determine if IDIFF is less than a negative or minimum current error limit If it is, the program exits through a Y branch, wherein IDIFF is set equal to -IDLIM On the other hand, if IDIFF is not less than 95 -IDLIM the program exits through the N branch and enters into an action block, wherein the motor terminal voltage is calculated by the regulator.

The motor terminal voltage is calculated 100 by setting a location VR, which is an intermediate value in the calculation, equal to (G 1 x IDIFF)-(G 2 x IDIFFO).

Gains Gl and G 2 were previously 105 identified Gain 1 (Gi) for discontinuous current mode operation is normally 2 to 3 times the value for continuous current operation and Gain 2 is equal to 0 for discontinuous current mode operation The 110 IDIFFO term is a location in memory which stores the old value of IDIFF The program now proceeds to a DIRFLG= O decision block In that decision block, a test is being performed to see if the forward bridge is 115 being fired by testing the condition of DIRFLG, a flag in memory which specified which bridge is being fired If DIRFLG is not equal to zero, indicating that the reverse bridge SCR's are being fired, exit is made 120 through an N branch and VR is set equal to VRO-VR where, VRO is from a location in memory storing the old value of VR If DIRFLG is equal to 0, indicating that the forward SCR's are being fired, the program 125 1,598,919 then exits through a Y branch into an action block wherein VR is set equal to VRO+VR. Upon the completion of calculating VR,

the program enters into a decision block VR>VRLIMP There are two constants, (VRLIMP and VRLIMN) stored in memory which specify positive and negative limits on the maximum and minimum calculated voltage If VR is greater than VRLIMP, then exit is made from that decision block through a Y branch into an action block wherein VR is set equal to VRLIMP On the other hand, if VR is not greater than VRLIMP, an N branch is taken and entry is made into a VR<VRLIMN decision block.

In that block, a Y branch is taken wherein VR is set equal to VRLIMN if VR is less than VRLIMN If not, an N branch is taken and VRO, the location for storing the old value of VR, is updated by setting VRO=VR.

The program now enters into point D leaving Fig 18 and entering to point D of Fig 19 Upon entering into Fig 19, the processor now enters into an MODFLG= O decision block where a test is performed to see if the system is in continuous or discontinuous current mode If the MODFLG is not equal to 0, it indicates that the system is in continuous mode Thus, the processor exits from a NO branch entering to a DIRFLG= 0 decision block It is in the flow chart of Fig 19 where the decision is made as to whether it is appropriate to reverse the direction of the motor The criteria for reversal of the motor is that the system must be in discontinuous current mode and the sign of the current set point (DESI) must be opposite to the direction flag (DIRFLG) This determination of current reversal is explained as follows If the MODFLG= 0 decision test is positive, the processor will exit through a Y branch indicating discontinuous mode into a sign of DESI OPP DIRFLG decision block In this latter decision block, the determination is made to see if DESI is opposite to DIRFLG If it is not opposite, an N branch is taken and the program enters into the DIRFLG= 0 decision block as previously described However, if the DE Sl is opposite DIRFLG, the program takes a Y branch and enters in to an action block, wherein the direction flag DIRFLG is reversed from its present state As shown in that action block, if DIRFLG is set equal to a 1, it indicates that current will flow in the reverse bridge and not the forward bridge.

If DIRFLG is set equal to zero, then the forward bridge will be fired The program now proceeds into the DIRFLG= 0 decision block to determine the relative polarity of CEMF and voltage from the bridge If the reverse bridge is to be fired, the N branch is taken from that decision block and entry is made into an action block, wherein the desired terminal voltage VT is calculated by setting VT=CEMF (the counter electromotive force) minus VR (the motor voltage since the polarities are opposite) If 70 the forward bridge is to be fired, as indicated by DIRFLG=O, then entry is made through the Y branch into an action block wherein the desired motor terminal voltage VT is calculated by setting 75 VT=CEMF+VR to establish its proper polarity.

In the present system, the motor terminal voltage has positive and negative limits placed on it, thus the tests immediately 80 following the calculation of VT are to determine whether VT is equal to or less than positive and negative limits The first decision block after the calculation of VT is VT>VTLIMP If VT is in excess of the 85 positive limit a Y branch is taken into an action block, wherein VT is set equal to the maximum positive limit VTLIMP On the other hand, if VT is less than VTLIMP, a no branch is taken and a similar test for 90 VT<VTLIMN is performed If VT is less than the minimum limit, then a Y branch is taken and VT is set equal to VTLIMN If not, the N branch is taken from the VT<VTLIMN decision and entry is then 95 made into an action block of Fig 19 wherein the firing angle FINVAL to develop the desired VT is extracted from the table of values computed on the previously described relation FINVAL= 245 8 COS-1 100 ( 3 VT/7 r VLN) as previously described It will be recalled that these values of FINVAL were previously described and shown in Table 1 This type of table entry, is well known in the art and is a straight-forward 105 manner of merely addressing the table at an address specified by the value of VT, and using the value of the location addressed as the firing angle FINVAL.

The program now exits Fig 19 at 110 connector E and enters in at connector E of Fig 20 wherein the system clock is read by the processor in a manner as previously described The program will not continue to execute in Fig 20, and proceed through its 115 execution, finally returning back to the interrupt point of the main program in the manner as previously described.

Having described the invention in detail, it can now be appreciated that the overall 120 structure and method of the present system consists of a main program which loops continuously to read the speed reference switches and the motor direction switch and compute the speed set-point for the motor 125 The interrupt program accepts speed setpoint data from the main program and reads motor speed armature current, and time as measured by the 3600 system clock The interrupt program further calculates the 130 1,598,919 desired firing angle for the SCR's and controls the processor to send data having a value proportional to firing angle to a counter in the system and an address word to an SCR select and drive direction logia to effect the generators of gating pulses for the direct digital firing of SCR's as selected by the address data to regulate and control a reversing 3-phase drive motor system The program is synchronized with the firing of the SCR's by virtue of the generation of an interrupt at each SCR firing to start the regulator calculations to load the counter at the proper time to control the time of firing a next SCR to be fired.

The processor of the system reads armature current twice each 60 electrical degrees A first armature current reading is taken at a predetermined time (e g 4 degrees) before the next SCR is to be fired.

This first current reading is used to determine the mode of the current regulator operation, (continuous or discontinuous) A second current reading is taken and regulator calculations are started approximately 200 after the previous firing of an SCR The second current reading is used by the current regulator program as current feedback for controlling the overall current regulator.

Thus it is seen, that there has been shown and described a regulating and control system for controlling a load such as DC motor which enjoys the benefits of a processor, such as a micro computer, and which far exceeds the capabilities of prior analog regulating and control systems with limited additional expense.

Attention is directed to our copending application No 51571/77, (Serial No.

1598918) from which the present application was divided, and which describes and claims a method of a system for controlling a controllable rectifier.

Claims (1)

1. WHAT WE CLAIM IS:-

   1 A method of controlling a controllable rectifier connected between an AC source and a DC motor in a system of the type including a data processor programmed to calculate a firing angle to develop a firing pulse to fire the controllable rectifier to regulate the speed of the DC motor, comprising the steps of:a) reading into the processor parameters corresponding to desired motor speed; b) directing the processor to: read a value corresponding to motor current; compare the value with a stored value corresponding to a predetermined current; establish a continuous or discontinuous current mode of operation according to the result of the comparison; select a system gain corresponding to the established mode of operation; read, after a predetermined delay, a value corresponding to actual motor voltage; calculate a value for determining the firing angle as a function of the difference between the desired motor speed and the actual motor speed, the difference between the previously read motor current and the last read motor current, and the previously calculated firing angle determining value; read a first value corresponding to phase interval of the AC source from zero-crossings of the AC source; read a second value which is synchronized with the first value and represents an increment of time within the phase interval; calculate a time to use the firing angle determining value by comparing the second value with a predetermined constant proportional to system calculation time; calculate the firing angle determining value as a value proportional to required motor terminal voltage which is dependent on the selected system gain; derive an address of a rectifier to be fired from the first value; repeatedly compare the value of the calculated time to use the firing angle with the second value; and repeatedly incrementally changing the firing angle when the calculated time and the second value correspond; c) generating a firing pulse and sending it to the rectifier whose address has been calculated when the repeatedly incremented firing angle reaches a predetermined value; and d) repeating steps b) and c).

   J A BLEACH & CO, Agent for the Applicants.

   Printed for Her Majesty's Stationery Office, by the Courier Press, Leamington Spa, 1981 Published by The Patent Office, 25 Southampton Buildings, London, WC 2 A l AY, from which copies may be obtained.