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GB1597594A - Manufacture of semiconductor elements - Google Patents

Manufacture of semiconductor elements Download PDF

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Publication number
GB1597594A
GB1597594A GB2738/77A GB273877A GB1597594A GB 1597594 A GB1597594 A GB 1597594A GB 2738/77 A GB2738/77 A GB 2738/77A GB 273877 A GB273877 A GB 273877A GB 1597594 A GB1597594 A GB 1597594A
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United Kingdom
Prior art keywords
layer
produced
substrate
process according
semiconductor
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GB2738/77A
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Funkwerk Erfurt VEB
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Funkwerk Erfurt VEB
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Publication of GB1597594A publication Critical patent/GB1597594A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H01L21/31155—Doping the insulating layers by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32131—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Electron Beam Exposure (AREA)
  • Physical Vapour Deposition (AREA)
  • Drying Of Semiconductors (AREA)

Description

(54) IMPROVEMENTS RELATING TO THE MANUFACTURE OF SEMICONDUCTOR ELEMENTS (71) We, VEB FUNKWERKERFURT (formerly KOMBINAT VEB FUNKWERK ERFURT), of 50, Erfurt, Rudolfstrasse 47, German Democratic Republic, a Corporation organised and existing under the laws of the German Democratic Republic, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- This invention relates to a process for the manufacture of a semiconductor element (hereinafter referred to as "a process as hereinbefore defined") in which there is provided between an ion source and a semiconductor substrate of a said element a mask which has a structure to be produced in said element and in which modifications in the substrate or in at least one disposed thereon are produced.
In the manufacture of semiconductor components, it is known to use photolithographic processes for producing the structures; the layers to be structured are coated with a photoresist, subsequently exposed to light according to the desired structures, and developed. In the developing process which follows, a locally confined region of the layer of photoresist is removed. In these regions the layer disposed thereunder is subsequently removed by means of liquid etchants, either wholly or partially depending on the subsequent process step. Depending on the technology applied, this procedure is repeated an appropriate number of times. Besides semiconductor layers, the layers to be structured may be insulating or conductive.
Photolithographic processes have the disadvantage that, by reason of the wet processes required, uncontrollable contamination is caused which may result in unstable electrical parameters and a reduction in the yield. A significant disadvantage resides in the fact that in the photolithographic processes there is a theoretical limit to the resolution imposed by the wavelength of the light used.
There are moreover known ion implantation processes for the purpose of doping the entire area.
There is also known the process involving the writing ion beam (precision beam technology), which, however, is too time-consuming on account of the high doses required for the purpose.
It is also known that, relative to unradiated oxide, silicon oxide which has been subjected to ion radiation has the property of differential rates of etching which depend on the radiation dose and the quality of the oxide.
The objects of the invention are to eliminate the disadvantages described, to provide a process capable of giving a higher yield, and to provide a process for the manufacture of semiconductor structures, in which the wet processes required in photolithographic processes are avoided, which gives a higher resolution and thus a higher degree of integration coupled with good reproducibility of the parameters, which enables the structuring of electrically conductive layers required in the manufacturing process for semiconductor structures to be performed nonphotolithographically and which, to a large extent, eliminates contamination.
According to the invention, in a process as hereinbefore defined, said mask is arranged between the ion source and the substrate in such a way that a reduced image of the mask is produced by means of an ion beam radiating from said source on the substrate or said at least one layer disposed on said substrate, said substrate and/or said at least one layer being thereafter subjected to an etching process, in which the desired structure is produced by reason of differential etching between regions of said element which have, and regions which have not, been subjected to radiation from said source.
The etching process may be a wet-, gaseous phase- or plasma etching process.
The process embodying the invention may be applied to the manufacture of a semiconductor component comprising at least one bipolar or unipolar circuit.
The process embodying the invention may be applied to the doping of a predetermined portion of said substrate.
It has been found that, by bombardment of metallic layers by high-energy protons, structural modifications are produced of a kind in which there is a differential etching rate between bombarded and unbombarded regions.
By means of apparatus comprising an ion source, from which an ion beam of high divergence is emitted, from which, by means of a system of apertures, a partial beam, which is of homogeneous intensity and which passes through a mark having the structure of which an image is to be produced, is created, a reduced image of the mask structure is produced on the semiconductor substrate by means of an ion-optical system arranged between said source and said substrate. Such apparatus is described and claimed in the complete specification of our co-pending patent application 25964/78.
(Serial No. 1 597595.) The technical advantages of the invention reside in the fact that, in using the process, as compared with the known processes, nonphotolithographic structuring of the electrically conductive layers is achieved. Thus, it is possible, in connection with the non-photolithographic structuring of suitable silicon dioxide insulating- and protective layers to perform, by using the process, a semiconductor manufacturing process which, as compared with known processes, is entirely nonphotolithographic.
As compared with known processes, a significantly higher resolution is also achieved, and thus a higher packing density and, by reducing the contamination, an improvement in the stability of the electrical parameters is made possible. The thermal stressing as well as the requirements for accuracy of positioning of the exchangeable masks are smaller by a factor of 102 (area) as compared with a contact mask process, by reason of the 10-fold reduction produced by the object-glass. Likewise the requirements concerning the manufacturing tolerances for the exchangeable masks are reduced by a factor of 10, as compared with the requirements for the quality of the image, i.e. 1 ttm of tolerance in the accuracy of positioning of the mask corresponds, in the case of a reduction ratio of 1 :10, to an image displacement of 0.1 gum.
The economic effects reside in simplification of the technical procedure, a significant increase in the periods of application of the masks as compared with conventional photographic stencils, as well as an increase in the yield.
The present invention will now be explained in greater detail with reference to the following example: The insulating layers on the semiconductor surface which, as a rule, consist of silicon dioxide, are bombarded, preferably with light ions, over a locally confined region, by means of the apparatus hereinbefore referred to. The said apparatus is an ion-optical appliance, which will hereinafter be referred to as an ion projector.
The ion projector defines a combination of a particle accelerator and an ion-optical projection device, which consists of an ion source, an ion-optical system (object-glasses), an arrangement for receiving, preferably self-supporting, metal masks, a target chamber with a transfer device for semiconductor substrates, an appropriate vacuum system and a variety of measuring, electronic and electrical auxiliary devices.
Light ions, for example protons or mixtures of light ions, are produced in an ion source and extracted from the latter in such a way that the ion beam is of high divergence.
By means of a system of apertures, a partial beam of high homogeneity of intensity is created, which passes through a mask of which an image is to be produced and on which appropriate semiconductor structures are formed. By means of a focussing lens, the total intensity of the beam passing through the mask is directed into the entrance aperture of the objective of which an image is to be produced. The objective reduces the mask of which an image is to be produced according to the spacing between the objective and the image, e.g. by a factor of 10 relative to the original size of the desired structure on the semiconductor substrate, the image being created in the vicinity of the focal plane and the objective lens potential difference defining the majority of the energy of the ions.
This "ion image" of the mask now impinges on the silicon dioxide layer and penetrates the latter to a depth depending on the energy and nature of the ions.
The electrostatic lenses and the stability of the high tension are so arranged that the optical quality, depth of focus and resolution satisfy the requirements. When using protons having an energy of, e.g. 60 keV, the theoretical resolution is approximately 10-3 A.
For the purpose of effective application of the ion projector to the production process, the latter is provided with a device for changing the masks, of adequate accuracy.
There is moreover provided a target chamber of appropriate capacity with all the auxiliary equipment, for accommodating the semiconductor substrate.
The subsequent etching process for structuring the insulating layer is carried out by a dry etching procedure by means of gaseous etchants and preferably, though not necessarily, with the complete elimination of wet processes.
The electrically conductive layer of the semiconductor structure, which frequently consists of aluminium, is bombarded in locally confined regions with protons (H±ions) by means of the aforesaid apparatus, structural modifications in the aluminium layer being produced in such a way that, in the course of the etching processes, the bombarded regions have a higher etching rate relative to non-bombarded regions. In the said apparatus, the protons are accelerated to energies of 40--100 keV.
The required dose is 10'71019 protons per cm2. Following the locally confined bombardment of the aluminium layer, the structured, electrically conductive Al-layer of the semiconductor structure is produced by an Al-etching process.
WHAT WE CLAIM IS: 1. A process for the manufacture of a semiconductor element, in which there is provided between an ion source and a semiconductor substrate of a said element a mask which has a structure to be produced in said element and in which modifications in the substrate or in at least one layer disposed thereon are produced, said mask being arranged between the ion source and the substrate in such a way that a reduced image of the mask is produced by means of an ion beam radiating from said source on the substrate or said at least one layer disposed on said substrate, said substrate and/or said at least one layer being thereafter subjected to an etching process, in which the desired structure is produced by reason of differential etching between regions of said element which have, and regions which have not, been subjected to radiation from said source.
2. A process according to Claim 1, wherein said structure is produced on an electrically insulating said layer.
3. A process according to Claim 1, wherein said structure is produced on an electrically conductive said layer.
4. A process according to Claim 3, wherein said electrically conductive layer is an aluminium layer and wherein said ion beam comprises protons.
5. A process according to any one of Claims I to 3, wherein said ions are light ions.
6. A process according to any one of the preceding claims, wherein a plurality of partial masks, each of which is subjected to ion radiation, are used for producing said structures which are relatively long or of a closed loop configuration.
7. A process according to any one of the preceding claims, applied to the manufacture of a semiconductor component comprising at least one bipolar or unipolar circuit.
8. A process according to any one of the preceding claims, applied to the doping of a predetermined portion of said substrate.
10. A process for the manufacture of semiconductor elements, the process being substantially as hereinbefore described.
11. A semiconductor element which has been subjected to a process according to any one of the preceding claims.
**WARNING** end of DESC field may overlap start of CLMS **.

Claims (1)

  1. **WARNING** start of CLMS field may overlap end of DESC **.
    The subsequent etching process for structuring the insulating layer is carried out by a dry etching procedure by means of gaseous etchants and preferably, though not necessarily, with the complete elimination of wet processes.
    The electrically conductive layer of the semiconductor structure, which frequently consists of aluminium, is bombarded in locally confined regions with protons (H±ions) by means of the aforesaid apparatus, structural modifications in the aluminium layer being produced in such a way that, in the course of the etching processes, the bombarded regions have a higher etching rate relative to non-bombarded regions. In the said apparatus, the protons are accelerated to energies of 40--100 keV.
    The required dose is 10'71019 protons per cm2. Following the locally confined bombardment of the aluminium layer, the structured, electrically conductive Al-layer of the semiconductor structure is produced by an Al-etching process.
    WHAT WE CLAIM IS:
    1. A process for the manufacture of a semiconductor element, in which there is provided between an ion source and a semiconductor substrate of a said element a mask which has a structure to be produced in said element and in which modifications in the substrate or in at least one layer disposed thereon are produced, said mask being arranged between the ion source and the substrate in such a way that a reduced image of the mask is produced by means of an ion beam radiating from said source on the substrate or said at least one layer disposed on said substrate, said substrate and/or said at least one layer being thereafter subjected to an etching process, in which the desired structure is produced by reason of differential etching between regions of said element which have, and regions which have not, been subjected to radiation from said source.
    2. A process according to Claim 1, wherein said structure is produced on an electrically insulating said layer.
    3. A process according to Claim 1, wherein said structure is produced on an electrically conductive said layer.
    4. A process according to Claim 3, wherein said electrically conductive layer is an aluminium layer and wherein said ion beam comprises protons.
    5. A process according to any one of Claims I to 3, wherein said ions are light ions.
    6. A process according to any one of the preceding claims, wherein a plurality of partial masks, each of which is subjected to ion radiation, are used for producing said structures which are relatively long or of a closed loop configuration.
    7. A process according to any one of the preceding claims, applied to the manufacture of a semiconductor component comprising at least one bipolar or unipolar circuit.
    8. A process according to any one of the preceding claims, applied to the doping of a predetermined portion of said substrate.
    10. A process for the manufacture of semiconductor elements, the process being substantially as hereinbefore described.
    11. A semiconductor element which has been subjected to a process according to any one of the preceding claims.
GB2738/77A 1976-02-04 1977-01-24 Manufacture of semiconductor elements Expired GB1597594A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DD76191181A DD136670A1 (en) 1976-02-04 1976-02-04 METHOD AND DEVICE FOR PRODUCING SEMICONDUCTOR STRUCTURES

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GB1597594A true GB1597594A (en) 1981-09-09

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GB25964/78A Expired GB1597595A (en) 1976-02-04 1977-01-24 Manufacture of semiconductor elements
GB2738/77A Expired GB1597594A (en) 1976-02-04 1977-01-24 Manufacture of semiconductor elements

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JP (1) JPS52155064A (en)
CS (1) CS209199B1 (en)
DD (1) DD136670A1 (en)
DE (1) DE2701356A1 (en)
FR (1) FR2340565A1 (en)
GB (2) GB1597595A (en)
SE (1) SE7700374L (en)

Cited By (3)

* Cited by examiner, † Cited by third party
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US4967088A (en) * 1987-06-02 1990-10-30 Oesterreichische Investitionskredit Aktiengesellschaft Method and apparatus for image alignment in ion lithography
US5266409A (en) * 1989-04-28 1993-11-30 Digital Equipment Corporation Hydrogenated carbon compositions
US5750422A (en) * 1992-10-02 1998-05-12 Hewlett-Packard Company Method for making integrated circuit packaging with reinforced leads

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4325182A (en) * 1980-08-25 1982-04-20 General Electric Company Fast isolation diffusion
GB2165692B (en) * 1984-08-25 1989-05-04 Ricoh Kk Manufacture of interconnection patterns
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US5266409A (en) * 1989-04-28 1993-11-30 Digital Equipment Corporation Hydrogenated carbon compositions
US5750210A (en) * 1989-04-28 1998-05-12 Case Western Reserve University Hydrogenated carbon composition
US5750422A (en) * 1992-10-02 1998-05-12 Hewlett-Packard Company Method for making integrated circuit packaging with reinforced leads

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CS209199B1 (en) 1981-11-30
DE2701356A1 (en) 1977-08-18
SE7700374L (en) 1977-08-05
FR2340565A1 (en) 1977-09-02
GB1597595A (en) 1981-09-09
JPS52155064A (en) 1977-12-23
DD136670A1 (en) 1979-07-18

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