GB1459819A - Data handling system - Google Patents

Abstract

1459819 Data processing system INTERNATIONAL BUSINESS MACHINES CORP 29 Oct 1974 [26 Dec 1973] 46679/74 Heading G4A [Also in Division H4] A data handling or processing system includes a central unit and a number of other units each arranged, in response to a sequence of timing signals, to perform a sequence of operations, each of the other units including an individual timing circuit generating an appropriate single sequence of timing signals in response to an input signal and generating a "DONE" signal on completion of the sequence, and the central unit including means to issue input signals to selected ones of the other units to cause them to perform their sequences of operations and means to prevent the issue of further input signals until a "DONE" signal has been received from each of the selected other units. Timing signal generation.-Each unit, including the central unit, has a circuit, Fig. 2 (not shown), for generating a sequence of timing signals. The circuit includes a series of latches (A, B, C) which are set and reset in a timed sequence (which depends on circuit delays) in response to an input signal (DO). The output of one of the latches is fed to a delay line formed of a cascaded series of inverters and further logic circuits, controlled by additional control inputs (L, M), selectively connect various taps along the delay line to the latches to introduce a delay in the timed sequence of signals. System.-The central control unit, Fig. 5, includes a timing circuit 80 which produces a series of timing signals to gate a control word from a store 81 to one of the registers 88, 89. The timing sequence then stops and part of the control word sends "DO" signals to selected other units to activate them. As each activated unit finishes its operation it returns a "DONE" signal to the central unit where it is compared, 95, with mask signals. When all activated units finish their operations a positive comparison produces a "NEXT" signal to advance the central unit timing circuit and extract the next control word which is addressed via line 100 by its predecessor. An example of one of the other units is shown in Fig. 4 where data is successively gated into a logic unit 69, and result data gated to an output in response to clock signals A, B, C (only A and C being used), a "DONE" signal being produced when the result data is produced. The clock circuits may be formed in the same integrated circuit chip as the unit to which they belong. The sequences of operations in each of the units may include an error check operation, detection of an error causing the central unit to reinitiate the same sequence of operations (retry).