GB1448178A - Error detection and correction in data transmission - Google Patents

Abstract

1448178 Data transmission; error correction STANDARD TELEPHONES & CABLES Ltd 18 July 1974 31844/74 Addition to 1428050 Heading H4P In an automatic retransmission error correction duplex data transmission system as disclosed in the parent Specification 1,428,050 in which blocks to be transmitted are numbered in a cyclic serial sequence, which numbers may or may not be transmitted, with parity bits included in each block for error detection, the sequence character is added modulo-2 to all or preselected groups of parity bits of all, or some of the blocks in order to indicate, at the receiving end, non-alignment of counters defining the sequence characters. Where mod-2 addition is performed on some only of the blocks, condition of non-alignment is distinguished from transmission error as disagreement is registered only to the some blocks. The some blocks may be every nth block and preferably n is odd, e.g. n=3 in a particular embodiment. Fig. 1 shows one embodiment of a modification which may be made to a transmitter as disclosed in the parent Specification 1,428,050. When a block awaiting transmission is one to be modified, gate G3 is enabled when a group of four parity bits is approaching exclusive-OR gate A1, in which a sequence number stored in register SR1 is added mod-2, and thence passing through gate G2 to line. At the receiver, Fig. 2, parity bits generated from the incoming stream in decoder D are added to received parity bits in mod-2 adder A3 and if correspondence is registered gate G7 is enabled allowing contents of register RDS to pass to a utilizing device. Parity bits corresponding to those in which a sequence number is added are similarly treated hence sequence counter SCR counts correctly received and accepted data blocks the result being placed in a shift register SR2. When these particular parity bits are about to leave decoder D, gate G6 is enabled thus the sequence number and parity bits are added mod-2 in A2 the reuslt being applied to A3 at the same time as the modified parity bits are received from the remote station. As transmission error alters parity, an error indication will be given and similarly if transmitting and receiving counters fall out of step, the modified parity bits presented to A3 differ: this also gives an error signal (which may be different) hence adding sequence numbers to some blocks enables distinguishment between the types of error.