GB1366673A - Control of shift registers - Google Patents

Abstract

1366673 Shift register stores COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS CIT-ALCATEL and SOC LANNIONNAISE D'ELECTRONIQUE 20 Sept 1971 [18 Sept 1970] 43688/71 Heading G4C A shift register comprises a number of serially connected stages or groups of stages, each stage comprising two series-connected bi-stables. A bit is read into the first of the bi-stables in any one stage under the control of a pulse from a first train of clock pulses and is read into the second bi-stable under the control of a second train. The first and second clock pulse trains fed to one stage or group of stages differ from those fed to another stage or group. In a conventional register, Fig. 1 (not shown), the same first and second trains h1, h2, Fig. 5, are fed to each stage so that a bit fed to the first stage appears at the outputs of successive stages A, B, C ... in turn at the times indicated by I1. By feeding differing trains to the stages the pulse appears at successive stages at different times. For example, if odd-numbered stages are fed with first and second trains h1, h2 and the even-numbered stages with first and second trains h2, h1, every third pulse of h1 and h2 being omitted, the output pulse timing pattern is as at I3. In another arrangement, Fig. 4 (not shown), the pattern is as at I4.