GB1340220A - Data storage apparatus - Google Patents

Abstract

1340220 Error detection/correction INTERNATIONAL BUSINESS MACHINES CORP 23 July 1971 [23 July 1970] 34618/71 Heading G4C A digital data storage system includes an error detection means operable to read out a previously stored word and generate an error signal if the word was incorrectly stored, a means being provided responsive to the error signal for inverting all the bits of the read out word and entering it into the location from which it was read in inverted form together with a marker bit indicating that the word is stored in inverted form. In the preferred embodiment the memory 1 is a monolithic integrated circuit store storing words which contain an even number of bits including data bits, a parity bit, and the marker bit. In operation a word to be stored is fed from a source 5 to the store inputs 10 via AND gates 7. The word is then read out and stored in register 14. The read out word is then tested for errors by parity checking circuits (not described) and/ or by comparison with the input word. If an error is detected a signal is passed to flip-flop 21 via AND gate 19. The output of the flip-flop passes to AND gate 23b which conducts when a "write back" signal occurs and passes a signal to the exclusive-OR gates 9 causing the word read from the store and held in register 14 to be written back in inverted form. The signal from the AND gate 23b is fed to the store in a marker bit location to indicate that the contents of the associated word location are in inverted form. The combination of the inverted erroneous word and a consistently defective storage location result in the complement of the word without errors being read out. The inverted word in the store may be checked using the same procedure, an error causing a "stop" signal to be passed to an associated data processing system 18 instead of another inversion being made. On read out the marker bit is read into stage 14d of the output register and is applied to gate 23a causing a signal to be passed to the exclusive-OR gates 9 which invert the word as it is read out and before it passes to the associated data processor 18.