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GB1197418A - Data Storage Apparatus - Google Patents

Data Storage Apparatus

Info

Publication number
GB1197418A
GB1197418A GB611469A GB611469A GB1197418A GB 1197418 A GB1197418 A GB 1197418A GB 611469 A GB611469 A GB 611469A GB 611469 A GB611469 A GB 611469A GB 1197418 A GB1197418 A GB 1197418A
Authority
GB
United Kingdom
Prior art keywords
data
word
bits
byte
store portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB611469A
Inventor
Philip Charles Austin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to GB611469A priority Critical patent/GB1197418A/en
Priority to FR7001685A priority patent/FR2031150A5/fr
Priority to JP45009033A priority patent/JPS4936331B1/ja
Priority to DE19702004934 priority patent/DE2004934B2/en
Publication of GB1197418A publication Critical patent/GB1197418A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

1,197,418. Data storage. INTERNATIONAL BUSINESS MACHINES CORP. 5 Feb., 1969. No. 6114/69. Heading G4C. Data storage apparatus has a first store portion storing words of m1 data bits and n1 error correction code bits and a second store portion storing words of m2 data bits and n2 error correction code bits, where m1 > m2 and n1 # n2, and means for correcting an error or a predetermined number of errors in the data bits of an accessed word. Each store portion has a plurality of integratedcircuit storage modules, each module storing a corresponding bit (or bits) of each word in the portion. A common address register selects a store portion (of which there may be more than two) and a word in it, the word being placed in a register, a data byte or bytes of the word being gated, with correction by bit inversion under control of the error correction code bits, to an output bus, the byte or bytes being selected by the address register. Gating to the bus may precede completion of the error checking in which case the uncorrected data sent is ignored if correction is necessary, the corrected data being sent after a delay. A parity bit is generated to accompany each byte on the bus.
GB611469A 1969-02-05 1969-02-05 Data Storage Apparatus Expired GB1197418A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB611469A GB1197418A (en) 1969-02-05 1969-02-05 Data Storage Apparatus
FR7001685A FR2031150A5 (en) 1969-02-05 1970-01-16
JP45009033A JPS4936331B1 (en) 1969-02-05 1970-02-03
DE19702004934 DE2004934B2 (en) 1969-02-05 1970-02-04 MEMORY ARRANGEMENT WITH CIRCUITS FOR ERROR DETECTION AND ERROR CORRECTION

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB611469A GB1197418A (en) 1969-02-05 1969-02-05 Data Storage Apparatus

Publications (1)

Publication Number Publication Date
GB1197418A true GB1197418A (en) 1970-07-01

Family

ID=9808641

Family Applications (1)

Application Number Title Priority Date Filing Date
GB611469A Expired GB1197418A (en) 1969-02-05 1969-02-05 Data Storage Apparatus

Country Status (4)

Country Link
JP (1) JPS4936331B1 (en)
DE (1) DE2004934B2 (en)
FR (1) FR2031150A5 (en)
GB (1) GB1197418A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0099620A2 (en) * 1982-04-21 1984-02-01 Digital Equipment Corporation Memory controller with data rotation arrangement
EP0242595A2 (en) * 1986-04-25 1987-10-28 International Business Machines Corporation Error detection using variable field parity checking
EP0517406A2 (en) * 1991-06-06 1992-12-09 International Business Machines Corporation Computer system for enabling a choice of errordetection technologies

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3814922A (en) * 1972-12-01 1974-06-04 Honeywell Inf Systems Availability and diagnostic apparatus for memory modules
US3800294A (en) * 1973-06-13 1974-03-26 Ibm System for improving the reliability of systems using dirty memories
US4183096A (en) * 1978-05-25 1980-01-08 Bell Telephone Laboratories, Incorporated Self checking dynamic memory system
US4223382A (en) * 1978-11-30 1980-09-16 Sperry Corporation Closed loop error correct

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0099620A2 (en) * 1982-04-21 1984-02-01 Digital Equipment Corporation Memory controller with data rotation arrangement
EP0099620A3 (en) * 1982-04-21 1986-01-22 Digital Equipment Corporation Memory controller with data rotation arrangement
EP0242595A2 (en) * 1986-04-25 1987-10-28 International Business Machines Corporation Error detection using variable field parity checking
EP0242595A3 (en) * 1986-04-25 1990-04-18 International Business Machines Corporation Error detection using variable field parity checking
EP0517406A2 (en) * 1991-06-06 1992-12-09 International Business Machines Corporation Computer system for enabling a choice of errordetection technologies
EP0517406A3 (en) * 1991-06-06 1993-09-01 International Business Machines Corporation Computer system for enabling a choice of errordetection technologies

Also Published As

Publication number Publication date
JPS4936331B1 (en) 1974-09-30
DE2004934A1 (en) 1970-08-20
FR2031150A5 (en) 1970-11-13
DE2004934B2 (en) 1977-08-25

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee