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FR3121548B1 - Procede de preparation d’un substrat avance, notamment pour des applications photoniques - Google Patents

Procede de preparation d’un substrat avance, notamment pour des applications photoniques Download PDF

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Publication number
FR3121548B1
FR3121548B1 FR2103274A FR2103274A FR3121548B1 FR 3121548 B1 FR3121548 B1 FR 3121548B1 FR 2103274 A FR2103274 A FR 2103274A FR 2103274 A FR2103274 A FR 2103274A FR 3121548 B1 FR3121548 B1 FR 3121548B1
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FR
France
Prior art keywords
preparing
base substrate
dielectric layer
layer
photonic applications
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR2103274A
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English (en)
Other versions
FR3121548A1 (fr
Inventor
Ludovic Ecarnot
Aymen Ghorbel
Marcel Broekaart
Daniel Delprat
Severin Rouchier
Stephane Thieffry
Carine Duret
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR2103274A priority Critical patent/FR3121548B1/fr
Application filed by Soitec SA filed Critical Soitec SA
Priority to EP21740160.3A priority patent/EP4189734B1/fr
Priority to CN202180048518.0A priority patent/CN115777139A/zh
Priority to PCT/FR2021/051140 priority patent/WO2022023630A1/fr
Priority to KR1020227041969A priority patent/KR20230042215A/ko
Priority to US18/007,145 priority patent/US20230230874A1/en
Priority to JP2023501665A priority patent/JP2023535319A/ja
Priority to TW110126926A priority patent/TWI796735B/zh
Publication of FR3121548A1 publication Critical patent/FR3121548A1/fr
Application granted granted Critical
Publication of FR3121548B1 publication Critical patent/FR3121548B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physical Vapour Deposition (AREA)
  • Optical Integrated Circuits (AREA)

Abstract

L’invention porte sur un procédé de préparation d’un substrat support (1) comprenant les étapes suivantes : fournir un substrat de base (3) comportant :+ une couche de piégeage de charges (2) disposée sur une face principale (31) du substrat de base (3) ; et+ une couche de compensation de courbure (32) disposée sur une face arrière (33) du substrat de base (3), la face arrière (33) étant opposée à la face principale (31) ;former une couche diélectrique (4) sur la couche de piégeage de charges (2), la formation de la couche diélectrique (4) mettant simultanément en œuvre le dépôt et la pulvérisation ionique de la couche diélectrique. ( Figure 4 )
FR2103274A 2020-07-28 2021-03-30 Procede de preparation d’un substrat avance, notamment pour des applications photoniques Active FR3121548B1 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FR2103274A FR3121548B1 (fr) 2021-03-30 2021-03-30 Procede de preparation d’un substrat avance, notamment pour des applications photoniques
CN202180048518.0A CN115777139A (zh) 2020-07-28 2021-06-23 将薄层转移到设有电荷俘获层的载体衬底的方法
PCT/FR2021/051140 WO2022023630A1 (fr) 2020-07-28 2021-06-23 Procede de report d'une couche mince sur un substrat support muni d'une couche de piegeage de charges
KR1020227041969A KR20230042215A (ko) 2020-07-28 2021-06-23 전하 트래핑 층을 구비한 캐리어 기판에 박층을 전사하는 공정
EP21740160.3A EP4189734B1 (fr) 2020-07-28 2021-06-23 Procede de report d'une couche mince sur un substrat support muni d'une couche de piegeage de charges
US18/007,145 US20230230874A1 (en) 2020-07-28 2021-06-23 Method for transferring a thin layer onto a support substrate provided with a charge-trapping layer
JP2023501665A JP2023535319A (ja) 2020-07-28 2021-06-23 電荷トラップ層が設けられたキャリア基板に薄層を転写するプロセス
TW110126926A TWI796735B (zh) 2020-07-28 2021-07-22 將薄層轉移到提供有電荷捕捉層的載體基板之方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2103274 2021-03-30
FR2103274A FR3121548B1 (fr) 2021-03-30 2021-03-30 Procede de preparation d’un substrat avance, notamment pour des applications photoniques

Publications (2)

Publication Number Publication Date
FR3121548A1 FR3121548A1 (fr) 2022-10-07
FR3121548B1 true FR3121548B1 (fr) 2024-02-16

Family

ID=78332818

Family Applications (1)

Application Number Title Priority Date Filing Date
FR2103274A Active FR3121548B1 (fr) 2020-07-28 2021-03-30 Procede de preparation d’un substrat avance, notamment pour des applications photoniques

Country Status (1)

Country Link
FR (1) FR3121548B1 (fr)

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100701341B1 (ko) 1999-03-16 2007-03-29 신에쯔 한도타이 가부시키가이샤 실리콘 웨이퍼의 제조방법 및 실리콘 웨이퍼
FR2838865B1 (fr) 2002-04-23 2005-10-14 Soitec Silicon On Insulator Procede de fabrication d'un substrat avec couche utile sur support de resistivite elevee
FR2860341B1 (fr) 2003-09-26 2005-12-30 Soitec Silicon On Insulator Procede de fabrication de structure multicouche a pertes diminuees
JP2006114847A (ja) * 2004-10-18 2006-04-27 Sony Corp 半導体装置、及び貼り合わせ基板の製造方法
FR2933233B1 (fr) 2008-06-30 2010-11-26 Soitec Silicon On Insulator Substrat de haute resistivite bon marche et procede de fabrication associe
FR2953640B1 (fr) 2009-12-04 2012-02-10 S O I Tec Silicon On Insulator Tech Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante
US9768056B2 (en) 2013-10-31 2017-09-19 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition
EP3221884B1 (fr) * 2014-11-18 2022-06-01 GlobalWafers Co., Ltd. Plaquettes de semi-conducteur sur isolant à haute résistivité comprenant couches de piégeage de charges et son procédé de fabrication.
US9978582B2 (en) * 2015-12-16 2018-05-22 Ostendo Technologies, Inc. Methods for improving wafer planarity and bonded wafer assemblies made from the methods
WO2020008116A1 (fr) 2018-07-05 2020-01-09 Soitec Substrat pour un dispositif integre radioafrequence et son procede de fabrication

Also Published As

Publication number Publication date
FR3121548A1 (fr) 2022-10-07

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