FR3076067B1 - Procede de fabrication de composite a couche mince ultra-plane - Google Patents
Procede de fabrication de composite a couche mince ultra-plane Download PDFInfo
- Publication number
- FR3076067B1 FR3076067B1 FR1762805A FR1762805A FR3076067B1 FR 3076067 B1 FR3076067 B1 FR 3076067B1 FR 1762805 A FR1762805 A FR 1762805A FR 1762805 A FR1762805 A FR 1762805A FR 3076067 B1 FR3076067 B1 FR 3076067B1
- Authority
- FR
- France
- Prior art keywords
- substrate
- ultra
- thin film
- film composite
- manufacturing ultra
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000002131 composite material Substances 0.000 title abstract 2
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 239000010409 thin film Substances 0.000 title abstract 2
- 238000000034 method Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 abstract 7
- 230000008030 elimination Effects 0.000 abstract 1
- 238000003379 elimination reaction Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
- Micromachines (AREA)
- Laminated Bodies (AREA)
Abstract
Un procédé de fabrication d'un composite à couche mince comprend les étapes suivantes : a) fourniture d'un premier substrat (14) et d'un substrat de référence (10) ayant une face ultra-plane (12) ; b) collage du premier substrat (14) sur la face ultra-plane (12) du substrat de référence (10) ; c) amincissement du premier substrat (14) jusqu'à une épaisseur submillimétrique prédéterminée de sorte à former une face ultra-plane amincie (17) ; d) collage d'un substrat support (18) sur la face ultra-plane amincie (17) ; e) élimination du substrat de référence (10).
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1762805A FR3076067B1 (fr) | 2017-12-21 | 2017-12-21 | Procede de fabrication de composite a couche mince ultra-plane |
PCT/EP2018/085799 WO2019121886A1 (fr) | 2017-12-21 | 2018-12-19 | Procédé de fabrication de composite à couche mince ultra-plane |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1762805 | 2017-12-21 | ||
FR1762805A FR3076067B1 (fr) | 2017-12-21 | 2017-12-21 | Procede de fabrication de composite a couche mince ultra-plane |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3076067A1 FR3076067A1 (fr) | 2019-06-28 |
FR3076067B1 true FR3076067B1 (fr) | 2020-01-10 |
Family
ID=62222759
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1762805A Expired - Fee Related FR3076067B1 (fr) | 2017-12-21 | 2017-12-21 | Procede de fabrication de composite a couche mince ultra-plane |
Country Status (2)
Country | Link |
---|---|
FR (1) | FR3076067B1 (fr) |
WO (1) | WO2019121886A1 (fr) |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3921885A (en) | 1973-06-28 | 1975-11-25 | Rca Corp | Method of bonding two bodies together |
US20020187595A1 (en) * | 1999-08-04 | 2002-12-12 | Silicon Evolution, Inc. | Methods for silicon-on-insulator (SOI) manufacturing with improved control and site thickness variations and improved bonding interface quality |
JP2003531492A (ja) | 2000-04-14 | 2003-10-21 | エス オー イ テク シリコン オン インシュレータ テクノロジース | 特に半導体材料製の基板又はインゴットから少なくとも一枚の薄層を切り出す方法 |
FR2995136B1 (fr) * | 2012-09-04 | 2015-06-26 | Soitec Silicon On Insulator | Pseudo-substrat avec efficacite amelioree d'utilisation d'un materiau monocristallin |
US9136337B2 (en) * | 2012-10-12 | 2015-09-15 | Sumitomo Electric Industries, Ltd. | Group III nitride composite substrate and method for manufacturing the same, laminated group III nitride composite substrate, and group III nitride semiconductor device and method for manufacturing the same |
FR3027250B1 (fr) * | 2014-10-17 | 2019-05-03 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de collage direct via des couches metalliques peu rugueuses |
-
2017
- 2017-12-21 FR FR1762805A patent/FR3076067B1/fr not_active Expired - Fee Related
-
2018
- 2018-12-19 WO PCT/EP2018/085799 patent/WO2019121886A1/fr active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO2019121886A1 (fr) | 2019-06-27 |
FR3076067A1 (fr) | 2019-06-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PLFP | Fee payment |
Year of fee payment: 2 |
|
PLSC | Search report ready |
Effective date: 20190628 |
|
PLFP | Fee payment |
Year of fee payment: 3 |
|
ST | Notification of lapse |
Effective date: 20210806 |