FR2631743A1 - STRUCTURE WITH NON-COPLANAR ELECTRODES FOR LIQUID CRYSTAL MATRIX DISPLAY WITH AMORPHOUS SILICON THIN FILM TRANSISTORS AND MANUFACTURING METHOD - Google Patents

Abstract

To dielectrically and chemically isolate gate electrodes and pixel electrodes in matrix liquid crystal display devices in large area flat panels, these two separate electrodes are arranged in a non-coplanar arrangement. In particular, the present invention contemplates the use of a layer of silicon nitride 14 disposed above grid electrode structures 12 and simultaneously supporting transparent pixel electrode structures 20 in different layers so as to ensure the desired degree of isolation which positively affects the performance of the device and improves light blocking by the use of aluminum as the desirable gate electrode material.

Description

STRUCTURE WITH NON-COPLANAR ELECTRODES FOR MATRIX DISPLAY

  LIQUID CRYSTALS WITH SILICON THIN FILM TRANSISTORS

AMORPHOUS AND MANUFACTURING METHOD

  The present invention relates generally to structures of field effect transistors and pixel electrodes (picture elements) for use in liquid crystal display (LCD) devices. The present invention also relates to methods of manufacturing such devices and structures. More particularly, the present invention relates to a structure and a method in which a gate electrode, a pixel electrode and source and / or drain contact electrodes are arranged in a non-coplanar arrangement so as to be effectively isolated. each other. Even more specifically, the present invention provides a structure in which all the electrodes are non-coplanar, thereby eliminating short-circuit problems which limit the efficiency and which exist all

  particularly between the gate and pixel electrodes.

  In a matrix-addressed liquid crystal display, a plurality of pixel elements are individually controlled by electronic switching elements disposed near at least one pixel electrode. The application of a voltage signal to the pixel electrode via the electronic switching device causes changes in physical and optical properties in liquid crystal materials which are arranged above or below the pixel electrode. Typically, the pixel electrodes are made of an electrically transparent conductive material. Thus, optical changes in the liquid crystals lead to the display of images on a screen which includes a network

  pixel elements and associated switching devices.

  Thus, by controlling the switching devices, images (of text and graphics) may be caused to appear on the screen. Matrix-addressed liquid crystal displays are a particularly good replacement for cathode ray tube devices in many applications. In view of the speed and control of the displayed information, it is desirable to use a matrix addressed system in which each pixel element is individually controllable. In addition, to ensure image resolution pleasing to the human eye, it is necessary to use a large number of pixel elements arranged very close to each other, typically currently at distances

  from about 50 to 150 pixels per linear inch (2.5 centimeters).

  While matrix-addressed liquid crystal displays have been used successfully to replace cathode ray tubes (CRTs) in small pocket TV systems and the like, it is nevertheless very desirable to be able to form liquid crystal display with a large display area which not only ensures high resolution and color presentation if desired but also provides very fast image processing to prevent blinking and to be able to adapt to the information rate of the signals in the bands

of TV.

  However, for the production of display devices with flat panels, in particular those of the matrix-controlled type, the problems of manufacturing efficiency severely limit the screen size which can be produced economically. In particular, it will be noted that the yield of

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  manufacturing is inversely proportional to the square of the probability of occurrence of a defect in a given row or column of the display. Thus, performance limitations are a notable factor for the production of liquid crystal display devices in large, high resolution flat panels. To manufacture these displays, processing steps dependent on several materials must be used. In particular, manufacturing often requires etching or shaping of a type of material below which there is a material of different composition but which must not be sensitive to the etching of the upper layer. In addition, etching operations on a part of the structure must not affect other structures present during the etching or removal operations. This is often difficult to achieve for desirable materials. For example, some materials that are useful in etching electrode materials

  grid tend to degrade the pixel electrode material.

  Thus, the manufacturing processes for matrix-addressed liquid crystal displays depend very much on the materials, the processing steps and the order of the processing steps. However, there is still a desire to manufacture large flat panel displays despite the performance problems associated with the screen size and the compatibility of the materials. In addition, one of the notable problems which can arise and which can have a noticeable detrimental influence on the yield is the existence of short circuits or leakage paths between the material of the pixel electrodes and the patterns of grid electrodes. and grid bus. The inventors have observed the repeated appearance of defects which occur in the

  grid or pixel engraving areas where short-

  circuits between electrodes limiting efficiency. Thus, it is seen that it is desirable to be able to electrically insulate the gate and pixel electrode materials as much as possible to thereby eliminate the problem of short circuits or paths

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  which limit the efficiency and more particularly to allow the choice of the grid electrode material from a greater range of materials. These two problems are solved according to the present invention. More particularly, the gate electrode is always covered with an insulating layer which protects it from subsequent processing chemicals. This allows for a wider choice of grid materials which

  do not interact with the processing of the pixel electrode.

  In addition, this provides dielectric isolation for

  eliminate short circuits between electrodes.

  According to a particular embodiment of the present invention, a structure of field effect transistors and pixel electrodes intended for use in a liquid crystal display device incorporates a layer of insulating material such as silicon nitride or silicon oxide which is disposed above the gate electrode so as to electrically isolate it from the material of the pixel electrode disposed in the vicinity of the field effect transistor. Thus, according to the present invention, the gate electrode and the pixel electrode are arranged in a non-coplanar arrangement. This preserves the dielectric isolation between the material of the gate electrode and the material of the pixel electrode, not only in the vicinity of the transistor switching element but also

  all over the display substrate.

  In addition, the present invention also provides a method of fabricating field effect transistor structures and display electrodes for use in liquid crystal display devices. According to this method, a gate electrode is first placed on an insulating substrate and, above, is placed a layer of insulating material such as silicon nitride. An island or mesa structure, incorporating layers of amorphous silicon, doped amorphous silicon and molybdenum, is formed on the gate electrode. Then, a configuration of transparent pixel electrode material such as indium tin oxide is disposed on the insulating material in the vicinity of the structure of the island. This provision

  is carried out by lifting procedures (lift-

  off) which will be described more particularly below. A layer of source and / or drain contact material is then placed on the structure and shaped so as to form a field effect transistor, one of the electrodes of which is preferably in

  contact with the adjacent pixel electrode.

  It is therefore an object of the present invention to provide a process for manufacturing doped amorphous silicon field effect transistors which results in the production of a structure.

  specific non-coplanar electrodes.

  More particularly, an object of the present invention is to provide a structure which isolates the gate electrode from the subsequent steps of manufacturing a transistor by providing a continuous insulating layer, such as a layer of silicon nitride, au- above the gate electrode but below the

pixel electrode material.

  Another object of the present invention is to provide a method which allows a wide selection of gate electrode materials to be used without producing incompatibility problems.

  associated with subsequent processing steps.

  Another object of the present invention is to allow the use of aluminum as a gate material rather than titanium since aluminum has better light blocking capabilities for the channel region and a line conductance of higher scanning in applications at

liquid crystal displays.

  Another object of the present invention is to provide gate electrode materials which have conductivities

higher electrical loads.

  Another object of the present invention is to eliminate

  short circuits between gate and pixel electrodes.

  Finally, but without this constituting a limitation, another object of the invention is to provide manufacturing methods and structures which are particularly suitable for the manufacture of liquid crystal display devices.

  matrixed in flat large area panels.

  These and other objects, features and advantages of the present invention will be discussed in more detail.

  in the following description of particular embodiments

  made in relation to the appended figures among which: FIG. 1 is a sectional view illustrating an initial step of the method according to the present invention and very particularly representing the formation of a gate electrode; Figure 2 is a sectional view similar to Figure 1 but more particularly showing the arrangement of a dielectric layer above the gate electrode and the substrate; Figure 3 is a sectional view similar to Figure 2 but showing more particularly the deposition of amorphous silicon, doped amorphous silicon and a metal electrode contact layer; Figure 4 is a sectional view similar to Figure 3 but illustrating more particularly the conformation of the three upper layers to form an island or a mesa structure covering the gate electrode; Figure 5 is a sectional view similar to Figure 4 but more particularly showing the result of the formation of an adjacent pixel electrode; Figure 6 is a sectional view similar to Figure 5 but more particularly showing the deposition of a source and / or drain contact electrode material at a higher level; Figure 7 is a sectional view similar to Figure 6 but more particularly illustrating the configuration of the higher level metallization to form a field effect transistor connected to an adjacent pixel electrode; and Figure 8 is a sectional view similar to Figure 7 but illustrating more particularly the application of a level

  upper passivation material.

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  The figures provide a sequential illustration of the steps of the method implemented according to the present invention. In particular, it should be noted that the steps provided and the resulting structure provide significant dielectric isolation between the gate electrode and the pixel electrode. This isolation and the isolation between the various stages provided with respect to the gate electrode allows the use of a wide variety of materials as the gate electrode. In particular, it can be seen that aluminum as the gate electrode material provides significant advantages. In particular, it can be seen that the light transmission through a titanium grid having a thickness of 800 angstroms at a wavelength of 0.56 micrometers is 0.041% while the transmission through aluminum in the same conditions is only 1.02 x 10-5% which improves the light-blocking capacity of the aluminum grilles by a factor of about 4,000. In addition, the electrical conductance in the bulk of the aluminum is about 20 times that of titanium. So we see that processes and structures that allow the use of aluminum as a material

  grid electrode has significant advantages.

  Referring very particularly to FIG. 1, it can be seen that the gate electrode 12 is arranged on an insulating substrate 10. The material of the substrate is preferably transparent glass. However, ceramics and other compatible materials can also be used, the main requirement

  for the substrate 10 being its electrically insulating nature.

  The gate electrode 12 is preferably aluminum.

  However, other conductive materials such as tungsten,

  gold, chromium and titanium can also be used.

  The gate electrode 12 is preferably formed by evaporation and then shaped and etched to form the gates of the individual transistors and also to form gate bus lines in the display. The result of this deposit and this conformation

is shown in figure 1.

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  Next, a layer of an insulating material 14 is deposited as shown in FIG. 2. The layer 14 preferably comprises silicon nitride. It is the existence of the insulating layer 14 which ensures the dielectric isolation and the desired processing isolation of the gate electrode 12. It will be noted that, while the insulating material 14 preferably comprises silicon nitride, it is also possible to use silicon oxide as long as suitable etching products are used to shape upper layer structures. The layer of insulating material 14 preferably has a thickness of between 300 and 3000 angstrms. For a grid thickness of approximately 800 angstrms, the insulating layer 14 will have a thickness of approximately 1500 angstroms. Generally, the grid thickness and the thickness of the insulating layer 14 are associated so that the insulating layer is preferably twice as thick as the grid electrode layer, at least in the first order. In any case, the layer 14 must not be too thin so that the electric field does not exceed 105 volts / cm. The insulating layer 14 is preferably deposited by chemical vapor deposition

plasma assisted.

  Next, an amorphous silicon layer 16 and an N + type doped amorphous silicon layer are deposited by plasma-assisted chemical vapor deposition to a combined thickness of about 500 angstroms, after which a layer with a thickness of 1000 angstrms of a conductive material 18 is deposited as shown in Figure 3. The layer 18 is preferably made of molybdenum. The molybdenum layer serves two purposes in this process. Firstly, it increases the reliability of the source / drain contact and secondly it acts as a mask for the subsequent conformation of the islet or of the mesa structure illustrated in FIG. 4. More particularly, the structure illustrated in FIG. 3 can be shaped by masking and etching using a potassium hydroxide solution or by an appropriate reactive ion etching process. These etching products attack layer 18, the amorphous silicon layer 17

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  and the intrinsic amorphous silicon layers 16 and 17, but do not affect the underlying layer of insulating material 14 which is preferably made of silicon nitride. In addition, it can be seen from FIG. 4 that after etching the layers of amorphous silicon 16 and 17 with potassium hydroxide, the layer of molybdenum 18 is preferably etched from the edge of the island

  or mesa, thus providing the structure illustrated in Figure 4.

  This last engraving is carried out with a mask similar to that used in connection with the formation of the mesa but in which slightly smaller islet patterns are defined. It is thus seen that the potassium hydroxide does not attack the layer 18 but attacks the silicon layers 16 and 17. The layer 18 acts as a mask to etch the island structure and is then reconfigured and etched to provide the structure illustrated in Figure 4. It will be noted in particular at this stage of the process that a non-coplanar basic structure has been formed using selective etching which attacks only the silicon, leaving the

  protective insulating layer 14 on the gate electrode 12.

  In the next step, a layer of transparent pixel electrode material 20 is formed as shown in FIG. 5. The pixel electrode 20 preferably comprises indium tin oxide (ITO) . It is however possible to use tin oxide although indium is preferred as a stabilizing element. Note that it is also possible to use titanium oxide as the transparent pixel electrode material. However, indium tin oxide is preferred. It will be noted that the conventional deposition and photolithography methods are not adaptable to the formation of the pixel electrode 20. In particular, etching products such as nitric oxide which are usually used to conform oxide d Indium and tin would unfortunately also attack the molybdenum coating 18. Thus, other methods of forming the pixel electrode elements 20 are provided. In particular, according to the present invention, a removal off process (lift off) is used. According to this process, a photosensitive material is deposited. A negative mask is then used to form an image on the photosensitive product so as to leave openings in the photosensitive product where it is desired to form the pixel electrode material. After depositing the ITO, the remaining photosensitive material is rinsed off, thereby taking with it any indium tin oxide which may have been deposited in areas other than the desired openings. A photosensitive product suitable for this purpose is the positive resin KTI 1470 or AZ1450J. Rinsing with a suitable photosensitive solvent includes soaking in chlorobenzene

  to form a clear profile of photosensitive product for the lift-

  off. The structure resulting from this lift-off process is

illustrated in figure 5.

  Then, a source and / or drain contact material 22 is deposited on the part to be treated. The result is shown in FIG. 6. The conductive layer 22 is shaped so as to form contacts on the resulting transistor structure. In addition, the conformation of the layer 22 also results in the formation of an electrical contact 22b connecting one side of the

  resulting field effect transistor at pixel electrode 20.

  The other part of the layer 22 is shaped so as to provide a contact 22a on the other side of the structure of the field effect transistor, as shown in FIG. 7. It will further be noted that the layer 18 previously formed essentially merges with layer 22 when these two layers comprise molybdenum, as is preferred here. It will also be noted that, to form the desired field effect transistor structure, the etching carried out on the structure shown in FIG. 6 must also include an etching of the doped amorphous silicon layer 17 so as to divide it into two parts, as shown in FIG. 7. Finally, a layer of passivation material, preferably silicon nitride-.24, is deposited on top of the entire wafer to be treated, thus providing the structure shown in FIG. 8. While

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  it is preferred to use silicon nitride as passivation material in the context of the present invention, it is also possible to use doped glasses or organic materials for this purpose. In particular, as passivation layers comprising glasses, it is particularly preferred that the passivation layer is formed by a process of chemical vapor deposition at low temperature assisted by plasma which does not act at temperatures high enough to cause a degradation of the structure and

amorphous silicon material.

  By more particularly considering some of the material compatibility problems mentioned here, it will be noted that molybdenum is a preferred source and drain contact material because it involves much simpler treatment steps. However, if practitioners wish to accept steps which are more particularly designed to mask a layer of indium-tin oxide during the conformation of the source / drain contact material, it is then possible to use other conductors as source / drain metallization contacts 22a and 22b. In particular, it is known that it is undesirable to carry out wet etching of aluminum and to expose the ITO material of the pixel electrode to wet etching. Note, however, that a digging process as described in United States Patent Application No. 104,452 filed October 5, 1987 and assigned to the Applicant, entitled "Array Proccess for a- Si FET With Protective Tab and DIG Structure "allows the use of aluminum sources and drains subject to a more complex treatment. Furthermore, with regard to the information of the pixel electrode by conformation of the indium tin oxide material, it is known that there would be a high risk of contamination in the region around the island. by a conductive material, thus adversely affecting the characteristics

of the device.

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  From the above, it should be noted that the process according to the present invention allows the easy fabrication of transistor structures and pixel electrodes which are particularly suitable for use in liquid crystal display devices in flat panels. large area. More particularly it is seen that the resulting process and structure provide significant dielectric and chemical treatment isolation between the gate electrode and pixel electrode materials. It can also be seen that the present invention notably increases the number of different materials which can be used as grid electrode materials and thus improves the overall characteristics of the display, in particular as regards the blocking functions of the light. We also see that the

  The present invention satisfies all of the above objects.

  While the present invention has been described in detail here in relation to some of its particular embodiments, many modifications and variations may

  be performed by those skilled in the art.

Claims (10)

BRIEFINGS   I. Structure of field effect transistors and pixel electrodes for use in liquid crystal display devices, characterized in that it comprises: a gate electrode (12) on an insulating substrate (10 ); a layer of insulating material (14) deposited over the gate electrode and the substrate; an amorphous silicon island (16) arranged on the insulating material so as to be above the electrode wire rack; -   an element of transparent conductive material (20) disposed on the insulating material in the vicinity of the amorphous silicon island (16); a layer of doped amorphous silicon (17) disposed on the island of amorphous silicon, this layer of doped amorphous silicon comprising a vacuum, this vacuum being disposed above the gate electrode, this vacuum also being arranged so as to dividing the doped amorphous silicon layer into two separate parts; a first electrode (22a) disposed on a first of the two parts of doped amorphous silicon; and a second electrode (22b) disposed on the second of the doped amorphous silicon parts, this second electrode also being arranged to be in contact with the conductive layer transparent.   2. Structure according to claim 1, characterized in that the insulating material (14) is chosen from the group   comprising silicon nitride and silicon oxide.   3. Structure according to claim 1, characterized in that the insulating substrate (10) comprises a material chosen from   the group comprising glass and ceramics. 263 1,743   4. Structure according to claim 1, characterized in that the gate electrode (12) comprises a material chosen from the group comprising aluminum, titanium, gold, chromium and tungsten. 5. Structure according to claim 1, characterized in that the transparent conductive material (20) comprises a material chosen from the group comprising indium oxide and   tin, tin oxide and titanium oxide.   6. Method for manufacturing structures of field effect transistors and pixel electrodes intended for use in liquid crystal display devices, characterized in that it comprises the following steps: depositing a gate electrode (12) on an insulating substrate (10); placing a layer of insulating material (14) on the gate electrode and the substrate; placing a layer of amorphous silicon (16), doped amorphous silicon (17) and a conductive material (18), respectively, on the insulating material; conforming the layers of conductive material, doped amorphous silicon and amorphous silicon so as to form an island structure above the gate electrode; placing an element (20) of transparent conductive material on the insulating material adjacent to the island;   placing a layer of conductive material (22) over   above the island, transparent conductive material and insulating material; and conforming the conductive material and the doped amorphous silicon to form a pair of contacts (22a, 22b) on the island, these contacts thus being arranged on two separate parts of the layer of doped amorphous silicon which also include a vacuum covering the gate electrode, one of the contacts being   electrical contact with the transparent conductive element.   7. Method according to claim 6, characterized in that the insulating material is chosen from the group comprising:   silicon nitride and silicon oxide.   8. Method according to claim 6, characterized in that the insulating substrate comprises a material chosen from the group   including glass and ceramic.   9. Method according to claim 6, characterized in that the gate electrode comprises a material chosen from the group comprising aluminum, titanium, gold, chromium and tungsten.   10. Method according to claim 6, characterized in that the transparent conductive material comprises a material chosen from the group comprising indium tin oxide, oxide of tin and titanium oxide.