FR2624673A1 - Digitally controlled oscillator, using a switchable element, application to the production of devices for recovering the tempo and phase of a digital signal - Google Patents

Abstract

The oscillator comprises a circuit with oscillating loop, an electrical element 20 which is inserted into the circuit and whose presence modifies the frequency of the oscillator, and analog switching means 22 provided in order to switch this element 20, thus enabling the frequency of the oscillator to take one or the other of two values Fmax and Fmin. The switching means are controlled by a binary digital input signal DC which enables the oscillator to deliver a signal whose average frequency depends on the density of the 1 logic states with respect to the 0 logic states of the input signal.

Description

NUMERICALLY CONTROLLED OSCILLATOR USING ELEMENT
SWITCHABLE, APPLICATION TO THE PRODUCTION OF DEVICES
RECOVERY OF THE RHYTHM AND PHASE OF A DIGITAL SIGNAL
DESCRIPTION
The present invention relates to a numerically controlled oscillator using a switchable element. It applies in particular to the production of devices for the recovery of the rhythm and the phase of a digital signal.

 Oscillators known as "voltage controlled oscillators" (VCO) are already known, and in particular crystal voltage controlled oscillators (VCXO). Such oscillators, controlled by an analog voltage, make it possible to produce analog type phase-locked loops, which are very stable and can have very little residual jitter.

 However, these oscillators require the use of diodes called "varicap diodes" or even "varactor" diodes, the integration of which is very delicate. The integration, and in particular the very large-scale integration (VLSI), of oscillators of the VCO or VCXO type, and consequently of phase-locked loops using such oscillators, is thus difficult.

 There are also known quartz oscillators of fixed frequency (not adjustable) which are used in digital type phase locked loops. These fixed frequency oscillators and digital type phase locked loops are easy to integrate.

 However, the frequency limitation (not adjustable) of the quartz oscillators used means that the digital loops which incorporate them have a non-negligible residual phase jitter, which can be very annoying in some applications, such as bidirectional digital transmission. echo cancellation, for example for the Digital Network for Service Integration (ISDN-or ISDN according to English terminology).

 The present invention relates to a variable frequency oscillator whose integration is easy and which, in a preferred embodiment, makes it possible to produce phase locked loops of low residual jitter.

 For this purpose, the oscillator of the invention uses a switchable element whose switching is controlled. by a digital signal with two logic states 0 or 1.

 This makes it possible to design certain devices for recovering the rhythm and the phase of a digital signal, using an oscillator according to the invention, in which one can store the phase error information received and therefore store the frequency (å a possible multiplying factor) of the digital signal received. It is also possible to envisage an application of the oscillator which is the subject of the invention, according to which means are associated with this oscillator making it possible to transform a control signal from a conventional VCO type oscillator into a binary sequence intended to control the oscillator. subject of the invention.

Specifically, the present invention relates to an oscillator comprising an oscillating loop circuit, characterized in that it further comprises
- an electrical element which is interposed in the circuit and whose presence modifies the frequency of the oscillator, and
- analog switching means provided for switching this element, thus allowing the frequency of the oscillator to take One or the other of two values Fmax and
Fmin, and in that said switching means are controlled by a signal. binary digital input that allows the oscillator to provide a signal whose average frequency is a function of the density of logic states 1 compared to logic states O of the input signal.

 Preferably, said element is a capacity, an element that can be easily integrated.

 In a particular embodiment of the invention, said circuit comprising another capacity, said capacity is mounted in parallel with this other capacity and the switching means are provided for interrupting or re-establishing, as a function of the signal of input, the connection in parallel capacities.

 In the oscillator which is the subject of the invention, a switchable element is thus used and any diode of the varicap type is freed, which makes it possible to produce an oscillator in accordance with the invention which can be easily integrated.

 According to a particular embodiment of the oscillator which is the subject of the invention, the switching means comprise a field effect transistor which is mounted as a switch.

 According to a preferred embodiment of the oscillator object of the invention, the oscillating loop circuit comprises a piezoelectric element.

 There is thus a piezoelectric type oscillator which allows the production of phase locked loops having only a small residual jitter, as will be seen more clearly below.

 In a particular application of the oscillator which is the subject of the invention, this oscillator can be preceded by a shift register in which a binary sequence is capable of being stored and the output of which can be linked to the input of said oscillator. register and control said switching means.

 In another particular application, the oscillator which is the subject of the invention can be preceded by a delta sigma digital converter capable of being controlled by a binary word and capable of translating this binary word into a binary sequence intended to control said switching means. .

 In another particular application, the oscillator which is the subject of the invention is preceded by an analog-to-digital delta sigma converter which receives an analog voltage at input and which is capable of converting this analog voltage into a binary sequence, and said switching means are controlled by this binary sequence.

The present invention also relates to a device for recovering the rhythm and phase of a digital signal received, this device being designed to supply a clock signal and comprising
electronic means for processing the digital signal received, capable of extracting the phase information contained in this digital signal received, and
an oscillator capable of supplying a signal making it possible to obtain the clock signal, and controlled by a phase error signal which is capable of being supplied by the processing means and which depends on the clock signal and said phase information, characterized in that the oscillator conforms to that of the invention and in that the switching means of this oscillator are controlled by a binary digital input signal resulting from said phase error signal.

 According to a particular embodiment of the device which is the subject of the invention, allowing the storage of the clock frequency (to the nearest possible multiplying factor), this device also comprises a shift register and a logic switch able to provide output a binary signal intended to control said switching means, the output of the logic switch is connected to the input of the shift register, said phase error signal is of the phase advance / phase delay type, the electronic processing means are further able to supply a digital signal for validation of this advance / delay signal, the logic switch receives the signal as an input. output of the shift register and the advance / delay signal and this Logic switch is controlled by the validation signal and capable of supplying as an output signal, the advance / delay signal When this is validated or the shift register output signal When the advance / delay signal is not validated.

According to another particular embodiment of the device which is the subject of the invention, said phase error signal is of the phase advance / phase delay type, the electronic processing means are further capable of supplying a digital signal for validation of this advance / delay signal, and the device further comprises
a digital filter capable of supplying a binary word as a function of the advance / delay signal and of the validation signal, and
- a digital delta sigma converter whose input is connected to the output of the digital filter and which is capable of translating said binary word into a binary sequence, the latter being intended to control the switching means of the oscillator, the device comprising thus a filtering and transcoding loop which comprises said electronic processing means, said digital filter, said digital delta sigma converter and said oscillator.

 The digital filter can be connected to the digital sigma delta converter directly or indirectly (in some special cases considered later).

 Likewise, the digital sigma delta converter can be connected to the electronic switching means forming part of the oscillator, directly or indirectly (in certain specific cases later considered).

 In a particular embodiment, also allowing the memorized clock frequency to be memorized (to within a possible multiplicative coefficient), said digital filter is an up-down counter.

 According to another particular embodiment, said digital filter comprises a first up-down counter and a second up-down counter 'connected in cascade, the first up-down counter is controlled by the advance / delay signal and by the validation signal and the second up-down counter is able to supply. said binary word.

In an advantageous embodiment of the device object of
The invention, the latter further comprises means for stabilizing said filtering and transcoding loop.

 The stabilization means may include a first multiplexer and a second multiplexer; the first multiplexer receives as input the output signal from the digital sigma delta converter as well as the output signal from the second multiplexer, and is controlled by a first digital signal of period T, which, for each period, is in Logical state 1 during a time interval of duration T1 and b Logical state 0 during a time interval of duration T2 with.

 T1 + T2 = T, the first multiplexer being provided to output the output signal of the delta sigma converter when the first digital signal is in logic state 1 and the output signal of the second multiplexer when the first digital signal is at logic state 0, the output signal of the first multiplexer constituting the digital input signal for controlling the switching means of the oscillator, and the second multiplexer receives as input the advance / delay signal as well as a second digital signal of period T, is controlled by the validation signal and is intended to output the advance / delay signal when it is validated, and the second digital signal otherwise, this second digital signal being, for each period, in logic state 1 only during a time interval of duration T2 / 2, included in the duration interval T2.

Alternatively, the stabilization means may include
means for converting the advance / delay signal into algebraic values, these conversion means being capable of providing the output with the value +1 when the advance / delay signal is in logic state 1 and the value -1 when the advance / delay signal is in Logical state 0,
first multiplication means provided for outputting a signal resulting from the multiplication of the output signal of the conversion means by the digital validation signal,
second multiplication means provided for outputting a signal resulting from the multiplication of the output signal of the first multiplication means by a determined gain, and
- summation means provided for outputting a signal resulting from the addition of the output signal of the second multiplication means to the binary word supplied as output by the digital filter, the output of the summation means being connected to the input of the digital sigma delta converter.

 Finally, the device - object of the invention may further comprise a circuit for rapidly re-phasing the signal supplied by the oscillator.

The present invention will be better understood on reading the description which follows, of exemplary embodiments given purely by way of non-limiting indication, with reference to the appended drawings in which:
- Figure I is - a schematic view of a particular embodiment of a conventional voltage controlled quartz oscillator,
FIG. 2 is a schematic view of a particular embodiment of the oscillator which is the subject of the invention,
FIG. 3 is a schematic view of a conventional digital phase locked loop,
FIG. 4 is a schematic view of a conventional analog phase-locked loop,
FIG. 5 is a schematic view of a phase locked loop using an oscillator according to the invention,
- Figure 6 is a schematic view # 'a controlled oscillator. in voltage, using an oscillator conforming to
The invention,
FIG. 7 is a schematic view of a clock recovery device, using an oscillator according to the invention as well as a shift register,
FIG. 8 is a schematic view of a particular embodiment of a digital delta sigma converter usable in the invention,
FIG. 9 is a schematic view of a particular embodiment of a clock recovery device using such a digital sigma delta converter and an oscillator according to the invention,
- Figures 10 and 11 are schematic views of other particular embodiments of a clock recovery device using the oscillator object of
The invention,
FIG. 12 is a block diagram of a clock recovery device using a first phase locking loop which comprises an oscillator according to the invention as well as a second stabilization loop of the first loop,
FIG. 13 schematically illustrates one way of producing the device shown in FIG. 12,
FIG. 14 is a timing diagram relating to certain signals used in the embodiment shown in FIG. 13,
FIG. 15 is a schematic view of another clock recovery device also using a first phase locking loop which comprises an oscillator according to the invention as well as a second stabilization loop of the first loop, and
- Figure 16 is a schematic and partial view of a clock recovery device according to the invention, using a fast phase resetting circuit.

 In Figure 1, there is shown schematically a particular embodiment of a conventional VCXO oscillator.

This known oscillator comprises an oscillating loop circuit comprising an inverting amplifier 2 as well as a piezoelectric element 4 comprising a quartz crystal suitably cut and placed between two electrodes which are respectively connected to the input and to the output of the amplifier. -inverter 2.

 The oscillator shown in FIG. 1 also includes a capacitance 6 called "bonding capacitance", a terminal of which is also connected to the input of the inverting amplifier 2, as well as a varicap diode 8 whose anode is earthed and the cathode of which is connected to the other terminal of -capacity 6 as well as to a terminal of a resistor 10.

 The oscillator shown in FIG. 1 also includes a phase shift capacitance 12 one terminal of which is grounded and the other terminal of which is connected to the output of the inverting amplifier 2.

 In a known manner, the application of an analog electric voltage vc between the other terminal of the resistor 10 and the ground makes it possible to vary the capacitance of the varicap diode 8 and therefore the frequency of the oscillator which is the frequency of the signal s supplied by the output of the inverting amplifier 2).

In Figure 2, there is shown schematically a particular embodiment of the oscillator object of the invention. In this particular embodiment,
The oscillator comprises an oscillating loop circuit comprising an inverting amplifier 14 as well as a piezoelectric element 16 constituted by a quartz crystal suitably cut and placed between two electrodes. The latter are respectively connected to the input and to the output of the inverting amplifier 16.

 The oscillator shown in FIG. 2 also includes a first capacitor 18, one terminal of which is connected to ground and the other terminal of which is connected to the input of the inverting amplifier 14, as well as a second capacitor 20 and a field effect transistor 22 mounted as a switch. The source of this transistor 22 is grounded while its drain is connected to a terminal of the second capacitor 20, the other terminal of which is connected to the input of the inverting amplifier 14.

 The oscillator shown in FIG. 2 further comprises a third capacitor 24 which constitutes a phase shift capacitance. One terminal of this capacitor 24 is connected to the output of the inverting amplifier 14 and the other terminal of this capacitor 24 is grounded.

 As a purely indicative and in no way limitative, the capacity 18 is of the order of 1 to 10 pf, the capacity 20 is.

on the order of 40 to 100 pf and the capacity 24 is on the order of 20 to 40 pf.

 The capacity 18 can even simply be constituted by a parasitic capacity of the circuit.

 The field effect transistor 22, which acts as an analog switch in the oscillator shown in Figure 2, is controlled by a binary digital signal DC which is applied to the gate of said transistor.

We will now explain how this digital signal
DC makes it possible to obtain at the output of the inverting amplifier 14, a signal S whose average frequency is a function of the density of the logic states 1 of the signal DC with respect to the logic states 0 of this signal DC.

When the field effect transistor 22 is blocked (analog switch open), which occurs when the signal
DC is in logic state 0 for example (depending, of course on the type of field effect transistor used), the capacitor 20 is not connected, only the capacitor 18 and the rest of the circuit are active, and l the oscillator provides a signal S of maximum frequency Fmax.

On the contrary, when the field effect transistor 22 is on (analog switch closed), which takes place when the DC signal is in Logic 1 state, the capacitor 20 is in parallel with the capacitor 18 and the oscillator supplies a signal
S of minimum frequency Fmin.

Consequently, the frequency of the signal S supplied by the oscillator can vary simply between Fmin and Fmax by varying the digital control signal DC of the oscillator. Indeed, if a DC signal is applied to the gate of the transistor 22, the output of the inverting amplifier 14 provides a signal S having an average frequency whose precise value depends on the ratio of the respective times of presence of the logic states "1" and "0" in the DC control signal during a given time interval. For example, if one chooses as signal DC a signal which passes periodically from Logical state O to Logical state 1 with the same duration for each state,
The oscillator provides a signal S whose frequency is equal to (Fmax + Fmin) / 2.

 The servo information of the oscillator shown in FIG. 2 is thus contained in the signal DC constituting a train of binary elements. The phase noise resulting from the continuous transition from Fmax to Fmin depends only on the DF / F ratio, in which F represents the nominal frequency of the quartz and DF is equal to Fmax-Fmin.

 However, for a quartz oscillator, this DF / F ratio is low (of the order of 10). Consequently, the phase noise is negligible for many applications, hence a low residual jitter for the phase locked loops using a quartz oscillator according to the invention, such as that which is represented in FIG. 2 .

We note that the latter, by its constitution, is easily integrated
In FIG. 3, there is shown schematically a known device for recovering the rhythm and phase of a digital signal SR, more simply called "clock recovery device", this device using a phase-locked loop of the type digital. This device comprises a clock 26 constituted by a quartz oscillator of stable frequency, close to a multiple of the bit rate of the received signal
SR, phase jump means 28 provided for adding or subtracting pulses from the clock 26, a divider 30 provided for supplying a clock signal HR at the rate of the digital signal received SR, means 32 for extracting the phase information contained in the signal SR, a phase comparator 34, one input of which receives the signal TS supplied by the extraction means 32 and the other input of which receives the clock signal HR supplied by the divider 30, and which provides information of advance or delay of the signal TS with respect to the signal HR to a digital filter 36 which can be constituted by an up-down counter whose output controls the phase jump means 28.

 The HR clock signal has a jitter which is produced by the phase jumps. To reduce this residual jitter, the frequency of the quartz oscillator used could be increased. For example, echo cancellation systems for the integrated services digital network would require frequencies on the order of 100 MHz for transmission at 160 kbit / s (frequency to be recovered from 160 kHz). Such a solution would require rapid technologies which are expensive and consume a lot of power.

In Figure 4, there is shown schematically another known clock recovery device, comprising an analog phase locked loop. The device represented in FIG. 4 comprises means 38 for extracting the phase information contained in the digital signal received SR, a phase comparator 40 whose input receives the signal TS supplied by the extraction means 38 and whose the other input receives the HR clock signal supplied by a divider 42 whose input 'is connected to the output of a voltage-controlled quartz oscillator 44. The phase comparator provides a voltage signal representative of the phase difference between the .TS and HR signals. This voltage signal is applied, after being filtered by a low-pass loop filter 46, to the input of Oscillator 44 to vary the frequency of the signal supplied by this oscillator until the HR signal is synchronous with the signal
SR.

 The clock used in the device represented in FIG. 4 is much more stable than the clock 26 in FIG. 3 (reduction of the residual jitter) but the realization of the analog loop represented in this FIG. 4 requires from a part a voltage analog control of Oscillator 44, hence a device more difficult to integrate than a numerically controlled device, and on the other hand a varicap diode (for the realization of oscillator 44), a diode whose integration is very delicate.

 The filter used in each of the devices shown in FIGS. 3 and 4 makes it possible to filter the phase error which controls the corresponding clock recovery loop. For example, for the device of FIG. 4, the narrower the bandwidth of the filter 46, the more the recovered clock is freed of residual jitter Le but the smaller the gripping range and the longer the acquisition time .

 In FIG. 5, there is shown diagrammatically a clock recovery device using an oscillator 48 according to the invention, for example of the kind which is shown in FIG. 2 and which comprises a piezoelectric element.

The device represented in FIG. 5 comprises electronic means -49 for processing -the digital signal received
SR, these processing means comprising means 50 for extracting the phase information contained in the digital signal received SR and a phase comparator 52, one input of which receives the signal TS (phase information) supplied by the means of extraction 50 and the other input of which receives the clock signal
HR provided by a divider 54 whose input is connected to the output of oscillator 48.

 The device shown in FIG. 5 is extremely simple: the phase comparator 52 provides phase error information which is in binary form (logic state 0 or 1) and which is used to directly control the switching means whose is provided with oscillator 48. Under these conditions, the recovered clock has a residual jitter which is negligible and the frequency of the oscillator does not need to be very high.

When the phase information TS is not highly noisy, the loop filtering becomes useless because the quartz oscillator 48 controlled by switched capacitance acts by itself as a loop filter.

 It will however be seen, with reference to FIG. 6, that the conventional principles of filtering phase-locked loops can be applied to loops using an oscillator such as the quartz oscillator 48, in accordance with the invention, as a frequency controlled oscillator. Indeed, the analog control voltage of a voltage-controlled quartz oscillator of the kind of that of FIG. 4 for example, can be transformed so that one can simply use an oscillator such as oscillator 48.

 To do this, an analog digital converter of the delta sigma 56 type, using simple integration for example, known in the state of the art, is used. An example of such a converter 56 is schematically represented in FIG. 6 and comprises an adder-integrator 58 as well as a flip-flop 60 of type D. The input + of the adder-integrator 58 receives the analog control voltage VC. The output of the integrator summator is connected to the input D of the flip-flop 60. The non-inverting output Q of this flip-flop is connected to the input - of the summator-integrator 58.

The analog voltage VC is converted, by the converter 56, into a sequence or binary train cds (for delta sigma code) representative of VC and supplied by the non-inverting output Q. This binary sequence cds controls the switching means 22 of the oscillator 48. Voltage conversion
VC in the binary sequence cds takes place at the conversion frequency fds of the converter 56.

 This conversion frequency is supplied by a clock 62 forming part of the converter 56, a clock whose output is connected to the clock input CK of the flip-flop 60.

 The exact value of the conversion frequency fds is not very important in the application of Oscillator 48 described with reference to FIG. 6.

 It can therefore be seen that a VCO (for example a VCXO) can be replaced by the association of an analog digital converter of the delta sigma type and of an oscillator (for example å quartz) in accordance with the present invention. that the device shown in FIG. 6 does not require any varicap diode, which facilitates its integration.

 We will now explain with reference to FIGS. 7 to 9 how to perform clock recovery by storing the recovered clock frequency or more exactly a multiple of this recovered clock frequency.

 We consider a clock recovery device which comprises, in a known manner, electronic processing means designed to provide phase error information. It is assumed that this information is in the form of binary information of the phase advance / phase delay type (the phase advance corresponding to logic state 1 and the phase delay corresponding to logic state 0) , with a validation state at each clock period.

 It is assumed that the validation signal of the advance / delay signal, validation signal which is also provided by the electronic processing means, is also binary information which is worth 1 If the advance / delay signal must be taken into account and O if this advance / delay signal is not valid and should therefore not be taken into account.

These assumptions cover applications where
The phase information has "holes" and is also valid for example when the phase error information comes from an adaptive recursive equalizer.

If, in a phase locked loop,
The phase error information is not permanently validated at each clock period according to the previous hypotheses), the recovered clock will tend to slip more or less quickly. This problem arises in particular in digital transmission When the transmission code used does not make it possible to collect permanent phase information or When activation-deactivation procedures momentarily cut off the signal transmitted (the so-called "transmission technique""or" ping-pong "is an example in which the transmission is periodically cut off). In these conditions, it is necessary to have a momentary memory of the transmitted frequency.

 Phase locked loops using an oscillator according to the invention lend themselves well to such storage. In fact, as already indicated, the frequency of the signal supplied by this oscillator depends on the cycle of the digital signal which acts on the switching means of said oscillator.

 In Figure 7, there is shown schematically a first device for said storage.

 The clock recovery device schematically represented in FIG. 7 uses, in addition to the oscillator 48, means 64 for processing the digital signal received SR, a shift register 66, a logic switch 68 (or multiplexer) and a divider 70 .

 The processing means 64 output the advance / delay A / R and validation VAL signals mentioned above. The logic switch 68, controlled by the validation signal VAL, receives as input the output signal from the shift register 66 and the advance / delay signal A / R. The output of the logic switch 68 is connected to the input of the shift register 66 and controls the switching means of the oscillator 48. The output of the latter is connected to the input of the divider 70 whose output is intended to supply the clock signal HR and is connected to an input of the processing means 64 which, in known manner, require this signal HR to compare it with the phase information extracted by them from the signal SR, in order to supply the signals A / R and VAL.

The device shown in Figure 7 operates as follows
If the A / R signal is validated (logic state 1 for VAL), then the switch 68 is put in a state in which this switch sends the A / R signal to the switching means of the oscillator 48; then, the state of A / R controls the oscillator 48 and this state is also stored in the shift register 66.

If the A / R signal is not validated (logic state 0 for
VAL), then the logic switch 68 is put in a state in which this switch sends the output signal of the shift register to the switching means of the oscillator 48; thus, the output of the shift register controls the oscillator 48. This shift register is then looped on itself. After a "learning" time (corresponding to the convergence of the device), the shift register has in memory a binary sequence representative of an average output frequency of the oscillator 48; this last is controlled by said sequence; the cycle stored in the shift register is representative of the frequency FO to be recovered and therefore allows the oscillator 48 to provide a signal of frequency FR very close (except for a multiplying coefficient) of Fi even in the case where the validation of the A / R signal is absent for a long time.

 The precision with which FR approaches FO in the absence of validation depends on the length of the shift register used. The longer this register, the longer the command cycle of the crystal oscillator 48 and the more precise the memorized information.

 We will now describe another hortoge recovery device also allowing the storage of the frequency to be recovered. This device is inspired by the device shown in FIG. 6 and uses a phase-locked loop comprising a device of the digital filter type which supplies a binary word E (N) of N bits, representative of the frequency to be recovered FO. This binary word E (N) can be compared to the control voltage VC which is converted into the sequence cds in the device shown in FIG. 6.

 A delta sigma digital converter, known in the state of the art, produces from this N bit word a CDS binary sequence, at an FDS frequency (converter conversion frequency), binary sequence which is representative of the word E ( N) to transcode.

 In FIG. 8, there is shown schematically an exemplary embodiment of such a digital delta sigma converter, which comprises, in this example, an adder 72 and an accumulator register 74. A clock not shown in FIG. 8 cadences the operation of this adder and this accumulator register at the FDS frequency. The adder 72 has its output connected to the input of the accumulator register 74 and receives as input the output signal of this accumulator register as well as the binary word E (N). The converter of FIG. 8 is thus capable of translating the word E (N) into the binary sequence CDS.

This is supplied by the adder 72.

In FIG. 9, the other clock recovery device is shown schematically, which also allows the memorized frequency to be memorized and which uses the digital sigma delta converter 76 shown in FIG. 8 as well as the processing means 64 already described, which receive as input the HR signal and the digital signal SR whose rhythm and phase are to be recovered and which supply the signals
A / R and VAL.

The device shown in FIG. 9 also includes the quartz oscillator 48, the output of which is connected to the input of the divider 70 which supplies the clock signal as an output.
HR.

 The device represented in FIG. 9 also includes an up-down counter 78 with N stages, which receives as input the signals A / R and VAL and which provides as output The binary word E (N). The CDS binary sequence which results from E (N) and which is supplied by the converter 76, is used to control the switching means of the crystal oscillator 48.

The A / R signal and the VAL signal are used to increment and decrement the up-down counter 78 (when the A / R signal is enabled, there is an increment of 1 for a phase advance and a decrement of 1 for a delay phase). This up-down counter 78 acts as a memory for the phase error command (in the absence of validation, the up-down counter remains at the value it had previously and the binary command word
E (N) does not change) and this up-down counter can be considered as a sequential filter (commonly used in digital phase locked loops).

 From the binary word E (N), The converter 76 produces the CDS sequence which controls the oscillator 48. This outputs a signal which is in phase with the signal SR and whose frequency is equal (to a coefficient multiplicative pres) at the frequency FO to recover.

The device shown in Figure 9 has an advantage over the device shown in Figure 7 in that, for equivalent performance, the device shown in Figure 9 uses a digital sigma delta converter which requires only a down-counter of N bits associated with an adder-accumulator of N bits, while the device represented in FIG. 7 uses a register å
-N length offset equal to 2
In Figure 10, there is shown schematically a clock recovery device which is a generalization of the device shown in Figure 9. The device of Figure 10 comprises the oscillator 48 whose output is connected to the input of the divider 70. The output of the latter provides the signal HR. This is sent to the processing means 64 which also receive the signal SR and supply the signals A / R and VAL to a digital loop filter 80 which, according to these signals, provides the binary word E (N) to the digital sigma delta converter 76. The latter translates this word into a sequence. binary
CDS allowing control of oscillator 48.

 The digital filter '80 can be as complex as you want (first order, second order, ...). This is particularly interesting when the phase error information is noisy for various reasons.

In FIG. 11, a particular embodiment of the device “diagrammatically shown in” in FIG. 10 has been represented. In the device represented in FIG. 11, the digital filter is constituted by a first up-down counter with N stages 82 set cascade with a second up-down counter
N floors 84.

 The first counter-sensor takes input A / R and VAL signals (to increment by one in the case of a phase advance and decrement by one unit in the case of a phase delay, this when the A / R signal is validated).

The second up-down counter 84 provides the binary word
E (N) to the converter 76 and is conventionally connected to the first up-down counter which supplies it, depending on the case, up count pulses UP or down count pulses DN.

 Returning to FIG. 10, the device represented in this figure comprises a filtering and transcoding loop which is composed of the elements referenced 64, 80, 76, 48 and 70 and which can be called "long-term loop" because it includes a digital filter which causes significant filtering but also induces a control delay which can be significant. This control delay can cause annoying oscillations in the long-term loop.

 This is why, according to the invention, in order to stabilize this long-term loop, it is possible to add to the device shown in FIG. 10 another loop known as "short-term loop". This short-term loop is, as will be seen more clearly below, a direct loop which acts directly and immediately on the control of oscillator 48. Furthermore, the long-term loop is assigned a gain G1 and the short-term loop is affected by a gain G2 different from G1.

 The joint use of these two loops makes it possible to obtain an HR signal always in phase with the clock signal to be recovered whatever the difference between the frequency of this clock signal to be recovered and the central frequency of the oscillator 48, this central frequency being equal to (Fmax + Fmin) / 2.

We will now give two examples of clock recovery devices using the two loops. In these two examples, the digital control signal of oscillator 48 results from the summation of a long-term loop control signal and a short-term loop control signal and, in a first example , this is a temporal summation carried out after the delta sigma converter (FIGS. 12 and 14) while in a second example, this summation is digital and carried out before this delta sigma converter (FIG. 15),
More specifically, in Figure 12, there is shown a block diagram of a first clock recovery device using a long-term loop and a short-term loop and comprising the processing means 64 which receive the input signal SR as well as the HR signal and which output the A / R and VAL signals.

The device shown in FIG. 12 also includes the digital filter 80 which, from the A / R signals and
VAL, generates the binary word E (N), as well as the digital delta sigma converter which, from this binary word, generates the CDS sequence.

 The device shown in FIG. 12 also includes the crystal oscillator 48, the output of which is connected to the input of the divider 70 which supplies the HR signal as an output.

 In addition, according to the diagram represented in FIG. 12, a signal M1 is formed resulting from the multiplication of the signals A / R and VAL, a signal M2 resulting from the multiplication of the signal h1 by a gain G2, a signal M3 resulting from the multiplication of the CDS sequence by a gain G1 and a signal M4 resulting from the summation of the signals M2 and M3. This signal M4, which is digital, controls the switching means of the oscillator 48.

In Figure 13, there is shown the means for performing the various multiplications and the summation which is discussed above. A first multiplexer 94 and a second multiplexer 96 are used for this purpose. The signal supplied by the output of the multiplexer 94 controls the switching means of oscillator 48. This multiplexer 94 is controlled by a loop control signal CB and receives at an input cl the CDS signal and at an input e2 the output signal from the multiplexer 96. The latter is controlled by the signal VAL and receives at an input cl The A / R signal and at an input e2 a signal
HZ.

 The signal CB is a digital signal of period T and, for each period T, is in the logic state 1 for a duration T1 and in the logic state O for a duration T2, T being the sum of T1 and T2 ( figure 14).

The HZ signal is also a digital period signal
T which, for each period T, is in logic state 1 for a duration T3 and in logic state 0 for the rest of the period, this duration T3 being equal to half of T2 and the interval of duration T3 being included in the duration interval T2 (see also Figure 14). By way of nonlimiting example, the rising edge of a slot corresponding to the logic state 1 of the signal HZ is synchronous with the falling edge of a slot corresponding to a logic state 1 of the signal CB.

 The signals CB and HZ are easily constructed from the multiples of the frequency of the signal HR coming from the divider 70 and resulting from the division of the signal supplied by the oscillator 48.

To do this, the divider 70 is provided with means 71 such as a time base, which provides the signals CB and GZ.

 The period T can be chosen equal to the period of the clock signal to be recovered since there can be a validation of phase error per clock period.

 When the signal CB is in logic state 1 for a duration T1, the first multiplexer 94 is provided to output the signal CDS (output of the digital delta sigma converter). When the signal CB is in Logical State O for a duration T2, the multiplexer 94 is provided to output the signal it receives at its input e2 and which is the output signal from the second multiplexer 96.

This multiplexer 96 is provided to output the signal A / R when the signal VAL is in logic state 1 and
When this signal VAL is in the logic state O, the second multiplexer 96 is provided to output the signal HZ.

In the latter case, we see that the capacity 20 of
The oscillator 48 (see FIG. 2) is connected in parallel to the capacity 18 of this oscillator during your half of the duration T2, and not connected to this capacity 18 during the other half of the duration T2. We then see that the duration T1 is directly proportional to the gain G1, with a certain coefficient of proportionality, and that the duration T2 is directly proportional to the gain G2 with the same coefficient of proportionality.

 Therefore, by varying the form of the control signal CB which is characterized by the durations T1 and TZ, it is possible to choose the ratio G1 / G2 of the respective gains of the long-term and short-term loops.

In Figure 15, there is shown schematically another clock recovery device also using a long-term loop and a short-term loop. The device represented in FIG. 15 comprises the processing means 64 receiving as input the signal SR and the signal HR supplied by the divider 70 and supplying as output the signals
A / R and VAL, as well as the sigma delta converter 76 which outputs the CDS sequence, the quartz oscillator 48 which is controlled by this sequence as well as the divider 70 whose input is connected to the output - of oscillator 48 and which outputs the HR signal.

The device represented in FIG. 15 also includes the digital filter 80 which, from the A / R and VAL signals supplied by the processing means 64, generates the binary word
IN).

 In addition, the device shown in FIG. 15 comprises a means 98 for converting the A / R signal into algebraic values. This. means 98 receives the input A / R signal and outputs the value -1 when this AIR signal is in logic O state and the value +1 when this A / R signal is in logic state 1.

 The device shown in FIG. 15 also includes means 100 for multiplying the value Cl supplied by the means 98, by the signal VAL, the signal C2 supplied by the output of these means 100 thus being capable of taking one of the values û, +1 and -1.

The device shown in FIG. 15 finally comprises means 102 provided for providing an output. signal C3 resulting from the multiplication of signal C2 by a gain 62 and the means 104 provided to output a signal C4 equal to the sum of the signal C3 and the binary word E (N), the output of the means 104 being sent to L input of the converter 76. The latter thus receives the signal C4 (instead of the word E (N) as was the case for the device in FIG. 12) and supplies the sequence
CDS to the oscillator, from this signal C4, to control the switching means of this oscillator.

 We see that in the device of Figure 15, the gain G1 does not appear and can therefore be considered equal to 1, only the ratio 61 / G2 being important in the end.

 The gain G2 thus makes it possible to measure the influence of the loop in the short term.

 When the signal VAL is in logic state 0, only the long-term loop is active, resulting in a "memory of the recovered clock frequency" effect.

 The device shown in FIG. 15 can be produced either by "wiring", by means of logic elements, or by means of a microprocessor. In the latter case, the diagram in FIG. 15 is rather to be considered as a principle diagram, all the calculations indicated above (algebraic conversion, multiplications, addition) being done in the microprocessor.

 The devices respectively shown in FIGS. 13 and 15 have the following advantages: they only induce a very small residual jitter; the phase of the clock signal recovered is independent of the difference between the frequency of the clock of the signal received and the center frequency of the oscillator; these two devices have great operating stability (memory) When the validation signal of the phase error is suppressed for a fairly long period; finally, these two devices can be very easily integrated in the form of integrated circuits because all of the control circuits they use are digital.

 The devices schematically represented in FIGS. 5, 7, 9, 10, 11, 12, 13 and 15 can be supplemented by a circuit for rapidly resetting the signal supplied by the oscillator 48 and therefore the clock signal HR, If necessary in the intended application.

 Different rapid re-phase circuits are known in the state of the art.

 The function of such a fast phase-resetting circuit is to allow correct operation, from the use of the clock recovery device, of a certain number of systems whose operation depends on the phase (and not on the frequency precise) of the recovered clock signal. Among these systems, there may be mentioned, for example, the adaptive recursive equalizers or the data reception systems used in digital transmission.

 One can use as a fast phase resetting circuit, a phase jump means 106 which receives as input the signal coming from the oscillator 48 and the output of which is connected to the input of the divider 70 (FIG. 16). This phase jump means 106 is controlled by an MPR signal from the processing means 64. Furthermore, this MPR signal is such that it only makes the phase jump means active during the activation period of the device. clock recovery.

Claims (16)

 1. Oscillator comprising an oscillating loop circuit, characterized in that it further comprises:  - an electrical element (20) which is interposed in the circuit and - the presence of which modifies the frequency of the oscillator, and  - analog switching means (22) provided for switching this element (20), thus allowing the frequency of the oscillator to take one or the other of two values Fmax and Fmin, and in that said switching means (22) are controlled by a binary digital input signal (DC) which allows the oscillator to supply a signal whose average frequency is a function of the density of the logic states 1 by relation to the logical states O of the input signal.  2. Oscillator according to claim 1, characterized in that said element is a capacitor (20).  3. Oscillator according to claim 2, characterized in that, said circuit comprising another capacity (18), said capacity (20) is mounted in parallel with this other capacity and in that the switching means are provided to interrupt or restore , depending on the input signal, the Connection in parallel of the capacities (18, 20).  4. Oscillator according to any one of claims 1 to 3, characterized in that the oscillating loop circuit comprises a piezoelectric element (16).  5. Oscillator according to any one of claims 1 to 4, characterized in that it is preceded by a shift register (66) in which a binary sequence is capable of being stored and whose output is capable of being connected to the input of said register and to control said switching means (22).  6. Oscillator according to any one of claims 1 to 4, characterized in that it is preceded by a digital delta sigma converter (76) capable of being controlled by a binary word and capable of translating this binary word into a sequence binary intended to control said switching means (22).  7. OsciLlateur according to any one of claims 1 to 4, characterized in that it is preceded by. an analog-digital delta sigma converter (56) which receives an analog voltage (VC) as an input and which is capable of converting this analog voltage into a binary sequence, and in that said switching means (22) are controlled by this sequence binary.  8. Device for recovering the rhythm and phase of a digital signal received (SR), this device being designed to supply a clock signal (HR) and comprising:  electronic means (49, 64) for processing the digital signal received, capable of extracting the phase information contained in this digital signal received, and  - An oscillator (48) capable of providing a signal making it possible to obtain the clock signal, and controlled by a phase error signal which is capable of being supplied by the processing means and which depends on the signal clock and said phase information, characterized in that the oscillator (48) conforms to any one of claims 1 to 4 and in that the switching means of this oscillator are controlled by a digital input signal binary resulting from said phase error signal.  9. Device according to claim 8, characterized in that it further comprises a shift register (66) and a logic switch (68) capable of supplying an output of a binary signal intended to control said switching means (22) , in that the output of the Logic switch is connected to the input of the shift register, in that said phase error signal (A / R) is of the phase advance / phase delay type, in that the electronic processing means (64) are further able to supply a digital signal (VAL) for validation of this advance / delay signal, in that the logic switch receives as input the output signal from the shift register and the signal advance / delay and in that this logic switch is controlled by the validation signal and capable of providing as an output signal, the advance / delay signal when the latter is validated or the output signal from the register offset When the advance / delay signal is not validated.  10. Device according to claim 8, characterized in that said phase error signal (A / R) is of the phase advance / phase delay type, in that the electronic processing means (64) are further capable providing a digital signal (VAL) for validation of this advance / delay signal, and in that the device further comprises  a digital filter (78, 80, 82-84) capable of supplying a binary word (E (N)) as output as a function of the advance / delay signal and of the validation signal, and  - a digital delta sigma converter (76) whose input is connected to the output of the digital filter and which is capable of translating said binary word into a binary sequence (CDS), the latter being intended to control the switching means of the oscillator (48), the device thus comprising a filtering and transcoding loop which comprises said electronic processing means (64), said digital filter (78, 80, 82-84), said digital delta sigma converter (76) and said oscillator (48).  11. Device - according to claim 10, characterized in that said digital filter is an up-down counter (78).  12. Device according to claim 10, characterized in that said digital filter comprises a first counter-counter (82) and a second up-down counter (84) connected in cascade, in that the first up-down counter is controlled by the signal d advance / delay (A / R) and by the validation signal (VAL) and in that the second up-down counter is able to supply said binary word (E (N)).  13. Device according to claim 10, characterized in that it further comprises means for stabilizing (94-96, 98-100-102-104) of said filtering and transcoding loop.  14. Device according to claim 13, characterized in that the stabilization means comprise a first multiplexer (94) and a second multiplexer (96), in that the first multiplexer receives as input the output signal (CDS) of the delta converter digital sigma (76) as well as the output signal of the second multiplexer, and is controlled by a first digital signal (CB) of period T, which, for each period, is in logic state 1 during a time interval of duration T1 and in the logic state O during a time interval of duration T2, with T1 + T2 = T, the first multiplexer being provided to output the output signal (CDS) of the delta sigma converter when the first digital signal ( CB) is in logic state 1 and the output signal of the second multiplexer when the first digital signal is in logic state 0, the output signal of the first multiplexer constituting the digital input signal for controlling the means ( 22) Osc switching illator, and in that the second multiplexer (96) receives as input the advance / delay signal (A / R) as well as a second digital signal (HZ) of period T, is controlled by the validation signal (VAL ) and is intended to output the advance / delay signal When this is validated, and the second digital signal in the opposite case, this second digital signal being, for each period, in Logical state 1 only during a time interval of duration T2 / 2, included in the duration interval T2.  15. Device according to claim 13, characterized in that the stabilization means comprise:  - Means (98) for converting the advance / delay signal into algebraic values, these conversion means being capable of providing the output with the value +1 when the advance / delay signal (A / R) is at L ' logic state 1 and the value -1 when the advance / delay signal is in logic state 0,  - first multiplication means (10û) provided to output a signal resulting from the multiplication of the output signal of the conversion means by the digital validation signal (VAL),  second multiplication means (102) provided for outputting a signal resulting from the multiplication of the output signal of the first multiplication means by a determined gain (G2), and  - summation means (104) provided for outputting a signal resulting from the addition of the output signal of the second multiplication means to the binary word (E (N)) supplied as output by the digital filter (80), the output of the summing means being connected to the input of the digital sigma delta converter (76).  16. Device according to any one of claims 8 to 15, characterized in that it. further comprises a circuit (106) for rapidly re-phasing the signal supplied by the oscillator (48).