FR2545294A1 - INVERTER PRIMING CONTROL CIRCUITS WITH ERROR COMPENSATION - Google Patents

Abstract

THE INVENTION RELATES TO AN INVERTER BOOT CONTROL CIRCUIT WITH ERROR COMPENSATION. THIS CONTROL CIRCUIT ESSENTIALLY INCLUDES A FIRST Z6 COUNTER WHICH COUNTS CLOCK PULSES BETWEEN A TRANSITION POINT OF A CONTROL SIGNAL AND THE OPERATION OF THE ASSOCIATED PHASE SWITCH, A Z13 MEMORY WHICH STORES THE NUMBER OF PULSES COUNTED AND A SECOND Z9 COUNTER PRE-SET TO BEGIN COUNTING FROM A NUMBER EQUAL TO THE NUMBER OF CLOCK PULSES PREVIOUSLY COUNTED BY THE FIRST COUNTER SO AS TO INTRODUCE THE DELAY TIME NECESSARY FOR THE OPERATION OF THE PHASE SWITCH. THE INVENTION APPLIES TO SINGLE-PHASE AND POLY-PHASE INVERTERS.

Description

INVERTER PRIMING CONTROL CIRCUITS WITH

ERROR COMPENSATION

  The present invention relates to electric inverters, and more particularly relates to a circuit for controlling the phase switching of inverters

modulated in pulse duration.

  Pulse-length modulated continuous-alternating inverters provide approximately sinusoidal outputs by controlling phase switches at a frequency higher than the fundamental sinusoidal frequency of the AC output. In the design of pulse-width modulated inverters , it is desirable to switch the power stage so as to reduce certain harmonics to low values in order to facilitate the filtering load of the

  output current and get a sinusoidal voltage.

  Relatively small errors in switching times

  may produce several harmonic voltages

  times greater than that desired.

  that the filtering circuit is considerably larger than would be theoretically necessary

to remove these harmonics.

  For example, in a transistor inverter,

  it is necessary to ensure a condition of non-

  overlap to avoid short circuits during switching This means that to switch an output point from one polarity to another, it takes a delay after the conductive transistor is locked to be sure that it will no longer drive when the other transistor is unblocked Very often, the load conditions are such that the second transistor is not at all conductive because the load current is derived by a switching diode, thus shortening the switching time with respect to the blocking time of the transistor The switching time of the transistor is

  very variable depending on the load current instan-

  tane as well as blocking characteristics of the transis-

  Therefore, the prescribed switching program may not be filled, resulting in

unpredictable harmonics.

  The aim of the invention is to reduce the output distortion due to switching errors to minirium by providing the required switching time for each switching point and using this prediction to set the start time of each switching period.

  switching, so that the switching is programmed.

  In general, a reference waveform to be reproduced at the phase output is available for the switching control circuit. The pulses in the reference wave must be reproduced at the phase output after a predetermined time interval. This delayed switching program is executed by measuring the switching time of a phase for a given pulse in an output cycle and subtracting the measured switching time from the predetermined time interval to obtain a delay time. switching for the corresponding pulse in the next output cycle, is then triggered at a point equal to the delay, obtained in the previous sycle, following

  the appropriate reference waveform pulse.

  This process is repeated for each phase output pulse In continuous operation, it is reasonable to assume that the switching periods are of the same length at corresponding switching points in each subsequent cycle. Therefore, the phase is switched after a period of time. predetermined time

  following the pulses of the reference wave.

  A circuit which fulfills this delayed phase switching function is described in United States Patent Application No. 355,073 filed March 5, 1982 in the name of the Applicant. This patent application discloses a circuit and method for eliminating any distortion in the inverters caused by

  the phase switching delay variations.

  Although tests of the circuit described in this patent application have confirmed the operation as described, random instabilities occur, resulting in momentary disturbances of the output voltage.

of the inverter.

  The essential object of the invention is to obtain greater stability of operation. In general, the invention relates to a phase switch firing control circuit for controlling a pulse width modulated inverter as a function of a reference pulse signal, said control circuit comprising a a shaping circuit which produces a control signal with transition points for triggering a phase switching sequence in the inverter, a first counter having a number of clock voltage pulses occurring between a predetermined transition point of said control signal and the switching of the associated phase switch, a memory circuit which stores the number of the clock voltage pulses counted by the first counter during each phase switching sequence, a second preset counter to start the counter at one number equal to the number of clock pulse pulses previously counted

  by the first counter during the switching sequence

  the associated phase switch, and connected to count the voltage pulses that occur after a predetermined transition point of the reference signal until a predetermined count is reached, so that the second counter produces a pulse of retaining outlet which results in the shaping circuit producing a

  second transition point in the control signal.

  Thanks to an appropriate timing of the switching function, polyphase inverters

  can be controlled by a single control circuit.

  The device which stores the number of voltage pulses counted by the first counter may be a shift register which stores the count of the first counter during each switching sequence and which delivers an appropriate stored count to the preset counter at an appropriate time to produce the

  desired waveform at the output of the inverter.

  The circuit according to the invention controls the operation of a phase switch in an inverter modulated in pulse duration according to a method consisting of

  to count a series of clock pulses that appear-

  between a determined transition point of a control signal and the actual operation of the phase switch in response to the transition point with a first counter; presetting a second counter at a count equal to the number of clock pulses counted by the first counter; operating the second counter to count the clock pulses, starting at the preset count when a predetermined transition point appears in a reference signal; and displaying a second transition point in the control signal when the second counter has a predetermined count, thereby triggering a phase switch switching sequence. Other features and advantages of

  the invention will appear during the description

  FIG. 1 is a series of waveforms illustrating the operation of an inverter priming control circuit according to the invention, during which FIG. FIG. 2 is a series of waveforms illustrating the operation of an inverter priming control circuit according to the invention, for a cycle of inverter output following the cycle. Figure 3 is a schematic diagram of an inverter boot control circuit realized according to a mode of operation.

embodiment of the invention.

  Referring to the drawings, the waveforms of FIG. 1 illustrate the inverter initiation control method and apparatus according to the invention for a portion of a single transient output cycle of a modulated inverter. in pulse duration In FIG. 1, the waveform A shows a pulsed wave P which forms part of a reference signal to be reproduced

  at the output of an inverter phase The reference signal

  It can be produced in the inverter priming control circuit or can be received from an external source. A fixed time interval T is shown with respect to each transition point of the pulsed wave P. purpose of switching the phase of the inverter at the end of each period T, so that the output of the inverter reproduces the reference signal To maintain a correct boot control function, the interval of time T must be at least as long as the maximum time of

switching of the phase.

  The waveform B of FIG. 1 represents a cumulative number of clock pulses counted by a pre-adjustable counter containing a pre-set count, for example Cl, C 2 and C 3 and being allowed to count after a transition point of the pulsed wave P. The pre-adjustable counter has a maximum count M 4 C which corresponds to the desired delay time T. In FIG. 1, the waveform C represents a control signal CN which reacts to count the pre-adjustable counter by producing a transition point each time the maximum count MC is reached These transition points are used to trigger

  the phase switching sequence of the inverter.

  In continuous operation, it is reasonable to assume that the switching times have the same value at the corresponding switching points of each subsequent cycle. Therefore, if a switching sequence is triggered after a delay TS which is equivalent to the difference between an interval of fixed time T and the switching time to the previous cycle, the actual switching occurs after the interval of

full time T.

  The other waveforms of FIG. 1 illustrate the means applied to achieve this result. The waveform D shows the output signal OP which represents the voltage of an output phase of the inverter. D 2 and D 3 are indicated after each transition of the control signal DN. The waveform E of FIG. 1 is the control signal TC and represents a cumulative count in a time measuring counter which measures the switching time of This function is fulfilled by a second counter which starts counting clock voltage pulses upon the appearance of a transition point of the NC control signal. The counting stops when the phase is switched, leaving a counting equivalent to the delay time TS to be used to control a pulse during the next output cycle This count is then stored in a memory, such as a random access memory or

a shift register.

  The waveform F of FIG. 1 represents a pulsed wave W by which data from the second counter and necessary for the next counting cycle are introduced into the memory element which advances and transfers the appropriate data to the counter. next operation of switching to the preset counter The number of stages of the memory, which may be a shift register, is equal to the number of phase switching operations in an inverter output cycle. The waveform G of the FIG. 1 represents a pulsed wave R which restores the second counter after its data have been introduced

in the shift register.

  The waveforms of FIG. 2 illustrate the operation of the invention for an inverter output cycle following the transient output cycle

  represented by the waveforms of Figure 1.

  During this cycle, the transition points of the control signal CN are delayed by a time equal to the time required for the pre-adjustable counter to count from its pre-set value to its maximum count, after a transition point in the wave

  pulsed P of reference waveforms In operation

  permanently, the running time of a switch

  for a given pulse in a cycle is equal to the operating time of a switch for the corresponding pulse of the previous cycle Therefore, the inverter output signal P changes state after a delay D1 following the first transition of the signal of NC control This results in a switching operation at a fixed time interval T after a transition point of the pulsed wave P of the reference signal. Under continuous operating conditions, the process continues for each pulse of the output cycle, with the sum of the delay of the control signal

  and switching delay always equal to

  FIG. 1 shows that the output signal OP does not change state after a fixed time interval T following a transition point in the reference pulse wave P This illustrates the response of the circuit when a transient condition appears just before the sampling cycle observed. On return to steady state,

  the switching program is satisfied.

  Fig. 3 is a control circuit diagram

  priming apparatus according to one embodiment of the invention.

  For simplicity, only one phase switching element 10 is shown. But it is understood that

  the invention can be applied to poly-inverters

  phased using known and appropriate drivers CT terminals are for receiving a clock signal consisting of a series of voltage pulses The configuration of desired output switching represented by the reference waveform T is developed in a shaping generator 12 in response to the clock pulse signal A bistable circuit Z1 which may be of the T type, as shown, serves to produce a control signal CN with transition points as shown in FIGS. and 2 A driving circuit 14 is made according to a known technology and it is used to control the phase 10 as a function of the NC control signal A comparator Z 2 compares the voltage appearing at the point N with a voltage signal taken from the filter 16 to produce the

OP output signal.

  The combination of the bistable circuit Z 3, the inverter Z 4 and the AND gate Z 5 ensures that only complete clock pulses are applied to the first counter Z 6 The bistable circuit Z 3 emits an authorization signal that allows clock pulses are received by counter Z 6 after a transition point of the NC control signal A change of the signal at the input of the bistable circuit TZ 3 is transmitted to the output Q, only if the clock pulse passes at low level, because of the signal

  inverted clock at the input C of the bistable circuit.

  If signals in D and Q are low and if

  the signal at D goes high while the impulse

  clock is high, the counter input remains low until Q is leveled

  high by a negative transition of the clock signal.

  Thus, the counter Z 6 can receive only a first complete clock pulse. Even if D and Q are high and D goes low in a clock pulse at the high level, there can not be no change of Q until the clock pulse disappears, also providing a full clock pulse to the counter Although this may result in an error of an entire period of a clock pulse in the time of recorded switching

  phase, this is considered to be negligible compared

  to a possible misreading by the meter

  if he had to count clock impulses incom-

  Thus, the addition of the bistable circuit Z 3 assures a correct transmission of data to the counter Z 6 and eliminates any possible source of erratic operation. When the reference waveform P, the control signal CN and the output signal OP all match, the circuit is at rest.

  the waveform P changes state, causing a deactivation

  cord with the NC control signal, the output of the EXCLUSIVE-OR gate Z 7 goes high, allowing the AND gate Z 8 to transmit the clock pulses to the preset counter Z 9. predetermined value, which can be its total capacity, so that its hold output signal goes low At the next clock pulse, all outputs of the counter go to zero

  and the restraint output signal goes high.

  This causes the operation of the bistable circuit Z1 and changes the state of the control signal CN which again corresponds to the reference waveform P, which stops the counter Z 9. At this time, the control signal CN is in disagreement with the output signal

OP inverter.

  Two actions are triggered by the appearance

  a transition point in the NC control signal.

  First, the driver circuit 14 starts the

  switching sequence of the inverter phase.

  Then, the output of the EXCLUSIVE-OR gate Z 10 goes high, allowing the clock pulses to reach the counter Z 6 which counts them until the phase is switched and which causes a transition of the form output waveform OP so that it corresponds with the control signal CN, which inhibits any other counting by the counter Z 6 This change in the output signal OP also triggers a series of two pulses produced by monostable multivibrators Z 11 and Z 12 The output of the Zli monostable multivibrator

  is the pulsed waveform W of Figures 1 and 2.

  This waveform is used to load data from the counter Z 6 into the shift register Z 13 which serves as a memory element, and which shifts the new data to the pre-adjustable counter Z 9, thereby setting this counter Z 9 to a new data figure before

  the end of a pulses of the waveform W The impulse

  The waveform W is also inverted by the Z inverter 14 and transmitted to the monostable multivibrator Z 12. The output of the multivibrator Z 12 delivers a second pulsed waveform identical to the waveform R of the figures. 1 and 2 The pulses of the waveform R restores the counter Z 6 so that it is ready to count during the phase switching delay of the next output cycle. The control circuit is then idle until next transition point of the reference wave P. The length of the shift register Z 13 is such that a data word representing the switching time of a phase is stored for each of the

  switching points in an inverter output cycle.

  Thus, when current data equal to the number of clock pulses required for a just ended phase switching operation are input into the shift register, the number required for the next switching point is placed in the counter.

  pre-adjustable Z 9 This number represents the time of com-

  switchover at a switching point corresponding to

  of the previous output cycle of the inverter.

  Thus, when the reference waveform P subsequently changes, the pre-adjustable counter starts counting to a number representing the expected switching delay of the associated phase and counts up to its capacity.

total.

  The phase is then switched at a moment to

  about the same as previous cycles.

  As a result, the phase switching is a replica of the reference waveform P, but with a delay of a predetermined period T equal to

  total count of the pre-adjustable counter Z 9.

  The invention has been described with regard to a particular embodiment but it is obvious that many modifications can be made therein.

  brought without leaving his frame or his mind.

Claims (5)

  1 Communicator boot control circuit   phase controller for controlling a pulse width modulated inverter in accordance with a reference pulse signal, said control circuit comprising a shaper circuit (12) which produces a control signal having transition points for triggering a sequence of pulses; phase switching in the inverter, a first counter (Z 6) for counting a number of clock voltage pulses which appear between a determined transition point of said control signal and the operation of an associated phase switch, a memory circuit (Z 13) for storing the number of the clock voltage pulses counted by said first counter during each phase switching sequence, characterized in that it further comprises a second counter (Z 9) pre-adjustable to start counting to a number equal to the number of clock pulse pulses previously counted by said first counter (Z 6) during the sequencing a preceding switch of said associated phase switch, and connected to count said voltage pulses that occur after a predetermined transition point of said reference reference signal, until a determined count is reached, so that said counter produces a retaining output pulse by which said shaper circuit produces a   second transition point in said control signal.   Circuit according to Claim 1, characterized in that it also comprises a transfer circuit (Z 11, Z 12) for transferring the stored number of voltage pulses for a given phase switch to said second counter when said switch phase is the next phase switch to initiate.   Circuit according to claim 2, characterized   characterized in that said memory circuit (Z 13) consists of a shift register, said transfer circuit (Z11, Z 12) comprising a monostable multivibrator connected to the offset input of said shift register.   Circuit according to any of the claims   1 to 3, characterized in that the circuit according to   Mateur (12) has a bistable circuit. Circuit according to any one of claims 1 to 4, characterized in that it further comprises a circuit (Z 3, Z 4, Z 5) provided to provide only complete clock voltage pulses to said first counter.   Circuit according to claim 5, characterized   characterized in that said circuit for providing only complete clock voltage pulses comprises an AND gate (Z 5) whose output is connected to the first counter and comprising two inputs, a first of which is connected to a dummy device which receives a signal clock, a bistable circuit (Z 3) having a clock input and an output (Q), said output (Q) being connected to the second of the inputs of said AND gate and an inverter (Z 4) having an input connected to said device which receives a clock signal and whose output is connected to the clock input of said bistable circuit.