FI86483C - Device for monitoring a data processing system - Google Patents

Description

1 86483

Device for monitoring a data processing system

TECHNICAL FIELD The present invention relates to a device for monitoring a data processing system, which controls, for example, telecommunications equipment and comprises an address bus capable of transmitting 2n addresses at a time, which is connected to computer elements such as memory locations and inputs. / output terminals to which data are obtained by each assigned binary address associated with the bus belonging to a first category of k used for current data processing, with an address redundancy stall being provided, which is a 2n-k unused addresses of a second category at current data processing.

The state of the art

Synchronous doubling with comparison, multiple redundancy with majority choice, parity control, and time monitoring in the form of watch dog and microprogrammed pointer control are known principles for monitoring a data processing system. In many cases, duplication, even if only partially used, is very expensive. Parity checking requires a fairly significant component addition. Pointer: ·. control and parity generation mean extended access times in data processing. Time monitoring results in - too late error detection.

The state of the art is addressed, for example, in the "12th Annual International Symposium on Fault-Tolerant Computint", Session 6B On-Line Monitoring, pages 237-256 30 (ISSN-0731-3071).

Disclosure of the Invention • Since the addresses transferred to the address bus are formed in a known manner by means of data transport and data calculations, an indirect monitoring of the data processing of, for example, a program memory controlled telecommunications system, is obtained by means of an address monitoring proposed in accordance with the invention.

As proposed in the claims, the proposed device is characterized by an insignificant component addition, more than at most 2n simple indication registers connected to the address bus, the outputs of which are connected to a fault signal generator. However, a prerequisite for the proposed monitoring principle is that the address bus has the initially mentioned overcapacity in relation to the number of computer elements connected thereto, i.e. 2n> k.

This condition often exists especially in today's microprocessors with n = 16 and applications of computer elements, whereby only a minor part of the possible addresses come into use and thereby obtaining said two categories of addresses.

According to the invention, the indication registers store information about the category affiliation of their addresses. Since proper data processing only results in the addresses of the first 2Q category, an error signal is generated due to each indication given by the registers that an address transmitted on the bus belongs to the second category. The greater the address redundancy of the data processing system, the greater the chance that the simple proposed monitoring device detects data processing errors.

Figure Description

The invention is further explained with reference to the accompanying drawing, the only figure of which shows an address bus 3 and computer element 2 of a data processing system 1 as well as a monitoring device comprising an error signal generator 5 and indication register 4 connected to the address bus.

Proposed embodiment

By a conventional data processing system 1, in the drawing, computer elements 2/1, 2/2 ... 2 / k, whose access inputs are connected to an address bus 3, are indicated by means of n 3 86 483 parallel wires. get 2n binary address numbers, which are received, for example, from an address calculation unit not shown. The access elements of the computer elements are connected to each output of an input in the bus but in the drawing, conventional address decoder not shown. Access to an element is obtained when an element assigned to the first category's address number is transferred on the bus. The drawing shows single computer elements 2/1, 2/2 ... 2 / il, for example, input / output terminals, 10 with separate address numbers A16, A32, A48 and element series 2 / i, 2 / i + l. ..., 2 / ka ... 2 / k, for example, memory locations for storing instruction sequences, with successively increasing address numbers A64, A65 ..., A2n-a ... A2n. The drawing further shows the address bus exits, whose address number of other category categories, for example Al ... A15, A49 ... A63, constitutes the address number redundancy of the data processing system.

The address bus is connected to a plurality of indication registers 4 for storing the address category indication. According to the drawing, all 2n address numbers that can be present on the bus activate their register for reading, whereby stored information is transmitted to an error signal generator 5. All k registers with the associated category's address number, for example A64, store a binary "0" 25 and all 2n-k registers with associated other categories: V address numbers, such as Al ... A15, store a binary "1".

: Generator 5 generates an error signal because of a current second category's address number, which does not allow access to a computer element.

The monitoring device must include so many indication registers that a safe indication of a current ad. interest category affiliation is possible. A secure indication accepts a device variant that includes only 2n-k registers, which are activated for resolution upon receipt of each address's // second category's address number, with binary "1" from the registers output 4 86483 indicating data processing errors. A further device variant comprises only k registers which are activated for reading a stored binary "1" upon receiving each of its first category address neurons and whose outputs 5 are connected to an inverting and idle input of an AND gate . A conventional so-called 'fetrobe' signal is used, so notify each address transmitted on the bus, to activate the second input of the AND gate.

If no access to a register is obtained, the AND-1Q sends the "strobe" signal to the activation signal of the error signal generator.

Claims (4)

5 86483 An apparatus for monitoring a data processing system (1), which controls, for example, telecommunication equipment and comprises an address bus (3) having the ability to transmit 2n addresses at a time connected to a computer element ( 2) such as memory locations and input / output terminals, to which access is obtained by means of each assigned and transmitted binary address 10 (e.g. A16, A64) belonging to a first category of k for current data processing, whereby a address redundancy is provided, which consists of 2n-k in the second data processing unused addresses of a second category (eg AI ... A15), characterized by a plurality of indication registers (4) connected to the bus, which are activated for reading at receiving each of said 2n addresses and storing each its indication of the two address categories including the address of the register, and a generator (5) connected to said indication register 2 0 to generate an error signal upon receiving an indication that the current address transmitted on the bus belongs to the second category. Device according to claim 1, characterized in that the 2n indication register is assigned to each of said 2n addresses. 3. Device according to claim 1, characterized by 2 n-k indication registers, which are assigned to each address of their second category. 4. Apparatus according to claim 1, characterized by e-signatures, which are assigned to each address of its first category. 6 86433