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ES2038928A2 - Sistema de tratamiento de acceso en procesador de informacion. - Google Patents

Sistema de tratamiento de acceso en procesador de informacion.

Info

Publication number
ES2038928A2
ES2038928A2 ES929200412A ES9200412A ES2038928A2 ES 2038928 A2 ES2038928 A2 ES 2038928A2 ES 929200412 A ES929200412 A ES 929200412A ES 9200412 A ES9200412 A ES 9200412A ES 2038928 A2 ES2038928 A2 ES 2038928A2
Authority
ES
Spain
Prior art keywords
information processor
access
processing system
address bus
access processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
ES929200412A
Other languages
English (en)
Other versions
ES2038928R (es
ES2038928B1 (es
Inventor
Kiyoshi Sudo
Yasumomo Sakurai
Koichi Odahara
Kenji Hoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of ES2038928A2 publication Critical patent/ES2038928A2/es
Publication of ES2038928R publication Critical patent/ES2038928R/es
Application granted granted Critical
Publication of ES2038928B1 publication Critical patent/ES2038928B1/es
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Storage Device Security (AREA)

Abstract

SISTEMA DE TRATAMIENTO DE ACCESO EN PROCESADOR DE INFORMACION, INCLUYENDO EL PROCESADOR: UN DISPOSITIVO DE ACCESO (10, 11) PARA GENERAR UNA SEÑAL DE PETICION DE ACCESO; UN DISPOSITIVO ACCEDIDO (13) PROVISTO DE MEDIOS DE MEMORIA (30) QUE SON ACCEDIDOS POR EL DISPOSITIVO DE ACCESO (10, 11); Y UNA LINEA GENERAL DE DIRECCION (14) QUE TIENE EL DISPOSITIVO DE ACCESO Y EL DISPOSITIVO ACCEDIDO CONECTADOS CON EL PROCESADOR DE INFORMACION AL MENOS POR LA LINEA GENERAL DE DIRECCION (14). EL SISTEMA DE TRATAMIENTO DE ACCESO ES TRATADO DE TAL MANERA QUE, SI SE PRODUCE UNA PETICION DE ACCESO, CUANDO LA SEÑAL DE PETICION DE ACCESO NO REQUIERE TODOS LOS BITS DE LA LINEA GENERAL DE DIRECCION (14), SE CARGA UN BIT NO UTILIZADO EN LA LINEA GENERAL DE DIRECCION (14) CON DATOS DE ESCRITURA PARA ENTREGARLOS AL DISPOSITIVO ACCEDIDO.
ES09200412A 1991-02-26 1992-02-25 Sistema de tratamiento de acceso en procesador de informacion. Expired - Fee Related ES2038928B1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3030503A JPH04270440A (ja) 1991-02-26 1991-02-26 アクセス方式

Publications (3)

Publication Number Publication Date
ES2038928A2 true ES2038928A2 (es) 1993-08-01
ES2038928R ES2038928R (es) 1996-02-01
ES2038928B1 ES2038928B1 (es) 1997-04-01

Family

ID=12305623

Family Applications (1)

Application Number Title Priority Date Filing Date
ES09200412A Expired - Fee Related ES2038928B1 (es) 1991-02-26 1992-02-25 Sistema de tratamiento de acceso en procesador de informacion.

Country Status (3)

Country Link
US (1) US5327539A (es)
JP (1) JPH04270440A (es)
ES (1) ES2038928B1 (es)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2273180A (en) * 1992-12-02 1994-06-08 Ibm Database backup and recovery.
FR2717921B1 (fr) * 1994-03-24 1996-06-21 Texas Instruments France Dispositif de gestion de conflit d'accès entre un CPU et des mémoires.
JPH096720A (ja) * 1995-06-15 1997-01-10 Canon Inc 情報伝送方法および情報伝送システム
US6801868B1 (en) * 2002-10-15 2004-10-05 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Real time calibration method for signal conditioning amplifiers

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4523272A (en) * 1981-04-10 1985-06-11 Hitachi, Ltd. Bus selection control in a data transmission apparatus for a multiprocessor system
EP0165822A2 (en) * 1984-06-21 1985-12-27 Fujitsu Limited Memory access control system
EP0284981A2 (en) * 1987-04-01 1988-10-05 International Business Machines Corporation Addressing in a computer system
US4797815A (en) * 1985-11-22 1989-01-10 Paradyne Corporation Interleaved synchronous bus access protocol for a shared memory multi-processor system
EP0427425A2 (en) * 1989-11-03 1991-05-15 Compaq Computer Corporation Improved paged memory controller

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5056015A (en) * 1988-03-23 1991-10-08 Du Pont Pixel Systems Limited Architectures for serial or parallel loading of writable control store
US5261073A (en) * 1989-05-05 1993-11-09 Wang Laboratories, Inc. Method and apparatus for providing memory system status signals

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4523272A (en) * 1981-04-10 1985-06-11 Hitachi, Ltd. Bus selection control in a data transmission apparatus for a multiprocessor system
EP0165822A2 (en) * 1984-06-21 1985-12-27 Fujitsu Limited Memory access control system
US4797815A (en) * 1985-11-22 1989-01-10 Paradyne Corporation Interleaved synchronous bus access protocol for a shared memory multi-processor system
EP0284981A2 (en) * 1987-04-01 1988-10-05 International Business Machines Corporation Addressing in a computer system
EP0427425A2 (en) * 1989-11-03 1991-05-15 Compaq Computer Corporation Improved paged memory controller

Also Published As

Publication number Publication date
JPH04270440A (ja) 1992-09-25
ES2038928R (es) 1996-02-01
US5327539A (en) 1994-07-05
ES2038928B1 (es) 1997-04-01

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 20040916