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EP2901294A4 - Network on a chip socket protocol - Google Patents

Network on a chip socket protocol

Info

Publication number
EP2901294A4
EP2901294A4 EP13842232.4A EP13842232A EP2901294A4 EP 2901294 A4 EP2901294 A4 EP 2901294A4 EP 13842232 A EP13842232 A EP 13842232A EP 2901294 A4 EP2901294 A4 EP 2901294A4
Authority
EP
European Patent Office
Prior art keywords
network
chip socket
socket protocol
protocol
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP13842232.4A
Other languages
German (de)
French (fr)
Other versions
EP2901294A1 (en
Inventor
Philippe Boucard
Jean-Jacques Lecler
Boris Boutillier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Technologies Inc
Original Assignee
Qualcomm Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/626,758 external-priority patent/US9471538B2/en
Priority claimed from US13/626,766 external-priority patent/US9225665B2/en
Application filed by Qualcomm Technologies Inc filed Critical Qualcomm Technologies Inc
Priority to EP22196229.3A priority Critical patent/EP4123468A1/en
Publication of EP2901294A1 publication Critical patent/EP2901294A1/en
Publication of EP2901294A4 publication Critical patent/EP2901294A4/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/403—Bus networks with centralised control, e.g. polling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/1735—Network adapters, e.g. SCI, Myrinet
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7825—Globally asynchronous, locally synchronous, e.g. network on chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)
  • Computer And Data Communications (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
EP13842232.4A 2012-09-25 2013-09-24 Network on a chip socket protocol Ceased EP2901294A4 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP22196229.3A EP4123468A1 (en) 2012-09-25 2013-09-24 Network on a chip socket protocol

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/626,758 US9471538B2 (en) 2012-09-25 2012-09-25 Network on a chip socket protocol
US13/626,766 US9225665B2 (en) 2012-09-25 2012-09-25 Network on a chip socket protocol
PCT/US2013/061295 WO2014052261A1 (en) 2012-09-25 2013-09-24 Network on a chip socket protocol

Related Child Applications (1)

Application Number Title Priority Date Filing Date
EP22196229.3A Division EP4123468A1 (en) 2012-09-25 2013-09-24 Network on a chip socket protocol

Publications (2)

Publication Number Publication Date
EP2901294A1 EP2901294A1 (en) 2015-08-05
EP2901294A4 true EP2901294A4 (en) 2016-08-10

Family

ID=50388890

Family Applications (2)

Application Number Title Priority Date Filing Date
EP13842232.4A Ceased EP2901294A4 (en) 2012-09-25 2013-09-24 Network on a chip socket protocol
EP22196229.3A Pending EP4123468A1 (en) 2012-09-25 2013-09-24 Network on a chip socket protocol

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP22196229.3A Pending EP4123468A1 (en) 2012-09-25 2013-09-24 Network on a chip socket protocol

Country Status (6)

Country Link
EP (2) EP2901294A4 (en)
JP (1) JP6144348B2 (en)
KR (1) KR101690568B1 (en)
CN (1) CN104685480B (en)
IN (1) IN2015MN00441A (en)
WO (1) WO2014052261A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2529217A (en) 2014-08-14 2016-02-17 Advanced Risc Mach Ltd Transmission control checking for interconnect circuitry
US11436185B2 (en) * 2019-11-15 2022-09-06 Arteris, Inc. System and method for transaction broadcast in a network on chip
CN117389931B (en) * 2023-12-12 2024-05-03 芯动微电子科技(武汉)有限公司 Protocol conversion module and method suitable for bus access to GPU (graphics processing unit) nuclear memory

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6826191B1 (en) * 1999-10-01 2004-11-30 Stmicroelectronics Ltd. Packets containing transaction attributes
US20080313365A1 (en) * 2007-06-14 2008-12-18 Arm Limited Controlling write transactions between initiators and recipients via interconnect logic

Family Cites Families (21)

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US6477646B1 (en) * 1999-07-08 2002-11-05 Broadcom Corporation Security chip architecture and implementations for cryptography acceleration
US8087064B1 (en) * 2000-08-31 2011-12-27 Verizon Communications Inc. Security extensions using at least a portion of layer 2 information or bits in the place of layer 2 information
WO2002069575A1 (en) * 2001-02-28 2002-09-06 Gotham Networks, Inc. Methods and apparatus for network routing device
US6996651B2 (en) * 2002-07-29 2006-02-07 Freescale Semiconductor, Inc. On chip network with memory device address decoding
US7277449B2 (en) * 2002-07-29 2007-10-02 Freescale Semiconductor, Inc. On chip network
US6671275B1 (en) * 2002-08-02 2003-12-30 Foundry Networks, Inc. Cross-point switch with deadlock prevention
EP1552669B1 (en) * 2002-10-08 2007-09-19 Koninklijke Philips Electronics N.V. Integrated circuit and method for establishing transactions
US7181556B2 (en) * 2003-12-23 2007-02-20 Arm Limited Transaction request servicing mechanism
US7613849B2 (en) * 2004-03-26 2009-11-03 Koninklijke Philips Electronics N.V. Integrated circuit and method for transaction abortion
US7716409B2 (en) * 2004-04-27 2010-05-11 Intel Corporation Globally unique transaction identifiers
CN101366245A (en) * 2005-09-13 2009-02-11 Ist国际公司 System and method for supporting flexible overlays and mobility in ip communication and computer networks
WO2007033363A2 (en) * 2005-09-13 2007-03-22 Ist International, Inc. System and method for providing packet connectivity between heterogeneous networks
US20070245033A1 (en) * 2006-04-14 2007-10-18 Microsoft Corporation Link layer discovery and diagnostics
JP2010500807A (en) * 2006-08-08 2010-01-07 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Electronic device and communication control method
US8285912B2 (en) * 2009-08-07 2012-10-09 Arm Limited Communication infrastructure for a data processing apparatus and a method of operation of such a communication infrastructure
FR2951342B1 (en) * 2009-10-13 2017-01-27 Arteris Inc NETWORK ON CHIP WITH NULL LATENCY
EP2333830B1 (en) * 2009-12-07 2014-09-03 STMicroelectronics (Research & Development) Limited a package comprising a first and a second die coupled by a multiplexed bus
EP2388707B1 (en) * 2010-05-20 2014-03-26 STMicroelectronics (Grenoble 2) SAS Interconnection method and device, for example for systems-on-chip
WO2011148925A1 (en) * 2010-05-24 2011-12-01 日本電気株式会社 Semiconductor device and network routing method and system
FR2961048B1 (en) * 2010-06-03 2013-04-26 Arteris Inc CHIP NETWORK WITH QUALITY-OF-SERVICE CHARACTERISTICS
EP2444903A1 (en) * 2010-09-29 2012-04-25 STMicroelectronics (Grenoble 2) SAS A transaction reordering arrangement

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6826191B1 (en) * 1999-10-01 2004-11-30 Stmicroelectronics Ltd. Packets containing transaction attributes
US20080313365A1 (en) * 2007-06-14 2008-12-18 Arm Limited Controlling write transactions between initiators and recipients via interconnect logic

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
MASOUD DANESHTALAB ET AL: "A Low-Latency and Memory-Efficient On-chip Network", NETWORKS-ON-CHIP (NOCS), 2010 FOURTH ACM/IEEE INTERNATIONAL SYMPOSIUM ON, IEEE, PISCATAWAY, NJ, USA, 3 May 2010 (2010-05-03), pages 99 - 106, XP031707260, ISBN: 978-1-4244-7085-3 *
MASOUD DANESHTALAB ET AL: "Memory-Efficient On-Chip Network With Adaptive Interfaces", IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, IEEE, USA, vol. 31, no. 1, 1 January 2012 (2012-01-01), pages 146 - 159, XP011390021, ISSN: 0278-0070, DOI: 10.1109/TCAD.2011.2160348 *
See also references of WO2014052261A1 *
SEIFI M R ET AL: "A clustered NOC in group communication", TENCON 2008 - 2008, TENCON 2008. IEEE REGION 10 CONFERENCE, IEEE, PISCATAWAY, NJ, USA, 19 November 2008 (2008-11-19), pages 1 - 5, XP031414565, ISBN: 978-1-4244-2408-5 *
WOO-CHEOL KWON ET AL: "In-network reorder buffer to improve overall NoC performance while resolving the in-order requirement problem", DESIGN, AUTOMATION&TEST IN EUROPE CONFERENCE&EXHIBITION, 2009. DATE '09, IEEE, PISCATAWAY, NJ, USA, 20 April 2009 (2009-04-20), pages 1058 - 1063, XP032317643, ISBN: 978-1-4244-3781-8, DOI: 10.1109/DATE.2009.5090821 *
XU YANG, ZHANG QING LI, FU FANG-FA , YU MING-YAN, LIU CHENG: "NISAR: An AXI Compliant On-chip NI Architecture OfferingTransaction Reordering Processing", 25 October 2007 (2007-10-25), XP002759391, Retrieved from the Internet <URL:http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4415774> [retrieved on 20160630] *

Also Published As

Publication number Publication date
KR20150063433A (en) 2015-06-09
WO2014052261A1 (en) 2014-04-03
EP4123468A1 (en) 2023-01-25
IN2015MN00441A (en) 2015-09-11
KR101690568B1 (en) 2016-12-28
JP2015535991A (en) 2015-12-17
CN104685480B (en) 2017-07-14
EP2901294A1 (en) 2015-08-05
JP6144348B2 (en) 2017-06-07
CN104685480A (en) 2015-06-03

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