EP1836526A1

EP1836526A1 - Capacitive junction modulator, capacitive junction and method for making same

Info

Publication number: EP1836526A1
Application number: EP05825964A
Authority: EP
Inventors: Sylvain David; Emmanuel Hadji
Original assignee: Commissariat a lEnergie Atomique CEA
Current assignee: Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date: 2004-12-16
Filing date: 2005-12-14
Publication date: 2007-09-26
Also published as: WO2006064124A1; FR2879820A1; US20080203506A1; JP2008524644A; FR2879820B1

Abstract

The invention concerns a capacitive junction comprising a region (16) adapted to be traversed by an electromagnetic wave, and a dielectric layer (14) interposed between two semiconductor material layers. The dielectric layer (14) has a reduced thickness at said region (16), that is a thickness at said region less than its thickness at a contact of the junction. Such a junction is for instance used to form a modulator. The invention also concerns a method for making such a junction.

Description

Capacitive junction modulator, capacitive junction and method for producing same

The invention relates to a capacitive junction modulator, for example an optical modulator, a capacitive junction and its method of production.

Modulator means a device capable of varying the intensity of an electromagnetic wave (eg light) passing through it, possibly in a binary manner: it may therefore be a switch. We seek nowadays to realize modulators (including optical) that can be integrated with microelectronic circuits, that is to say obtained by means directly applicable to manufacturing processes used in the silicon industry.

In this context, it has been proposed to use the physical property according to which the refractive index of a material can be modified by varying the density of the carriers in this material.

This property is for example used in the capacitive pn type junctions constituted by an oxide barrier interposed between two p-doped silicon layers and n respectively. A solution of this type is described, for example, in the article "A high-speed silicon optical modulator based on a metal oxide semiconductive capacitance", by A. Liu et al., In Nature, vol. 427, February 12, 2004.

In this type of solution, the electrical contacts are made by materials or large dopings which cause high optical losses and it is therefore desirable to move these electrical contacts away from the region where the luminous flux passes through the capacitive junction in order to reduce optical losses of the component.

For a given carrier density at the capacitive junction, this distance generates an increase in the power consumed, especially in the case where the capacitive junction extends from the region where it passes through the luminous flux to the electrical contacts. .

Moreover, the silicon layer deposited on the silicon oxide barrier layer is polycrystalline; this property generates optical losses. The invention therefore aims in particular at a capacitive junction modulator whose electrical contacts can be sufficiently far from the region of the capacitive junction traversed by the electromagnetic wave without this distance causing a problematic increase in the power consumed for a carrier density. given at the level of this same region.

The invention proposes a modulator comprising a capacitive junction crossed by an electromagnetic wave, the capacitive junction comprising a dielectric layer interposed between two layers of semiconductor material, characterized in that the dielectric layer has a thickness reduction at the level of electromagnetic wave, that is to say that the dielectric layer has a thickness (strictly) less than this level with respect to its thickness at a contact of the junction.

The reduction in thickness of the dielectric layer locally causes the formation of a more intense electric field, which allows a higher concentration of charge carriers in this region traversed by the electromagnetic wave.

In other words, for a given carrier concentration in the region traversed by the electromagnetic wave, there will be a lower concentration of carriers outside this region and therefore a reduced power consumption of the junction.

According to particularly practical and possibly combined implementation possibilities, at least one of said layers of semiconductor material is doped, at least one of said layers of semiconductor material is made of silicon and the dielectric layer is made of silicon oxide or insulating polymer. . Advantageously, the silicon layers are monocrystalline in order to limit the optical losses.

Each of said layers of semiconductor material may have a thickness of between 30 nm and 500 nm, while the dielectric layer may have a thickness of between 2 nm and 30 nm outside said reduction in thickness. Such dimensions further facilitate the integration of the modulator into a system made of thin layers.

According to one possible implementation, the thickness reduction is greater than 20%, for example between 20% and 60%, in order to generate the effect described above optimally. For example, for a layer 30 nm thickness dielectric outside the thickness reduction, a thickness reduction of 60% leads to a reduced thickness of about 10 nm.

In order to further improve the efficiency of the modulator and according to an original concept in itself, the modulator may comprise a plurality of dielectric layers separated by layers made of semiconductor material and each traversed over at least a portion by the electromagnetic wave. .

In this way, a stack of capacitive junctions is used which makes it possible to multiply the modulation effect in the direction of the thickness of the layers. The invention also proposes as such a capacitive junction which comprises a region capable of being traversed by an electromagnetic wave, the capacitive junction comprising a dielectric layer interposed between two layers of semiconductor material, characterized in that the dielectric layer exhibits a thickness reduction at said region, i.e., its thickness at said region is (strictly) less than its thickness at a contact of the junction.

The capacitive junction thus proposed may also possess the optional characteristics already presented for the capacitive junction of the modulator and the advantages that result therefrom. The invention finally proposes a method for producing a capacitive junction, characterized in that it comprises the following steps:

etching of a region of a layer in contact with a semiconductor material, said etching being initiated in said layer outside said region, filling of the etched space with a dielectric material.

According to an embodiment possibility, which said layer is interposed between two layers of semiconductor material which then form with the dielectric material the capacitive junction.

Each of said layers of semiconductor material has for example a thickness of between 30 nm and 500 nm.

As for it, said layer has a thickness of between 1 nm and 15 nm, which makes it possible, after etching and filling, to obtain a dielectric layer with a thickness of between 2 nm and 30 nm, as already indicated. According to a possibility of implementing the method, it also comprises a step of forming access holes to said layer outside said region, the etching being initiated by these holes.

This solution is particularly practical, especially when the capacitive junction is used as a modulator within a photonic crystal whose holes can be made during said hole-forming step.

Other characteristics and advantages of the invention will appear better in the light of the following description given with reference to the appended drawings, in which: FIGS. 1 to 7 show a method for producing a capacitive junction for an optical modulator according to a first embodiment of the invention;

FIG. 8 represents a stack of capacitive junctions according to a second embodiment of the invention. A first embodiment of the invention is now described with reference to FIGS. 1 to 7.

FIG. 1 represents a structure formed by a stack of layers which comprises:

a first layer 2 of semiconductor material, for example p-doped silicon (hereinafter referred to as "Si-p layer") which could for example be a substrate, but whose thickness is here limited, for example to 500 nm;

a second layer 4 which covers the first layer 2 and is made of a material which is relatively close to that of the first layer (here for example silicon-germanium SiGe), but which is more easily removed as described below, with a thickness for example between 1 nm and 15 nm;

- A third layer 6 made of semiconductor material, here n-doped silicon (this third layer 6 is therefore referred to in sequence "Si-n layer") of thickness 50 nm for example. The layered structure is for example made by successive deposition of the second layer 4 and the third layer 6 on the first layer 2, or alternatively by epitaxy so as to obtain a second and a third monocrystalline layers 4, 6. The layered structure is deposited on a substrate which gives it a mechanical strength, for example a SOI ("Silicon On Insulator") substrate or a quartz substrate.

Two holes 8, for example cylindrical, with axes perpendicular to the free surface of the third layer 6 are produced in the structure which has just been described, and precisely in two regions thereof separated by a central region 7. that is to say also at the interface between each pair of layers), which extend vertically over the entire depth of the third layer 6, the second layer 4 and the first layer 2. Each of the separate regions by the central region 7 has a plurality of holes (typically of the order of magnitude of ten or dozens of holes), which allows to give access from the outside (that is to say the face free of the third layer 6) to the second layer 4 over the entire aforementioned region, retaining the general mechanical structure of the third layer 6 in the same region.

This set of holes could also be provided by the presence of a photonic crystal where the holes may be of circular, square or other shape depending on the desired properties of the photonic crystal. This set of holes can also be presented as the repetition of the same hole, a set of holes, or as a compact aperiodic structure (that is to say non-periodic).

But for the sake of convenience, it may be preferred to make the holes of cylindrical or square section according to a simple triangular or square periodic network, where each hole will advantageously submicrometer size.

The structure shown in section is thus obtained by a vertical plane A-A in FIG. 2 and in plan view in FIG.

We then proceed to the next step of attacking the second layer 4 (made of SiGe in the example described here) by etching, for example wet with a mixture of hydrofluoric acid, acetic acid and hydrogen peroxide, as described for example in document "Chemical etching of Si ₁ ^ Ge _x in HF: H ₂ O _2: CH ₃ ^COOH" TK Carns et al. in J. Electrochem. Soc., Vol. 142, No. 4, April 1995. An n-type doping of the second layer 4 (Made of SiGe) can be provided during the formation of this layer to promote such etching.

Alternatively, one could use a dry etching of CF ₄ isotropic plasma etching type. Reference can be made to patent application FR 2 795 554 for more details on this type of process, used in this document in a different application.

Whichever method is used, this first leads to the elimination of the second layer 4 in each of the regions provided with the cylindrical holes 8, which starts the formation of cavities 9 instead of the second layer 4 in these regions, and secondly to attack the residual portions of the second layer 4 by etching action from the cavities 9, so that the portions of the second layer 4 located at the central region 7 are eliminated to form an extension 10 of each cavity 9. A passage 12 is thus formed between the two cavities 9 via their respective extension 10.

If the etching used primarily attacks the second layer 4 made of SiGe as has just been described, it also attacks, although more lightly, the layers in contact with the second layer 4, namely the first layer 2 and the third layer 6.

However, because of the slower metabolism of the etching reaction with the first layer 2 and the third layer 6 formed of silicon, the thickness of etched material will strongly depend on the exposure time of the zone considered to the reactive product so that that the parts of these layers 2, 6 located in the vicinity of the cylindrical holes 8 (through which the reagents penetrate) will be etched noticeably (which leads to an enlargement of the cavities 9); for example, with dry etching based on CF ₄ , the trimmed thickness is typically of the order of 10 to 50 nm for a lateral etching of 150 nm. On the contrary, the parts of these layers 2, 6 located at the central region 7 will be less etched as one moves away from the region of the cylindrical holes 8.

As a result, the lengths of the cavities 9 have a thickness which varies between the thickness of the cavity concerned 9 at the level of the latter at a thickness of the order of the initial thickness of the second layer 4 at the level of the passage 12 (where the etching of the silicon layers 2, 6 has hardly taken place).

A structure as shown in section is thus obtained in FIG. 4. It may be noted that the thickness reduction of the extensions 10 and of the passage 12 at the central region 7 and the shape of this reduction in thickness can be controlled. by playing on the concentration of germanium (Ge) of the second layer 4 made of SiGe. By varying the germanium concentration as a function of the depth in the layer, the rate of elimination of the second layer 4 is influenced as a function of the depth in question, which makes it possible to act on the profile of the extensions 10 in section. vertical.

For example, a uniform concentration of germanium in the second layer 4 will generate an abrupt profile between the portions of the extensions 10 generated by the only removal of the second layer 4 (parts near the passage 12) and the portions of the extensions 10 generated by the combination the removal of the second layer 4 and the attack of the layer 2,6 of Si-n or Si-p concerned.

On the contrary, a continuous variation of the germanium concentration at the passage of the doped silicon layer 2,6 concerned to the second layer 4 will allow a more even transition between the portion of the passage 12 formed by the elimination of the second layer 4 and the extensions 10 formed by the combination of the elimination of this same layer 4 and the attack of neighboring layers 2,6.

Once the cavities 9, the extensions 10 and the passage 12 formed as previously described, the cavities previously formed (cavities 9 and their extensions 10) and the residual portions of the cylindrical holes 8 are filled with a dielectric material 14.

This filling is for example carried out by infiltration of an insulator or by thermal oxidation of the structure (which causes the filling of the cavities with silicon dioxide), according to techniques used in other applications, as described for example in the application FR 2,800,913.

This gives the structure shown in section in Figure 5 and which thus comprises the basic elements of a capacitive junction (doped silicon layers separated by a dielectric material 14). The external parts of the regions provided with holes (with respect to the central region 7) are then etched so as to eliminate any residues of the second SiGe layer 4 and to obtain a thickness insulator profile 14. constant except at the central region 7 where the insulation thickness 16 is reduced as a consequence of the shape of the previously exposed extensions 10.

The structure thus obtained is shown in FIG. 6. It is then possible to proceed with the deposition of contacts on the one hand at the level of the third layer 6 (which retains an overall layer structure despite the presence of insulating material at the places where have been etched the cylindrical holes 8), and secondly on the upper face of the first layer 2 exposed during the previous etching step.

A capacitive junction has thus been formed which comprises the first layer 2 made of Si-p and the third layer 6 made of Si-n separated by an intermediate layer 14 made of insulating material which comprises a thickness reduction 16 at the level of the region. central 7, in particular with respect to the thickness of this same layer in the peripheral zone which carries the contacts.

The thickness reduction here is of the order of 20 to 60% because of the cavity forming process presented above.

This reduction in thickness 16, which causes a more intense electric field at the central region 7, allows a high concentration of charge carriers in the central region 7 and the capacitive junction thus produced is therefore particularly suitable for the production of a modulator, for example an optical modulator.

Such a modulator can easily be realized within an integrated optical structure, the waveguides of which are formed by photonic crystal microcavities. In this case, the width of the zone of reduced thickness 16 within the dielectric layer 14 is of the order of the width of the waveguide microcavity. This solution also makes it possible to etch the holes 8 used in the process described above in the same technological step as the holes that form the photonic crystal in the silicon.

FIG. 8 represents a second embodiment of the invention in which a stack of capacitive junctions is used as described below.

Such a multi-junction structure comprises alternating layers 22, 26 made of p-doped semiconductor material and layers 24, 28 of material n doped set-conductor, between each of which is interposed a dielectric layer 30.

In the example shown in FIG. 8, the multi-junction structure comprises two p-doped silicon layers 22, 26 (hereinafter referred to as Si-p layers 22, 26) and two n-doped silicon layers 24, 28 (FIG. hereinafter called layers 24, 28 of Si-n.

The structure therefore has the following organization:

a layer of Si-β 22;

a dielectric layer 30; a layer of Si-n 24;

a dielectric layer 30;

a layer of Si-β 26;

a dielectric layer 30; and

a layer of Si-n 28. Such a structure is for example obtained by applying the technique described in connection with the first embodiment to the aforementioned layer stack, which does not imply any additional technological step. relative to the case where a single junction is made as described with reference to Figures 1 to 7. As a result, the doped silicon layers are traversed by holes

23 filled with dielectric material in two regions separating a central region

21, 25, 27, 29 of each layer 22, 24, 26, 28.

Each dielectric layer 30 comprises a reduction in thickness at the central portion 21, 25, 27, 29 of the layers 22, 24, 26, 28 which adjoin it. These reductions in thickness are for example obtained by using the technique described in connection with the first embodiment for producing each dielectric layer 30.

Lateral etchings of the same type as those proposed in the first embodiment make it possible to expose the upper face of each of the doped silicon layers 22, 24, 26, 28 and thus to form electrical contacts 32, 34, 36, 38 with each of these upper faces.

By feeding the multi-junction structure which has just been described by means of the electrical contacts 32, 34, 36, 38, it is possible to control the accumulation of the charge carriers present in the doped silicon layers 22, 24, 26, 28 , which will be concentrated in particular at the level of the central region 21, 25, 27, 29 of each layer by virtue of the reduction in thickness of the dielectric layer 30 concerned: a particularly effective optical modulator is thus obtained thanks to this concentration of the carriers of charges in the central regions 21, 25, 27, 29 and the superposition of the capacitive junctions which makes it possible to obtain the modulation effect over a relatively large thickness.

In order to obtain an even better accumulation of the charge carriers in each of the junctions, the whole of this junction is connected in parallel by linking the contacts 32, 36 associated with the Si-p layers 22, 26 to a same terminal. a voltage generator and the contacts 34, 38 associated with the Si-n layers 24, 28 at the opposite terminal of this generator.

The products and processes presented above are only non-limiting examples of implementation of the invention.

Claims

A modulator comprising a capacitive junction traversed by an electromagnetic wave, the capacitive junction comprising at least one contact and a dielectric layer (14; 30) interposed between two semiconductor material layers (2,6; 22,24,26,28). characterized in that the dielectric layer (14; 30) has a lower thickness (16; 21,25,27,29) at the electromagnetic wave at its thickness at the contact.

The modulator according to claim 1, wherein at least one of said layers of semiconductor material (2,6; 22,24,26,28) is doped.

A modulator according to claim 1 or 2, wherein at least one of said layers of semiconductor material (2,6; 22,24,26,28) is made of silicon.

4. Modulator according to one of claims 1 to 3, wherein the dielectric layer (14; 30) is made of silicon oxide or insulating polymer.

5. Modulator according to one of claims 1 to 4, wherein each of said layers of semiconductor material (2,6; 22, 24, 26, 28) has a thickness between 30 nm and 500 nm.

6. Modulator according to one of claims 1 to 5, wherein the dielectric layer (14; 30) has a thickness between 2 nm and 30 nm outside said thickness reduction (16; 21, 25, 27, 29).

7. Modulator according to one of claims 1 to 6, wherein said reduction in thickness (16; 21, 25, 27, 29) is between 20% and 60%.

8. Modulator according to one of claims 1 to 7, comprising a plurality of dielectric layers (30) separated by layers made of semiconductor material (22, 24, 26, 28) and each traversed over at least a portion by the electromagnetic wave.

A capacitive junction comprising a region capable of being traversed by an electromagnetic wave, the capacitive junction comprising a contact and a dielectric layer (14; 30) interposed between two layers of semiconductor material (2,6; 22,24,26,28). characterized in that the dielectric layer (14; 30) has a thickness (16; 21,25,27,29) at said region less than its thickness at the contact.

The capacitive junction of claim 9, wherein at least one of said layers of semiconductor material (2,6; 22,24,26,28) is doped.

Capacitive junction according to claim 9 or 10, wherein at least one of said layers of semiconductor material (2,6; 22,24,26,28) is made of silicon.

12. Capacitive junction according to one of claims 9 to 11, wherein the dielectric layer (14; 30) is made of silicon oxide or insulating polymer.

13. Capacitive junction according to one of claims 9 to 12, wherein each of said layers of semiconductor material (2,6; 22, 24, 26, 28) has a thickness of between 30 nm and 500 nm.

14. The capacitive junction according to one of claims 9 to 13, wherein the dielectric layer (14; 30) has a thickness of between 2 nm and 30 nm outside said thickness reduction (16; 21, 25, 27). , 29).

15. A capacitive junction according to one of claims 9 to 14, wherein said reduction in thickness (16; 25,27,29) is between 20% and 60%.

16. A method of producing a capacitive junction, characterized in that it comprises the following steps:

etching a region of a layer (4) in contact with a semiconductor material (2, 6), said etching being initiated in said layer outside said region,

- filling the etched space with a dielectric material (14).

17. The method of claim 16, wherein said layer (4) is interposed between two layers of semiconductor material (2,6).

18. The method of claim 17, wherein each of said layers of semiconductor material (2,6) has a thickness between 30 nm and 500 nm.

19. Method according to one of claims 16 to 18, wherein said layer (4) has a thickness between 1 nm and 15 nm.

20. Method according to one of claims 16 to 19, further comprising a step of forming holes (8) for access to said layer (4) outside said region, the etching being initiated by these holes (8). .