EP1889435A1 - Differential detection unit for the zigbee ieee 802.15.4 standard - Google Patents

Abstract

The invention relates to a method for detecting data symbols contained in a received radio signal, a PN sequence that is specific for a symbol value being assigned to each data symbol from PN chips succeeding each other at the chip clock pulse at the transmission end, and the PN sequences assigned to the data symbols being offset QPSK modulated. According to the inventive incoherent detection method, the received radio signal is converted into a complex baseband signal sampled at the chip clock pulse, a demodulated signal is generated by differentially demodulating the complex baseband signal sampled at the chip clock pulse, derived sequences are provided, correlation results are calculated by correlating the demodulated signal with the derived sequences, and the values of the data symbols are derived, i.e. detected, by evaluating the correlation results, each derived sequence being allocated to a PIM sequence that can be assigned at the transmission end and being composed of derived chips whose values correspond to one respective logical combination of respective PN chips of the PN sequence which can be assigned at the transmission end and to which the derived sequence is allocated. The invention further relates to a corresponding receive unit.

Description

DIFFERENTIAL DETECTION UNIT FOR THE ZIGBEE IEEE 802. 15. 4 STANDARD

The present invention relates to a method and a receiving unit for detecting data symbols contained in a received radio signal. The invention broadly relates to a transmitting receiving device and an integrated circuit having such a receiving unit.

The invention is in the field of data transmission. Although applicable in principle to any digital communication systems, the present invention and the problem on which it is based are explained below on the basis of a "ZigBee" communication system according to IEEE 802.15.4.

For wireless transmission of information over relatively short distances (about 10m) so-called "Wireless Personal Area Networks" (WPANs) can be used, in contrast to "Wireless Local Area Networks" (WLANs) require WPANs for data transmission little or no infrastructure so that small, simple, energy-efficient and cost-effective devices can be implemented for a wide range of applications.

The IEEE 802.15.4 standard specifies low-speed WPANs that can be programmed with raw data rates up to max. 250 kbit / s and fixed or mobile devices are suitable for applications in industrial monitoring and control, in sensor networks, in automation, as well as in the field of computer peripherals and for interactive games. In addition to a very simple and cost-effective implementa- tion of the devices, extremely low energy consumption of the devices is of crucial importance for such applications. For example, battery life of several months to several years is the goal of this standard.

At the physical layer level, the IEEE standard 802.15.4 specifies 2.4 GHz spread spectrum for a raw data rate of fB = 250 kbit / s in the almost worldwide available ISM (industrial, scientific, medical) band of fC = 2 Mchip / s and an offset QPSK lviodulation (quartemary phase shift keying) with a symbol rate of fS = 62.5 ksymbol / s. in an 802.15.4 transmitter for the ISM band, the data stream to be transmitted is first converted to a sequence of pseudo-noise (PN) sequences using four bits of data in each symbol period (TS = i / fS = i6μs) a Select a total of 16 PIM sequences. Each symbol of four data bits is assigned in this way a symbol-value-specific PN sequence of 32 PN chips (chip period TC = TS / 32 = 500 ns = i / fC), which is transmitted instead of the four data bits. The "quasi-orthogonal" PIM sequences PO, P1, ..., P15 specified in the standard differ from each other by cyclic shifts and / or inversion of every other chip value (see IEEE std 802.15.4-2003, chapter 6.5.2.3) ,

The PN sequences assigned to the consecutive symbols are concatenated and then θffset QPSK modulated (quaternary γ phase shift keying) by the half-sine pulse shaping PN-chips of even index (0, 2, 4, ...) the inphase (I) carrier and those odd-index PN chips (1, 3, 5, ...) are modulated onto the quadrature phase (Q) carrier. To form an offset, the quadrature-phase chips are delayed by one chip period TC in relation to the in-phase chips (see IEEE std 802.15.4-2003, chapter 6.5.2.4). For detection of data symbols contained in a received signal, both coherent and incoherent approaches are known. While in coherent approaches the received signal is converted into the complex envelope (baseband) with the aid of a carrier wave control derived from a carrier control circuit, in incoherent approaches at least the phase accuracy, possibly also the frequency accuracy of the carrier oscillation, can be dispensed with.

A coherent receiving unit is known from the textbook "Nachrichtübertragung" by Karl-Dirk Kammeyer, 2nd edition, BG Teubner, Stuttgart, ISBN 3-519-16142-7 (Figure 12.1.7 on page 417) On the one hand results from the required carrier control circuit with the associated high-rate (higher than the chip rate) multiplication of the received signal with the frequency and in-phase carrier oscillation and on the other hand from the complex complex signal processing with a high-rate complex matched filtering very high energy consumption.

From the said textbook, an incoherent receiving unit is still known (Figure 12.3.7 on page 447). It has an FM discriminator, an integration unit and a so-called limiter and requires the processing of high-rate (higher than the chip rate) and partially complex-valued signals. This in turn is accompanied by a high implementation cost and high energy consumption. In addition, the performance (symbol error rate, etc.) of this receiving unit is insufficient in the demodulation of MSK signals.

Against this background, the object of the invention is to specify a detection method which makes energy-saving and simple implementations of transceivers, e.g. IEEE 802.15.4 and yet has high detection performance, i. a low error rate (symbol, bit, frame error rate etc.) even under disturbing influences such as channel distortions and / or noise. It is also the object of the invention to specify a corresponding receiving unit as well as a transmitting / receiving device and an integrated circuit.

According to the invention, this object is achieved by a method, a receiving unit, a transmitting receiving device and an integrated circuit having the features of claims 1, 13, 22 and 23. The method according to the invention for the incoherent detection of data symbols contained in a received radio signal, said transmitting side each data symbol assigning a symbol-value-specific PN sequence consisting of PN chips consecutive in chip clock and offset-QPSK-modulating the PN sequences assigned to the data symbols, provides for a) converting (transforming) the received radio signal into a complex baseband signal sampled in the chip clock b) generate a demodulated signal by differentially demodulating the chip base sampled complex baseband signal, c) provide derived sequences, d) calculate correlation results by correlating the demodulated signal with the derived sequences, and e) the values of the data Derive nsymbole by evaluating the correlation results, i. to detect the most likely transmitted data symbols. In this case, each derived sequence is associated with a PN-sequence which can be assigned on the transmitting side and consists of derived chips whose values each correspond to a logical combination of respective PN chips of the PN-sequence assignable to the transmitting end, to which the derived sequence is assigned.

The incoherent receiving unit according to the invention comprises a) an inner

Receiver for transferring the received radio signal into an in

Chip clock sampled complex baseband signal is formed, b) connected to the inner receiver differential demodulator, the C) a sequence providing unit configured to provide derived sequences described above, d) a correlation unit connected to the sequence providing unit and the differential demodulator, for calculating of correlation results by correlating the demodulated signal with the derived sequences, and e) an evaluation unit connected to the correlation unit, which is designed to derive the values of the data symbols by evaluating the correlation results.

The inventive transmitting / receiving device and the integrated circuit according to the invention each have such a receiving unit.

The essence of the invention is to provide from the received radio signal a chip clock sampled baseband signal and to differentially demodulate it and subsequently to correlate with derivative sequences adapted to the differential demodulation. Such differential demodulation in the chip clock allows very simple and energy-saving implementations of the receiving unit or the integrated circuit and thus of the transmitting receiving device, since, on the one hand, no carrier phase control is required and, on the other hand, the entire digital signal processing (incl.) Of demodulation does not require any rates higher than the chip rate. In addition, the use of derived sequences that are not identical to - but derived from - the PN sequences that can be used on the transmitting side, contributes significantly to very simple and energy-saving implementations, since this makes the sequence provisioning, the correlation, and the Extremely easy to implement the evaluation unit. such properties are particularly advantageous if - as in applications in industrial monitoring and control, in sensor networks, in automation or in the field of computer peripherals - an extremely low energy requirement and a very simple feasibility are indispensable. Although the invention is not limited to the IEEE 802.15.4 standard, this is the case with transmit / receive devices for this standard.

The performance of the receiving unit according to the invention or of the method according to the invention is also very high, the error rate (symbol, bit, Frame error rate etc.) during detection even under disturbing influences such as channel distortions and noise are smaller than eg with receiver units with discriminator and limiter. advantageous embodiments and further developments of the invention can be found in the dependent claims and the description with reference to the drawing. In an advantageous embodiment of the method according to the invention or the receiving unit according to the invention, the demodulated signal has soft information values. As a result, the error rate in the detection decreases, so that increases the performance of the method according to the invention or the receiving unit according to the invention. Preferably, a frequency offset after the actual differential demodulation (ie after multiplication of the instantaneous samples with the complex conjugate values of the samples of the chip clock baseband signal delayed by one chip period, respectively) is corrected by multiplication by a complex factor compared to the classical correction of the frequency offset before demodulation (in the so-called inner receiver), the implementation effort and the energy requirement is thereby further reduced because not multiplied by a "rotating pointer" in a higher clock, but only in the chip clock with a complex constant, further is advantageous none full complex multiplication, which would require four real-valued multiplies and two real-valued additions, but only a "half" complex multiplication of two real-valued multiplications and a real-valued addition, since only the imaginary part of the result This is the result of complex multiplication. This further reduces the implementation effort and the energy requirement. Preferably, the differential demodulation or the differential demodulator is designed so that no complex multiplication, but only real-valued operations are performed. With only two real-valued multiplies and a real-valued addition, this makes extremely simple implementations with extremely low energy requirements possible, if a correction of the frequency offset can be dispensed with. In a further advantageous embodiment of the method according to the invention or the receiving unit according to the invention, the correlation calculated such that the demodulated signal in each case (ie per symbol period TS) is correlated with a number of (31) chips of the respective derived sequence, which is one less than the number of (32) chips in each of the transmitting side usable PN sequences. By dispensing with a chip in the correlation calculation, each data symbol can advantageously be decided (detected) independently of the preceding symbol, which further reduces the implementation effort.

According to a further advantageous embodiment, the demodulated signal is equalized and the correlation results calculated by correlating the equalized demodulated signal with the derived sequences, preferably the equalization in this case has a suppression of a DC component. Due to the equalization, the error rate (symbol, bit, frame error rate, etc.) decreases during the detection, so that the performance of the receiving unit according to the invention or of the method according to the invention increases. In a further embodiment, the derived chips (ie the chips of a derived sequence) having a first positive index (ie all chips except the first) each have a value which is an XOR of the PN chip (ie the chip of that PN sequence, which is associated with the derived sequence) with this first positive index with the index-wise (and thus temporally) each preceding PN chip is derivable. Preferably, the index-wise (and time-wise) first derivative (zero-index) chip has a value derivable from an XOR of the index-wise first PN (zero-index) PN chip with the index-last PN chip. By using such derived sequences, the sequence providing unit, the correlation unit and the evaluation unit can be realized in a very simple and energy-saving manner. In another embodiment, the derived chips having an even-numbered index (0,2,4,...) each have a value which is assigned to the (logical) value of the respective XOR combination and the derived chips having an odd-numbered index (FIG. 1,3,5) each have a value associated with the inverted (logical) value of the respective XOR link. Preferably, the logical values (0,1) are assigned antipodal values (+/- 1), eg the logical 1 the value +1 and the logical 0 the value -1. As a result, the realization of the correlation unit is further simplified, since instead of multiple plications with the chip values of the derived chips are advantageous only to perform sign changes.

According to a typical embodiment, the correlation results are evaluated by first determining the index of the correlation result having the maximum value, and then assigning to that index the data symbol whose symbol value is assigned to the PN sequence assignable on the send side, which is the derived sequence is associated with precisely this index. As a result, the data symbols are reliably detected in a simple manner. In a preferred development of the invention, the correlation results are evaluated by determining the maximum correlation value of the correlation results, adding a constant, multiplying the resulting sum by a factor and limiting the (product) values thus obtained to a predetermined value range. The signal quality parameter obtained in this way can advantageously be used by the upper layers of the communication system to increase the reliability of the data transmission.

The invention will be explained in more detail with reference to the exemplary embodiments indicated in the schematic figures of the drawing. Show here

1 shows an example of a "wireless personal area network" (WPAN) according to the IEEE standard 802.15.4 with transmission receiving devices according to the invention; FIG. 2 shows an embodiment of an incoherent receiving unit (RX) according to the invention;

3 realization examples of the differential demodulator 22 of the incoherent receiving unit according to the invention according to FIG. 2;

4 realization example of the evaluation unit 24 of the inventive incoherent receiving unit according to FIG. 2;

5 shows an embodiment of a method according to the invention for incoherent detection;

FIG. 6 shows realization examples of the differential demodulation step S2 of the method according to the invention according to FIG. 5; FIG. Fig. 7 realization example of the evaluation step S6 of the inventive method of FIG. 5. in the figures are the same and functionally identical elements and signals - unless otherwise indicated - provided with the same reference numerals.

1 shows an example of a Wireless Personal Area Network (WPAN) 10 according to the IEEE 802.15.4 standard.It comprises three transceiver devices (TRX) 11-13 in the form of fixed or mobile devices, which by means of The transmission receiving device 11 is a so-called full-function device which performs the function of the WPAN coordinator, while the transmitting / receiving devices 12, 13 are so-called sub-function devices which In addition to the star-shaped network topology illustrated in FIG. 1, in which the bidirectional data transmission only occurs between one of the subfunctioning devices 12, 13 and the fully functional device 11, but not between the subfunction devices 12, 13, the standard also provides for so-called "peer-to-peer" topologies in which all fully functional te (one of which assuming the role of the WPAN coordinator) can communicate with all other full-function devices.

The transmitting receiving devices 11-13 each comprise an antenna 14, a transmitting unit (transmitte TX) 15 connected to the antenna, a receiving unit (receiver, RX) 16 connected to the antenna, and a control unit (control) connected to the transmitting and receiving units unit, CTRL) 17 for

Control of the transmitting and receiving units 15, 16. continue to include the

Transceiver devices 11-13 each one not shown in Figure 1

Energy supply unit in the form of a battery, etc. for powering the units 15-17, and possibly other components such as sensors,

Interfaces etc.

In the following, it is assumed that the data transmission in the ISM band (industrial, scientific, medical) by 2.4 CHz. The transmitting unit 15 of each transmitting / receiving device converts the respective data stream to be transmitted in accordance with the IEEE standard 802.15.4 into a radio signal to be radiated via its antenna 14, by first of all dividing the data stream to be transmitted into four as shown in the introduction to the description Bit wide symbols dθ, dl, d2, ... and these are converted into successive PN sequences (eg P5, P4, P7, if dθ = 5, di = 4, d2 = 7). The successive PM sequences are then offset QPSK (quaternary phase shift keying) with half sine pulse shaping.

Accordingly, the inventive incoherent receiving unit 16 of each transceiver converts a radio signal received from its antenna 14 (and generated by the transmitting unit of another transceiver according to the IEEE 802.15.4 standard) into the transmitted data as error-free as possible by transmitting the Among other things, the radio signal is demodulated and the data is subsequently detected (decided).

The transmitting unit 15 and the receiving unit 16 of a transmitting receiving device are in this case part of an integrated circuit (IC), eg an ASIC (application specific integrated circuit) (not shown in FIG. 1), while the control unit 17 is a microcontroller (likewise not shown) is realized. Advantageously, the transmitting receiving device can also have only one IC (for example embodied as ASIC) which performs the functions of the transmitting unit 15, the receiving unit 16 and the control unit 17. FIG. 2 shows a block diagram of an incoherent receiving unit 16 according to the invention which has the following series-connected functional blocks: an inner receiver (iREC) 21, a differential demodulator (DEMOD) 22, a correlation unit (COR) 23 and an evaluation unit (EVAL) 24 the receiving unit 16 has a sequence providing unit (SEQ) 25, which is connected to the correlation unit 23, and optionally an equalizer (EQ) 26 between the demodulator 22 and the correlation unit 23.

The inner receiver 21 connected to the antenna 14 of the transceiver converts the received radio signal r into a complex baseband signal b (envelope) having complex valued samples at the rate of the PN side PN chip used on the far side, i. in chip clock fC = 2Mip / s = i / TC = i / 500ns. Each complex sample comprises a real part (in-phase component I) and an imaginary part (quadrature component Q), each having a bit width of e.g. have four bits. Depending on the quality of the oscillators used, the complex baseband signal b may be subject to a more or less pronounced frequency offset. Complex-valued signals such as the baseband signal b are shown in the figures by arrows with double lines. The inner receiver 21 also has a synchronization unit (SYNC) 27 which performs symbol and chip clock synchronization and preferably determines a complex factor fOFF required to correct the frequency offset.

The chip clock baseband signal b is then converted by the differential demodulator 22 into a demodulated signal s having real-valued samples in the chip clock, preferably the differential demodulator 22 generates a demodulated signal s whose samples instead of so-called hard bits (ie two-stage, binary values) so-called soft information values (higher-level samples). As a result, the performance of the receiving unit 16 can be further improved; optionally, the differential demodulator 22 can also be advantageously used to correct a frequency offset. The individual functional blocks of the differential demodulator 22 and its mode of operation will be explained in more detail in connection with FIG. The demodulated signal s is then optionally equalized. The equalizer 26 provided for this purpose preferably determines an average value of the demodulated signal s per symbol period τs = i / fs = i6μs = 32 * TC and then releases this by subtracting the mean value from a DC component. Alternatively or additionally, the equalizer 26 may comprise a filter, eg a high-pass filter.

The optionally equalized demodulated signal s or se present in the chip clock fc is then correlated in the correlation unit 23 with so-called derived sequences FO, F1, F2,... Provided by the sequence providing unit 25 and with reference to the table below be explained. This leads to correlation results rsFO, rsFi, rsF2, ..., which represent a measure of the correspondence of the signal s or se with the respective derived sequence FO, F1,..., F15. The correlation results rsFO, rsFi, rsF2, ... are generated in the symbol clock fS = fC / 32 = 62.5 ksymbol / s (corresponds to a symbol period of TS).

Due to differential demodulation, the detection of an up-to-date data symbol requires knowledge of the previous data symbol. Now, in the correlation unit, the correlation results are calculated such that the demodulated signal is respectively correlated with a number of chips (31) of the respective derived sequence one less than the number of chips in each of the transmit-side usable PN sequences (32 ), so by dispensing with a chip in the correlation calculation - without significant losses in the performance of the detection - advantageously each data symbol independently of the previous symbol decided (detected), which further reduces the implementation cost of the receiving unit. in the evaluation unit (EVAL) 24, the correlation results rsFO, rsFi, ... finally evaluated and the data symbols dθ, dl, ... detected. Furthermore, the evaluation unit 24 preferably calculates a quality parameter (link quality indication, LQI), which indicates the quality of the communication connection. The evaluation unit 24 will be explained in more detail in connection with FIG.

FIG. 3 shows two block diagrams of different embodiments of the differential demodulator (DEMOD) 22 from FIG. 2. The more complex implementation of FIG. 3 a is advantageous in cases where a frequency offset is to be corrected, while the simpler implementation according to FIG. 3 b is advantageous if one Compensation of the frequency offset not required and / or not desired. In both cases, the input signal is the complex baseband signal b provided by the inner receiver 21 from FIG. 2 with samples in chip clock rate fc = 2ivichip / s.

The differential demodulator 31 shown in FIG. 3a comprises a delay unit 32 connected to the inner receiver 21, a first complex multiplier 33 connected to the inner receiver 21 and the delay unit 32, a second complex connected to the first complex multiplier 33 and the inner receiver 21 Multiplier unit 34 and an imaginary dividing unit 35 connected to the second complex multiplying unit 34.

The delay unit 32 is configured to provide the samples of two real input signals, which can be interpreted as real part (I) and imaginary part (Q) of a complex input signal, each delayed by one chip period τc = i / fC = 500ns. The complex multiplier units 33, 34 perform complex multiplications, the first multiplier unit 33 multiplying the complex samples applied to the first input by the complex conjugate values of the complex samples applied to the second input, while the second multiplier unit 34 "superimposing" the adjacent complex samples on each other The imaginary dividing unit 35 finally suppresses the real part of the complex input and provides the imaginary part of the input at the output.

For the following description of the operation of the differential demodulator 31, the samples of the complex baseband signal b are denoted by x (k) + j * y (k) (see FIG. 3a), where x (k) is the real part (in-phase component I ) and y (k) represent the imaginary part (quadrature component Q) of the samples and k indicates a time index (index of the chip period).

The first complex multiplier 33 multiplies the current samples x (k) + j * y (k) by the conjugate complex values x (kDj * y (ki) of samples x (kD + j * y (ki) delayed by one chip period TC : cKk) = (x (k) + j * y (k)) * (x (kD -j * y (kU). da)

The first complex products cKk) thus obtained are then multiplied in the second complex multiplier unit 34 by the complex factor fOFF provided by the inner receiver 21 in order to compensate for the frequency offset and to calculate second complex products c2 ⁽ k): C2 (k) = CKk) ^* fOFF. (2a) In the imaginary dividing unit 35, finally, the imaginary part of these second complex products c2 (k) is formed and the demodulated signal s (k) is provided: s (k) = lmag {c2 (k)}. (3a)

The implementation of the differential demodulator shown in Figure 3a can be simplified by replacing the functional blocks 34, 35 with a unit calculating only the imaginary part of the product of CKk) and fOFF: s (k) = Real {cKk)} * lmag {fθFF} + imag {d (k)} * Real {f OFF}. (2a'-3a ')

According to equation (2a'-3a '), this unit contains only two multipliers with two inputs each for the real-valued multiplication of Real {d (k)} with lmag {fOFF} or imag {cKk)} with Real {fOFF} and a downstream one Adder for adding the real-valued multiplication results. A further simplification of the differential demodulator results if the correction of the frequency offset is to be dispensed with. The advantageous in this case, very simple implementation form is shown in Figure 3b.

The differential demodulator 36 shown in FIG. 3b comprises a delay unit 32 connected to the inner receiver 21, two multipliers 37, 38 respectively connected to the inner receiver 21 and the delay unit 32 and a first adder 39 connected to the multipliers.

While the delay unit 32 of FIGS. 3a and 3b are configured identically, the multipliers 37, 38, in contrast to the complex multiplier units 33, 34 of FIG. 3a, are purely real multipliers for the multiplication of real-valued samples.

With the above designation of the samples of the complex baseband signal b, the operation of the differential demodulator 36 can be described as follows (see FIG. 3b). The first multiplier 37 multiplies the imaginary parts y (k) of the current samples x (lθ + j * y (k) of the complex baseband signal b by the real parts x (kD of the chip x delayed samples x (kD + j * γ (kD and calculates first (real-valued) products rKk) = γ (k) * x (kD. db ⁾ Analogously, the second multiplier 38 multiplies the real parts x (k) of the current samples x (k) + j * y (k) of the complex baseband signal b by the imaginary parts γ (kD of the samples x (kD + j * y delayed by one chip period) (k-D and thus calculates second (real-valued) products r2 (k) = x (k) * y (kD. (2b)

Finally, the first adder 39 forms the following difference of the first and second products and provides the demodulated signal s (k): s (k) = rκk) -r2 (k). (3b)

As can be seen from FIGS. 3 a and 3 b, hard decisions are not made in any of the two implementation forms 31, 36 of the differential demodulator 22. Such hard decisions would result in the samples of the demodulated signal s being only two values, e.g. the demodulated signal s would consist of so-called hard bits, in contrast to this the demodulated signal s consists of higher-level (more than two-stage) sampled values in each of the implementation forms according to FIG. 3a or 3b also referred to as "soft information values", in comparison to a hard decided demodulated signal of hard bits, the following blocks (equalizer 26, correlation unit 23, evaluation unit 24, see Figure 2) with the soft information values demodulated signal s according to Figure 3a 3b has made more information available and improved the performance of the entire receiving unit 16, ie, for example, the bit, symbol, frame error rate, etc. under disturbing influences such as channel distortions and noise. Applicant's simulations have shown that the performance of the receiver for AWCN is Channels (additive white caussian noise) approx. 2dB ver improves when the demodulated signal has 4-bit wide soft information values instead of hard bits.

In the following it is described how the derived sequences FO, F1,... Are provided by the sequence preparing unit 25 according to FIG. The following table shows both the PN sequences P0, P1,..., P15 to be used according to IEEE 802.15.4 and the derived sequences FO, F1,..., F15 assigned to the PN sequences according to the invention. As far as the PN sequences PO, P1, P2, ... to be used on the transmitting side are concerned, it should first be stated that a sequence supply is specified with a total of 16 PN sequences PO, P1,..., P15. Each PN sequence here comprises 32 so-called chips, each of which can assume a value of logical zero (0) or one (1). As can be seen from the table, for example, the first ten chips of the PN sequence P5 assume the values 001 1 0 1 0 1 00.

For the chips e.g. In the PN sequence P5, for convenience of description, the parameters P5cθ (first chip (cθ) of P5), P5d (second chip (CD), ..., P5C3O, P5C31 (last chip (c3D) are introduced other PN sequences such that Picj designates the chip with index j (ie, the (j + Dth chip) of the PN sequence with index i (Pi), where Ϊ = 0, 1, ..., 15 and j = 0.1, ..., 31. Furthermore, to better distinguish the chips of the PN sequences from those of the derived sequences, the former are referred to as Pi \ l chips.

Pi: PN sequence i (transmitting side) (PicO Pid Pic2 Pic3 Pic30 Pic31)

Fi: Pi-derived sequence (FicO Fiel Fic2 Fic3 Fic30 Fic31)

PO 1 1 0 1 1 0 O 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 FO + + + + + + + + + + + + + + + + + +

Pl 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 O 0 1 0

P2 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 O 0 1 0

P3 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 O 0 1

F3 + + + - - + + - + + - - + + + - - - - - - + + + - + + + + - + -

P4 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 O 0 1

F4 + - + - + + + - - + + - + + - - + + + + + + - + + +

P5 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 ^τi 0-

F5 - + + + + - + - + + + - - + + - + + - - + + + + + +

P6 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1

F6 - + + + - + + + + - + - + + + - - + + - + + - - + + + - - - - -

P7 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 F7

P8 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1

F8 - - - + + + + + + - - - + - - - - + - + - - - + + - - + - - + +

P9 1 0 1 1 1 0 O 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 O 0 1 1 1 O 1 1 1

F9 - - + + - - - + + + + + + - - - + - - - - + + - - - + + - - +

Pl C): 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 O 0 1 1 1

Fl C): + - - + - - + + - - - + + + + + + - - - + - - - - + - + - - - +

PI l. : 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0

Fl] - - + + - - + - - + + - - - + + + + + + - - - + - - - - + - +

Pi:: 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0

F12 + - + - - - + + - - + - - + + - - - + + + + + + +

P13: 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 O 1

F12: + - - - - + - + - - - + + - - + - - + + - - - + + + + + + - - -

P14: 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 O 0 O 1 1 O 0

F14: + - - - + - - - - + - + - - - + + - - + - - + + - - - + + + + +

PlS: 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 O 1 1 1 0 0 0

F15: + + + + + - - - + - - - - + - + - - - + + - - + - - + + - - - + If one divides the 16 PIM sequences into a first group of the eight Pisi sequences PO, P1,..., P7 and a second group of the eight PN sequences P8, P9,..., P15, then the table continues It can be seen that the PN sequences of the first group differ from one another only by a cyclical shift of their chip values. For example, the bit pattern {1 1 0 1 1 0} occurring at the beginning of the PN sequence PO is in the PN sequence P1 from the PN chip P1C4, in the PN sequence P2 from P2c8, in P3 from P3C12, in P4 as of P4d6, ..., and finally in P7 from P7c28 - with cyclic extension. The PN sequences of the second group differ only by a cyclic shift of their chip values from each other.

Furthermore, it should be noted that for each PN sequence of the first group there exists a PN sequence of the second group which differs from this PN sequence of the first group only in every other chip value, namely by an inversion of every other chip value eg the PN sequences PO and P8 in the table, it is found that the even-index PN chips have identical values (P0C0 = P8C0 = 1, P0c2 = P8c2 = 0, P0C4 = P8C4 = 1, etc.). while the odd-index PN chips have different values (POC1 = 1, P8C1 = 0, POC3 = 1, P8C3 = 0, POC5 = 0, P8c5 = 1, etc.).

According to the invention, each PN sequence is assigned a non-identical derivative sequence adapted to the differential demodulation, the PN sequence PO, for example, the derived sequence FO listed in the table below PO, the PN sequence P1, the derived sequence Fi, etc The chips of the derived sequences, here referred to as derived chips, can assume the anti-podal values +1 and -1, whereby in the table only the sign of these values is entered for reasons of clarity. Analogous to the designation of the PN chips introduced above, the derived chip with index j of the derived sequence is referred to below as index i, where i = 0, i,... I5 and j = 0, i,. 3i.

The values of the derived chips are as follows from the values of the PN chips. For example, to form the value of the derived chip F0C2, which according to the

Table is +1, the value of the one entered directly above it in the table is

PN chips Pθc2 = θ logically XOR to the value of the left (i.e., the preceding) P0c2 input PN chip POd = 1. The logical one

In this case, an XOR combination yields a value of logical 1 to which the antipodal value + 1 entered in the table for F0c2 is assigned. Corresponding the value of Fθc4 results from P0C4 XOR Pθc3 = 1 XOR 1 = O for the value of -1 entered in the table for Foc4, since the logical zero is assigned an antipodal value of -1. This derivation rule applies to all derived positive even index chips. Thus, if Ficj denotes the derived chip with index j of the derived sequence with index i and Picj and Picn denotes the PN chip with index j or n of the PN sequence with index i, the derivative chip Ficj results for positive even indices j i = 0, i, ..., i5 too

Ficj = 2 * (Picj XOR picn) - 1 with n = ji for j = 2,4,6, ..., 30, (4) where the multiplication of the result of the XOR operation with the factor 2 and the subsequent subtraction 1 is intended to reflect the assignment of the logical values of 0 and 1 to the antipodal values -1 and +1, respectively.

For the formation of the derivative chips Ficj with index j = 0, the last PN chip Picn with n = 31 is to be used instead of the (nonexistent) PN PNn chip Picn with index n = j-i = -1. Ficj = 2 * (Picj XOR Picn) - 1 with j = 0 and n = 3i for i = o, i, ..., i5. (5)

A derivation rule similar to equation (4) applies to the derivative chips ficj with odd index j. in this case, the result of the XOR linkage is to be inverted before being assigned to antipodal values:

Ficj = 2 * iiW {Picj XOR Picn} - 1 where n = ji for j = i _i 3 ₍ 5 _f ..., 3i, (6) where INVQ denotes the logical inversion and again i = 0, i, .. ., i5 applies.

Instead of the inversion of the logical values with subsequent assignment of logical 0 to the antipodal value -1 and of logical 1 to the antipodal value + 1, another assignment can of course also be made, namely from logical 0 to antipodal value +1 and from logical 1 to antipodal value. 1, thus omitting logical inversion. The formula is then

Ficj = 1 - 2 * (Picj XOR Picn) with n = ji for J = 1,3,5, ..., 31. ( ^6C )

The use of the respective "current" PN chip (with the index of the derived chip to be formed) and of the respective preceding PN chip corresponds to the transmission-side division of the PN chips with even (odd) index on the in-phase index explained in the introduction to the description. (I) carrier (quadrature phase (Q) carrier) in the context of offset QPSK modulation (quaternary phase shift keying) Other transmission-side I / Q divisions of the PN chips require a correspondingly adapted formation of the derived ones Crisps. dividing the 16 derived sequences into a first group of the eight derived sequences FO, F1, ..., F7 and a second group of the eight derived sequences F8, F9, ..., F15, it can be seen from the table that the derived sequences of the first group differ from each other only by a cyclic shift of their chip values. For example, the bit pattern {+ + +} occurring at the beginning of the derived sequence FO is in the derived sequence F1 from the derived chip Fic4, in the derived sequence F2 from F2c8, in F3 from F3d2, in F4 from F4d6, ..., and finally in F7 from F7c28 - with cyclic expansion. The derived sequences of the second group differ only by a cyclic shift of their chip values from each other.

Furthermore, it should be noted that for each derived sequence of the first group there exists a derived sequence of the second group which differs only by an inversion of all its chip values. the deduced sequences FO and F8 in the table, one finds that all chip values are inverted. Since this also applies to the sequence pairs F1 / F9, F2 / F10, etc., it should be noted that all derived sequences of the first group are contained in inverted form in the second group:

Ficj = (-D * Fncj with i = o, i, ..., 7, n = i + 8 and j = o, i, ..., δi (7) in contrast to the PN sequences where the corresponding pairs of sequences (P0 / P8, P1 / P9, etc.) differ by an inversion of every other PN chip, the corresponding pairs of derived sequences differ by an inversion of all their chip values.

The properties of the derived sequences mentioned in the preceding paragraphs allow very simple implementations of the sequence providing unit 25, the correlation unit 23 and the evaluation unit 24 and thus of the entire receiving unit 16 from FIG. 2.

It is obvious that instead of the deduced sequences listed in the table, the respective inverted sequences can also be used. This corresponds only to an exchanged assignment between the PN sequences and the derived sequences. In this case, the PN sequence PO is assigned the derived sequence F8 from the table, the PN sequence P1 the derived sequence F9 from the table, etc. This changed to order is to be considered in the correlation and / or the evaluation accordingly.

In the correlation unit 23, the first chip of the derived sequences (FicO) can advantageously be disregarded in the calculation of the correlation results so that the data symbols can be decided independently of the preceding data symbol in the evaluation unit 24. Without appreciable losses in the performance of the detection, the receiving unit can be realized so easily.

FIG. 4 shows a block diagram of the evaluation unit (EVAU 24 of FIG. 2) having an index determination unit 41 connected to the correlation unit 23, an allocation unit 42 connected to the correlation unit 23, and preferably an LQI unit 43-46 connected to the correlation unit 23 (link qualityin The LQI unit has the following series-connected function blocks: a maximum-conversion unit 43 connected to the correlation unit 23, an adder unit 44, a third multiplier 45 and a value-restriction unit 46.

The correlation results rsFO, rsFi, ..., rsFis calculated by the correlation unit 23 are evaluated in the index determination unit 41 by the index of the correlation result having the maximum value among all the correlation results rsFO, rsFi,..., ΓSF15, per symbol period TS determined and according to Figure 4 is output as the value of the index 'm. For example, if the correlation result rsF5 has the maximum value among all the correlation results, the index determination unit 41 outputs the value m = 5. This means that the signal s or se with the derived sequence F5 has the highest degree of agreement among all derived sequences FO, F1,..., F15.

The allocation unit 42 assigns to each index m the symbol value to which the PN sequence assigned to the derived sequence with this index m is assigned. Assuming that the symbol value d = 5 is assigned to the PN sequence P5 at the transmitting end and this in turn is assigned the derived sequence F5 in accordance with the table above, the allocation unit 42 in the above example assigns the data symbol d = 5 to the index m = 5 to. The maximum forming unit 43 of the LQI unit determines per symbol period TS the maximum correlation value rsFmax of all correlation results rsFO, rsFi,..., ΓSF15. The adder unit 44 optionally has an integration unit 47, but in any case a second adder 48, wherein the integration unit 47 adds or averages a plurality of maximum correlation values rsFmax, preferably determined in successive symbol periods, and the second adder 48 adds a constant -Kc Value + K subtracts to calculate the sum r4. The third multiplier 45 then multiplies the sum r4 by the factor fSKAL before the value restriction unit 46 restricts the third products r3 thus obtained to a predetermined value range (eg 0 ... 255) to obtain an LQI value as a measure of the quality of the communication connection provide. The constant -K and the factor fSKAL are chosen in this case so that the signal quality (LQ1) provided according to the above steps completely covers the given value range (eg O... 255) depending on the quality of the received radio signal r.

The receiving unit according to the invention described above with reference to FIGS. 2 to 4, and thus also transmission receiving apparatuses having such a receiving unit, are characterized by very simple realizability, extremely low energy consumption and high performance (bit error rate or the like as a function of disturbing influences such as Noise and / or channel distortion). Investigations of the applicant require the digital parts of receiving units according to the invention - without synchronization unit - a hardware cost in the order of a few thousand gate equivalents (NAND gate with two inputs), in data transmission mode these digital parts of the receiving units according to the invention have a power requirement of the order of a few Milliwatts (mW).

FIG. 5 shows a flow chart of the method according to the invention for incoherent detection. In step S1, first the received radio signal r is converted into a complex baseband signal b with samples in chip clock fC, in step S2 the complex baseband signal b is differentially demodulated, in the optional step S3 the demodulated signal s is equalized and thus an equalized demodulated signal se is formed , in step S4, which can alternatively also be carried out before step S3 - in extreme cases even before step S1 the derived sequences FO, F1, F2,... described in more detail above are provided, in step S5 the demodulated signal s or the equalized demodulated signal se is correlated with the derived sequences FO ₁ F1, F2,... to obtain the correlation results rsFO, rsFi, rsF2, ... to calculate. Finally, the correlation results in step S6 are evaluated and the values of the data symbols dθ, dl, d2,... Are derived. A more detailed description of the steps S1-S6 can be found in the above description of the operation of the receiving unit 16 or its functional blocks 21-26 with reference to FIGS. 1 and 2.

FIG. 6 shows two flow diagrams of different implementation forms of the differential demodulation step S2 from FIG. 5. The first implementation form according to FIG. 6a is advantageous in cases where a frequency offset is to be corrected, while the second implementation according to FIG. 6b is advantageous if compensation of the frequency offset should not take place.

According to FIG. 6a, a complex factor fOFF suitable for correcting a frequency offset is determined in step S2ai. This step takes place within the scope of step S1 of FIG. 5 (provision of b), but can also take place in the context of step S2 (however, step S2a4), in step S2a2 the sample values x (k) + jy (k In step S2a3, first complex products cKk) are calculated by dividing the conjugate complex values of the samples x (ki) -jy (kD delayed according to step S2a2 with the instantaneous samples x (k) of the complex chip clock baseband signal b Finally, in step S2a4, the demodulated signal s is formed by dividing (only the) imaginary parts of second complex products c2 (k) from the first complex products cKk) [S2a3l and the complex one Factor fOFF [S2ail be calculated. A more detailed description of the steps S2ai-S2a4 is the above description of the operation of the differential demodulator 22, 31 and its function blocks 32-35 with reference to Figures 2 and 3a and the equations da) to (2a'-3a '). refer to.

According to FIG. 6b, the samples x (k) + jy (k) of the complex chip clock baseband signal b are delayed in step S2a2 in FIG. 6a by one chip period TC, in step S2b2 first products rKk) are calculated by the real components the delayed samples x (kD with the imaginary parts of the In step S2b3, second products r2 (k) are calculated by multiplying the imaginary parts of the delayed samples y (ki) by the real parts of the undelayed samples x (k) of the complex baseband signal b are multiplied. Finally, in step S2b4, the demodulated signal s is formed by subtracting the second products r2 (k) from the first products rKk). A more detailed description of the steps S2bi-S2b4 can be found in the above description of the operation of the differential demodulator 22, 36 or its function blocks 32, 37-39 with reference to FIGS. 2 and 3b and the diagrams db) to (3b) , Both the demodulated signal s generated in accordance with FIG. 6a and that shown in FIG. 6b advantageously have soft information values (see description of FIG.

FIG. 7a shows a flowchart of the evaluation step S6 from FIG. 5. In step S6ai, the index m of the correlation result which has the maximum value is determined, for example m = 5, if rsF5 of all the correlation results rsFO, rsFi, rsF2, In step S6a2, this index m is assigned the data symbol whose symbol value is assigned to that PN-sequence which can be assigned on the transmitting side and to which the derived sequence with this index m is assigned. If, for example, the symbol value d = 5 in the above example is assigned to the PIM sequence P5 and to this in turn the derived sequence F5, then the index m = 5 is assigned the data symbol with the symbol value d = 5. FIG. 7b shows a further flow chart of the evaluation step S6 from FIG. 5, in which the signal quality is determined. In step S6bi, first the maximum value rsFmax of all correlation results rsFO, rsFi, rsF2,... Is determined for each symbol period TS. After optionally (not shown in FIG. 7b) several values rsFmax belonging to successive symbol periods have been added (accumulated, integrated), in step S6b2 the sum r4 is multiplied by adding a constant -K which is multiplied by the factor fSKAL in step S6b3 to calculate a third product r3. The signal quality parameter LQi (link quality indication) is finally determined in step S6b4, in which the values of the third product r3 are limited to a predetermined value range, such as 0 ... 255. The constant -K and the factor Gate fSKAL are chosen so that the signal quality LQl completely covers the given value range depending on the quality of the received radio signal r.

A more detailed description of the steps from FIGS. 7a and 7b can be found in the above description of the mode of operation of the evaluation unit 24 or its function blocks 41-48 with reference to FIGS. 2 and 4.

Although the present invention has been described above with reference to exemplary embodiments, it is not restricted thereto but can be modified in many ways, the invention is not based on WPANs per se nor on WPANs according to IEEE 802.15.4 or the PN specifications specified there. Sequences (number and length of sequences, stage and value of the chips, etc.), rates and stages of the chips / symbols / bits, etc. limited. Also, the invention is not limited to the derived sequences given in the table above. For the relationship between the derived chips and the PN chips, various equivalent logical relationships can be given.

LIST OF REFERENCE NUMBERS

10 Data transmission system / "Wireless Personal Area Network"

(WPAN) according to the IEEE 802.15.4 standard 11-13 Transceiver, "transceiver"

14 antenna

15 transmitting unit, "transmitter"

16 receiving unit, "receiver"

17 control unit 21 internal receiver

22 differential demodulator

23 correlation unit, despreader

24 evaluation unit, detector

25 sequence providing unit 26 equalizer

31 differential demodulator (with correction of a frequency offset)

32 delay unit

33, 34 first and second complex multiplier unit, respectively

35 imaginary dividing unit 36 differential demodulator (without correction of a frequency offset)

37, 38 first and second multipliers, respectively

39 first adder / subtractor

41 index determination unit 42 allocation unit, detection unit

43 maximum formation unit

44 adding unit

45 third multiplier

46 Value restriction unit 47 Integration unit

48 second adder / subtractor

COR correlation unit, despreader

CTRL control unit DEMOD differential demodulator

EQ equalizer EVAL evaluation unit, detector

FM frequency modulation

IC integrated circuit; Chip iREC inner receiver

IMAG Imaginary Education Unit

IND index determination unit

ISM industrial, scientific, medical (frequency band at 2.4 CHz)

LQl signal quality parameter (link qualitv indication)

MAP allocation unit

MAX maximum formation unit

MSK minimum shift keying

PN pseudo-noise

QPSK quaternary phase shift keying

RX receiver, receiver

SEQ Sequence Provisioning Unit

TRX transmitting receiver, transceiver

TX transmitting unit, transmitter

WPAN Wireless Personal Area Network

b complex baseband signal with samples in chip clock

CKk), c2 (k) first and second complex products dθ, d- 1, (12, ... data symbols fB bit clock (= 1 / TB) fc chip clock (= 1 / TC) fs symbol clock (= i / fS) fOFF complex factor fSKAL scaling factor

FO ₁ FI, F2, ... derived sequences, FVFSK sequences, second codes

(Receiver-side)

F5C0, F5C1, ... chips of the derived sequence ("derived chips") F5, i, J ₁ m,, n indices

K constant

PO ₁ PI P2 PN sequences, spreading sequences, first codes (transmitting side)

P5C0, P5C1, ... PN sequence chips ("PN chips") P5 r Radio signal, received signal rKk), r2 (k) first or second products r3 third product r4 sum rsFO, rsFi, ... correlation results rsFmax maximum correlation result s demodulated signal; soft information values, equalized demodulated signal; equalized soft information values

TB bit period (= i / f B) TC chip period (= i / fθ

TS symbol period (= i / fs) x (k) + jy (k) samples of the complex sampled in chip clock fc

Baseband signal b

Claims

claims

1. A method for the incoherent detection of data symbols (dθ, d1, d2,...) Contained in a received radio signal (r), wherein each transmitting side

Data symbol (dθ = 5) is assigned a symbol-value-specific PN sequence (P5) from in chip clock (fθ successive PN chips (P5cθ, P5d, P5c2, ...) and the data symbols (dθ, dl, d2, ...) ) PIM sequences (P5, P4, P7,...) are offset-QPSK-modulated, with the steps a) transfer (SD of the received radio signal (r) into a complex baseband signal sampled in chip clock (fα) (b b) generating (S2) a demodulated signal (s) by differentially demodulating the complex baseband signal (b) sampled in the chip clock (fθ), c) providing (S4) derived sequences (FO, F1, F2, ...), each derived sequence (F5) being associated with a transmit-assignable PN sequence (P5) and consisting of derived chips (F5cθ, F5d, F5c2, ...) each having a logical combination of respective PIM chips (P5cθ , P5C1, P5c2, ...) correspond to the transmit-side assignable PN sequence (P5) which has the derived sequence (F5) assigned net, d) calculating (S5) correlation results (rsFO, rsFi, rsF2, ...) by correlating the demodulated signal (s) with the derived sequences (FO, F1, F2, ...), and e) deriving (S6) the values of the data symbols (dθ, dl, d2, ...) by evaluating the correlation results (rsFO, rsFi, rsF2, ...).

2. The method according to claim 1, characterized in that the demodulated signal (s) has soft information values.

3. Method according to claim 2, characterized in that a complex factor (fOFF) suitable for correcting a frequency offset is provided (S2aD and the generation of the demodulated signal (s) comprises the following steps: a) delaying (S2a2) the sampled values (x (x) k) -t-jy (k)) of the complex baseband signal (b) by one chip period (TO, b) calculating (S2a3) first complex products (d (k)) by multiplying the conjugate complex values of the delayed samples (x (ki) -jy (k-D) by the non-delayed samples (x (k) + jy (k )) of the complex baseband signal (b), O generating (S2a4) the demodulated signal (s) by calculating the imaginary parts of second complex products (c2 (k)) from the first complex products (CKk)) and the complex factor (fOFF) ,

A method according to claim 2, characterized in that the generation of the demodulated signal (s) comprises the steps of: a) delaying (S2bD the samples (x (k) + jγ (k)) of the complex baseband signal (b) by one chip period (TC), b) calculating (S2b2) first products (rKk) by multiplying the real parts of the delayed samples (x (kD) with the imaginary parts of the undelayed samples (y (k)) of the complex baseband signal, c) calculating (S2b3) of second products (r2 (k)) by multiplying the imaginary parts of the delayed samples (y (kU) by the real parts of the undelayed samples (x (k)) of the complex baseband signal, d) generating (S2b4) the demodulated signal ( s) by subtracting the second products (r2 (k)) from the first products (rKk)).

5. Method according to one of the preceding claims, characterized in that, when calculating the correlation results (rsFO, rsFi, rsF2,...), The demodulated signal (s) is correlated with a number of derived chips which is one less than one the number of PN chips contained in each PN-sequence that can be assigned on the fly.

6. A method according to any one of the preceding claims, characterized in that the demodulated signal (s) is equalized (S3), wherein the Entzer- tion preferably has a suppression of a DC component, and the

Correlation results (rsFO, rsFi, rsF2, ...) are calculated by correlating the equalized demodulated signal (se) with the derived sequences (FO, Fi ₁ F2, ...).

7. Method according to one of the preceding claims, characterized in that the derived chips have a first positive index (F5ci, i = i, 2, ...) each have a value which consists of an XOR combination of the PN chip with this first positive index (P5ci, i = i, 2,...) with the index-wise preceding PN Chip (P5cj, j = iD is derivable.

8. The method according to any one of the preceding claims, characterized in that the index-wise first derivative chip (F5cθ) has a value derivable from an XOR operation of the index-wise first PN chip (P5cθ) with the index-last PN chip (P5c3D is.

9. The method according to claim 7 or 8, characterized in that a) the derived chips with an even-numbered index (F5cθ, F5c2, ...) each have a value which is associated with the value of the respective XOR-linkage and b) the derived chips with an odd-numbered index (F5d, F5c3,...) each have a value which is assigned to the inverted value of the respective XOR link.

10. The method according to any one of the preceding claims, characterized in that the evaluation of the correlation results (rsFO, rsFi, rsF2, ...) comprises the following steps: a) determining (S6aD of the index ¹ (m = 5) of that correlation result (rsF5) b) assigning (S6a2) of the data symbol to this index (m = 5) whose symbol value (d = 5) is assigned to the transmit-assignable PN sequence (P5) containing the derived sequence ( F5) is associated with this index (m = 5).

11. The method according to any one of the preceding claims, characterized in that the evaluation of the correlation results (rsFO, rsFi, rsF2, ...) comprises the following steps: a) determining (S6bD of the maximum correlation value (rsFmax) of the correlation results, b) calculating ( S6b2) of a sum (r4) by adding a constant (-K) ₁ c) calculating (S6b3) a third product (r3) by multiplying the sum (r4) by a factor (f SCAL), d) providing (S6b4) the signal quality (LQi) by limiting the values of the third product (r3) to a predetermined value range (0 ... 255), the constant (-K) and the factor (fSKAL) being chosen the signal quality (LQ1) provided according to steps a ⁾ to d) completely covers the predetermined value range depending on the quality of the received radio signal (r).

12. incoherent receiving unit (16) for detecting in a received radio signal (r) contained data symbols (do, dl, d2, ...), characterized in that the receiving unit (16) is formed, a Ver¬ To carry out according to one of the preceding claims.

13. Incoherent receiving unit (16) for detecting in a received radio signal (r) contained data symbols (dθ, dl, d2, ...), where each data symbol (dθ = 5) on the transmitting side a symbol value-specific PM sequence (P5) from in Chip clock (fθ consecutive PN chips (P5cθ, P5d, P5c2, ...) is assigned and the PN symbols (P5, P4, P7, ...) assigned to the data symbols (dθ, dl, d2, ...) Offset QPSK modulated, comprising: a) an inner receiver (21) for converting the received radio signal (r) into a complex baseband signal sampled in the chip clock (fC)

(b) is formed, b) a differential demodulator (22; 31; 36) connected to the inner receiver (21), for generating a demodulated signal (s) by differentially demodulating the complex baseband signal sampled in the chip clock (21) ( b) is formed, c) a sequence providing unit (25) adapted to provide derived sequences (FO, F1, F2, ...), each derived sequence (F5) being associated with a transmit-assignable PN sequence (P5) is and consists of derived chips (F5c0, F5d, F5C2, ...) whose values each correspond to a logical combination of respective PN chips (P5cθ, P5d, P5c2, ...) of the transmit side assignable PN sequence (P5) d) a correlation unit (23) connected to the sequence providing unit (25) and the differential demodulator (22) and used for calculating correlation results (rsFO, rsFi, rsF2, ... ) by correlating the demodulated e) formed with the derived sequences (FO, F1, F2, ...), and e) an evaluation unit (24) connected to the correlation unit (23), which for deriving the values of the data symbols (dθ, dl , d2, ...) by evaluating the correlation results (rsFO, rsFi, rsF2, ...) is formed.

14. incoherent receiving unit according to claim 13, characterized in that the differential demodulator (22) is designed such that the demodulated signal (s) has soft information values.

An incoherent receiving unit according to claim 14, characterized in that the incoherent receiving unit is adapted to provide a complex factor (fOFF) suitable for correcting a frequency offset and the differential demodulator (22; 31) comprises the following units: a) one with the inner receiver (21) connected delay unit (32) for delaying the samples (x (k) + jy (k)) of the complex baseband signal (b) by one chip period (TC), b) one with the inner receiver (21) and the delay unit ( 32) for calculating first complex products (CKk) by multiplying the conjugate complex values of the delayed samples (x (ki) -jy (kD) by the non-delayed samples (x (k) + jy ( k)) of the complex baseband signal (b), c) a unit (34, 35) connected to the first complex multiplier unit (33) and the inner receiver (21) for generating the demodulated signal (s) by calculating the imaginary parts of second complex products (C2 (k)) from the first complex products (CKk)) and the complex factor (fOFF).

16. incoherent receiving unit according to claim 14, characterized in that the differential demodulator (22; 36) comprises the following units: a) a delay unit (32) connected to the inner receiver (21) for delaying the samples (x (k) + jy (k)) of the complex baseband signal (b) around a chip period (TC), b) a first multiplier (37) connected to the inner receiver (21) and the delay unit (32) for calculating first products

(rKk)) by multiplying the real parts of the delayed samples (x (kD) with the imaginary parts of the instantaneous samples (y (k)) of the complex baseband signal, c) a second multiplier (38) connected to the inner receiver (21) and the delay unit (32) for calculating second products (r2 (k) by multiplying the imaginary parts of the delayed samples (γ (kD) by the real parts of the undelayed samples (x (k)) of the complex baseband signal, d) a first adder (39) connected to the first and second multipliers (37, 38) for generating the demodulated signal (s) by subducting the second products (r2 (k)) from the first products (rKk)).

17. incoherent receiving unit according to any one of claims 13-16, characterized in that the correlation unit (23) is formed when calculating the correlation results (rsFO, rsFi, rsF2, ...), the demodulated signal (s) each with a number of derived chips one less than the number of PN chips contained in each transmit side assignable PN sequence.

An incoherent receiving unit according to any of claims 13-17, wherein between the differential demodulator (22) and the correlation unit

(23) an equalizer (26), which is preferably designed to suppress a DC component, is arranged to equalize the demodulated signal (s), and the correlation unit (23) to calculate correlation results (rsFO, rsFi, rsF2, ...) Correlating the equalized demodulated signal

(se) with the derived sequences (FO, F1, F2, ...) is formed.

An incoherent receiving unit according to any of claims 13-18, wherein the sequence providing unit (25) comprises storage means for storing the derived sequences (FO, F1, ...).

20. incoherent receiving unit according to any one of claims 13-19, characterized in that the evaluation unit (24) comprises the following units: a) an indexing unit (41) connected to the correlation unit (23) for determining the index '(m = 5) of that correlation result

(rsF5) that has the maximum value b) an allocation unit (42), which is associated with the index determination unit (41), for assigning the data symbol to this index (m = 5) whose svmbol value (d = 5) is assigned to the transmit sequence assignable PN sequence (P5) that contains the derived sequence (F5) is assigned to this index (m = 5).

21 incoherent receiving unit according to any one of claims 13-20, characterized in that the evaluation unit (24) comprises the following units: a) a with the correlation unit (23) connected to the maximum forming unit (43) for determining the maximum correlation value (rsFmax) of the correlation results, b) an adding unit (44) connected to the maximum forming unit (43) for calculating a sum (r4) by adding a constant (-K),

O a third multiplier (45) connected to the adding unit (44) for calculating a third product (r3) by multiplying the sum (r4) by a factor (fSKAU, d) a value limiting unit (46) connected to the third multiplier (45) for providing the signal quality (LQI) by limiting the values of the third product (r3) to a predetermined range of values (0 ... 255), the constant (-K) and the factor (fSKAL) being chosen such that the values after the Step a) to d) provided signal quality (LQi) depending on the quality of the received radio signal (r) completely covers the predetermined range of values.

22 transmitting / receiving device (11-13), in particular for a Datenübertravgsvstem (10) according to IEEE standard 802.15.4 in the 2.4 GHz band, comprising a) an antenna (14), b) a with the transmitting unit (15) connected to the antenna (14) for transmitting data, in particular according to the IEEE standard 802.15.4 in the 2.4 GHz band, wherein the transmitting unit (15) is designed to give each data symbol (dθ = 5) a sym- Bloc-specific PN sequence (P5) from in chip clock (fC) successive PN chips (P5co, P5ci, P5c2, ...) assign and the data symbols (dθ, dl, d2, ...) assigned PiM sequences (P5 , P4, P7, ...) to modulate offset QPSK, c) an incoherent receiving unit (16) connected to the antenna (14) according to one of claims 12 to 21, d) a control unit (17) connected to the transmitting unit (15) and the receiving unit (16) for controlling the transmitting and receiving units (15, 16).

23 integrated circuit, in particular for a transmitting / receiving apparatus according to claim 22, with an incoherent receiving unit (16) according to any one of claims 12 to 21.