Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
  • H03K17/06—Modifications for ensuring a fully conducting state
  • H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
  • H03K17/06—Modifications for ensuring a fully conducting state
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters

Definitions

• the present invention relates to the control of transistors and more particularly of MOSFETs.
• a MOS transistor is included in an electrical conversion bridge, for example a voltage rectifier bridge.
• an electrical conversion bridge for example an inverter
• Such an electrical conversion bridge can be used reversibly.
• it is known to operate as an alternator an electric motor controlled by a reversible inverter comprising
• MOSFETs using the internal diode of the MOSFETs as a rectifying element. This amounts to using the inverter as a diode bridge.
• each MOS transistor is switched in the on state when a reverse current (negative current) flows between its drain and its source (Phase I), and in the off state the rest of the time (Phase II). .
• the present invention is intended to overcome these disadvantages.
• a first aspect of the invention provides a method of controlling a switching assembly comprising a plurality of parallel connected transistors having: a linear operating mode in which the internal resistance of the transistors is controllable within a given range of values; a mode of operation in a closed switch, in which the internal resistance is equal to a minimum value; and, a blocked operating mode, wherein the internal resistance is equal to a maximum value.
• the method comprises: a first phase of operation during which a current flows from a source terminal to a drain terminal of the transistors; a second phase of operation during which no current flows.
• the method comprises the steps according to which, successively: (a) controlling the transistors of the switch assembly in a closed switch mode during at least a portion of the first phase;
• the transistors are linearly controlled at the end of the first phase for at least a first predetermined period
• the mode-locked transistors are commonly controlled during at least a portion of the second phase.
• step (d) prior to step (a), during which each transistor is controlled in linear mode during at least a portion of the first phase;
• the first duration is greater than or equal to 5% of the first phase
• a drain / source voltage Uds increases during the second phase, and reaches a maximum rise slope, and each transistor of the switching assembly has a low parasitic capacitance discharge time so that a gate / source voltage Ugs is substantially less than a threshold value determined when the drain / source voltage Uds reaches said maximum rise slope; the process is implemented in an electrical conversion bridge;
• the electric conversion bridge is connected to a rotating electrical machine that can alternately operate alternator or motor;
• the method is implemented to control a switch.
• a second aspect of the invention proposes a device for controlling a transistor comprising means for implementing the method according to the first aspect.
• Such a device advantageously comprises a comparator and adjustment means comprising: a capacitance and a series resistance connected between an output of the comparator and an input of the comparator, a resistor connected between said comparator output and the gate terminal of the comparator; switching assembly, and a resistor connected between said comparator input and the drain terminal of the switching assembly.
• FIG. 1 is a diagram of a device according to the second aspect of the invention
• FIG. 2 is a timing diagram showing the evolution over time of the source / drain voltage and the current in a switching assembly comprising MOS transistors during the implementation of the method according to the first aspect of the invention
• FIG. 3 is a timing diagram showing in more detail the evolution as a function of time of the source / drain voltage and of the gate / source voltage of the switching assembly
• FIG. 4 represents a switching assembly in an exemplary implementation of the invention.
• a control circuit of a switching unit 1 comprising MOS parallel connected transistors may for example comprise an error amplifier 2, which may be implemented with an operational amplifier 2.
• the voltage at the terminals drain / source of the switching assembly (noted Uds in the following and in the figures) can be compared to a reference voltage 3 (noted Uref in the following and in the figures), for example negative.
• the error amplifier drives the switching assembly 1 for example by simultaneously applying a voltage to the gate of each transistor of the assembly.
• this control circuit comprises a feedback loop, preferably comprising a capacitor C1 and two resistors R1 and R2.
• the switching assembly In operation, when the drain / source voltage becomes negative, the switching assembly is controlled by applying a positive voltage on its gate. It is thus possible to vary the internal resistance of the transistors so that the drain / source voltage drop due to the passage of current I flowing through the transistors from the source to the drain does not exceed the reference voltage. It is thus possible to maintain constant the voltage across the switching assembly.
• the product of the intensity of the current flowing through each transistor and the minimum internal resistance of the transistors is greater than the reference voltage value.
• the voltage applied to the gate by the amplifier is so high that the transistors go into closed switch mode (ON state).
• the evolution of the voltages and currents at the switching assembly is described by the timing diagram of FIG. 2 in such a case.
• the first phase (noted I later and in the figures) corresponds to a drain / source voltage negative, and in which current flows through the switching assembly.
• the second phase corresponds to a positive drain / source voltage in which the switching assembly 1 is supposed to be totally blocked (no current flows).
• the voltage across the switching assembly 1 becomes negative, it enters the phase I.
• the duration noted 4 on the curve representing the evolution of the voltage at the drain / source terminals of the set of switching 1 corresponds to the time required for servoing to start driving the transistors. Then, the servocontrol tries to keep the voltage Uds constant by modifying the internal resistance of the transistors. Each transistor can therefore operate linearly for the duration noted (d).
• the current I represented in dashed lines, reaches a value so high that the internal resistance reaches its minimum value Rdson and the switching unit 1 switches to closed switch mode (ON state). This corresponds to the noted duration (a) of the curve. Since the internal resistance of each transistor 1 becomes substantially constant, the voltage at its terminals becomes proportional to the current flowing through this transistor.
• each transistor is controlled linearly for the duration noted (b). To do this, it must be ensured that the servocontrol, illustrated by the diagram of FIG. 1, is fast enough to be able to switch the switching assembly back into linear mode as soon as current I passes below a value. determined (Vref / Rdson).
• the switching assembly may comprise adjustment means.
• these adjustment means may comprise a capacitance and resistances, in particular formed by the capacitor C1 and the resistors R1, R2, R3.
• the capacitor C1 is connected between the output of the operational amplifier 2 and a connection of the resistor R1.
• the other connection of the resistor R1 is connected to the input (-) of the operational amplifier.
• the resistor R2 is connected between the drain of the switching unit 1 and the inverting input of the amplifier 2.
• the resistor R3 is connected between the output of the operational amplifier 2 and the gate of the switching assembly 1.
• the values of the resistance and the capacitance are such that the performance of the servocontrol is improved, in particular when the intensity of the instantaneous current is below a certain value.
• the speed of the slaving is such that it can control the transistors in fast linear mode until the end of phase I, before the transition to phase II.
• the duration (b) represents more than 5%, preferably more than 10% of the duration of the phase I. This percentage depends on the values of current flowing in the conversion bridge.
• the bridge operates periodically, and the phase I is substantially equal to half a period of operation. The electrical charges accumulated in the transistor 1 thus have time to be evacuated before the transition to phase II.
• phase II the voltage Uds becomes positive, then causing the passage in phase II.
• phase II the transistors of the switching assembly 1 are blocked and the current flowing through them is substantially zero. This is illustrated by part (c) of the curve of FIG. 2. Since the operation of an electrical conversion bridge is periodic, at the end of phase II, it goes back to phase I.
• the blocking of the transistors which takes place between the end of phase I and the beginning of phase II, is fast enough not to be hampered by the Miller effect.
• a parasitic capacitance of the transistors accumulates charges due to the rapid variation of the drain / source voltage across the transistors and causes an increase in the voltage between the gate and the source. This increase, represented by part 8 of the curve of the figure
• control unit of the switching assembly sufficiently discharges the parasitic capacitances of the transistors before the voltage Uds reaches its maximum rise slope.
• This discharge time is a function of the resistance R3 and the total charge stored by the transistors in their parasitic capacitances.
• the control unit In order for the control unit to control the switching unit as quickly as possible, it is possible, for example, to choose an operational amplifier having a slew rate, and high output current capacitors, i.e. the possibility of varying the output voltage of the error comparator very quickly. The latter then ceases to behave as a linear amplifier, to advantageously transform itself into a fast comparator.
• a switching assembly 1 comprising a plurality of transistors T1, T2 and T3, connected in parallel with each other, is used. It is thus possible to increase the power of the electric conversion bridge, which in fact admits larger currents.
• the implementation of a plurality of transistors connected in parallel is in principle reserved for devices operating in open / closed switch mode.
• the use of a plurality of transistors connected in parallel and operating in linear mode leads to an unequal distribution of the currents flowing respectively through each transistor. This results in difficulties in ensuring the linear servo-control of the transistors and the current distribution, requiring the designers to generally insert resistive elements at the source or emitter of each transistor to distribute the current. current consumption, or to provide a linear servo device for each transistor.
• the first solution would cause significant losses, incompatible with an alternator-starter control device, in which the operation starter imposes currents exceeding 700 amps and a large available torque to start engines.
• the starter function could not be provided with such a device.
• the second solution is also not feasible, since it would cause a sharp increase in the cost and size of the device.
• the equal distribution of the currents is not essential, because of the enslavement of the transistors connected in parallel, which adjusts the voltage Vgs of all the transistors to a single value , forcing the voltage Vds to a regulated value common to all the transistors.
• the number of transistors in a switching assembly does not affect the performance of the regulation, and in particular the dynamic behavior of the switching assembly.
• the transfer function, reflecting the frequency behavior of the switching assembly is, against all expectations, little affected by the paralleling of a plurality of identical type transistors even when the currents are poorly distributed.
• This method and this device can be implemented in any system requiring a rectifying system, such as a rectifier bridge, a simple switch, for example a battery switch or an inverter, for example a reversible inverter connected to a machine. rotating electric.
• a rectifying system such as a rectifier bridge, a simple switch, for example a battery switch or an inverter, for example a reversible inverter connected to a machine. rotating electric.

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• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Inverter Devices (AREA)
• Electronic Switches (AREA)
• Power Conversion In General (AREA)

Applications Claiming Priority (2)

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• 2005
  • 2005-03-31 FR FR0503157A patent/FR2884079B1/fr not_active Expired - Fee Related
• 2006
  • 2006-03-22 JP JP2008503549A patent/JP2008535350A/ja active Pending
  • 2006-03-22 US US11/909,112 patent/US7737650B2/en not_active Expired - Fee Related
  • 2006-03-22 EP EP06726119A patent/EP1864381A2/de not_active Ceased
  • 2006-03-22 MX MX2007012086A patent/MX2007012086A/es unknown
  • 2006-03-22 KR KR1020077022294A patent/KR20070116047A/ko not_active Application Discontinuation
  • 2006-03-22 BR BRPI0607847A patent/BRPI0607847A2/pt not_active IP Right Cessation
  • 2006-03-22 WO PCT/FR2006/000621 patent/WO2006103333A2/fr not_active Application Discontinuation
  • 2006-03-22 CN CNA2006800092577A patent/CN101147323A/zh active Pending

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