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EP1459362A2 - Procede de deposition de couches de semi-conducteurs iii-v sur un substrat non iii-v - Google Patents

Procede de deposition de couches de semi-conducteurs iii-v sur un substrat non iii-v

Info

Publication number
EP1459362A2
EP1459362A2 EP02790389A EP02790389A EP1459362A2 EP 1459362 A2 EP1459362 A2 EP 1459362A2 EP 02790389 A EP02790389 A EP 02790389A EP 02790389 A EP02790389 A EP 02790389A EP 1459362 A2 EP1459362 A2 EP 1459362A2
Authority
EP
European Patent Office
Prior art keywords
layer
iii
substrate
layers
particular according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02790389A
Other languages
German (de)
English (en)
Inventor
Holger JÜRGENSEN
Alois Krost
Armin Dadgar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aixtron SE
Original Assignee
Aixtron SE
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10219223A external-priority patent/DE10219223A1/de
Application filed by Aixtron SE filed Critical Aixtron SE
Publication of EP1459362A2 publication Critical patent/EP1459362A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
    • C30B23/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C30B29/406—Gallium nitride
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02463—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD

Definitions

  • the invention relates to a method for depositing III-V semiconductor layers, for example gallium arsenide, aluminum arsenide, gallium indium arsenide or gallium indium aluminum arsenide phosphide, on a light III-V substrate, for example silicon, by introducing gaseous starting materials into the process chamber of a reactor.
  • III-V semiconductor layers for example gallium arsenide, aluminum arsenide, gallium indium arsenide or gallium indium aluminum arsenide phosphide
  • III-V layers are deposited according to the invention in the MOCVD
  • silicon substrates have the advantage of being less expensive than III-V substrates and also suitable for integration into silicon component structures.
  • One possibility of improving the layer quality is the deposition of thick semiconductor layers. However, this is limited by the thermal mismatch of the layers. These thermal mismatches lead to lattice tension and strong tension
  • Another problem is the combination of Ill-V layer structures or electronic components made from such layer structures with silicon Components on a substrate.
  • the invention is based on the object of crystalline deposition of thick III-V semiconductor layers on a silicon substrate without the disadvantageous lattice stresses occurring.
  • the invention is also based on the abe to combine on a Sustrat III-V components with silicon components.
  • the object is achieved by the invention specified in the claims, claim 1 initially and essentially aimed at depositing a thin intermediate layer between two III-V layers at a reduced growth temperature.
  • the reduced growth temperature for the intermediate layer should, if possible, be at least 100 ° C. below the growth temperature for the III-V layers.
  • the lattice constant of the intermediate layer is preferably smaller than the lattice constant of the III-V layers.
  • a multiplicity of intermediate layers, each separated by a III-V layer is deposited. Multiple thin intermediate layers are thus deposited on one III-N layer each.
  • the intermediate layer is preferably deposited untensioned.
  • the intermediate layer can contain boron or silicon.
  • the thickness of the intermediate layer is in the annometer range.
  • the III-N layers deposited between the intermediate layers can be considerably thicker. They can be a few micrometers thick.
  • the III-V layer grows on the at low temperatures different intermediate layer on pseudomorph. This leads to tension.
  • a compressive prestress is preferably achieved.
  • the compressive pre-tension is achieved with the low-temperature intermediate layer.
  • the method according to the invention enables the growth of essentially unstressed III-V semiconductor layers in the system (AI, Ga, In) (As, PN, Sb) by the growth of low-temperature layers between III-V layers, the low temperature always showing a clear temperature , is at least 100 ° C below the usual growth temperature.
  • the preferred compressive tension is created by the tensile stress during cooling. In the case of an indium phosphite system, this can be carried out by means of a GaAs, AlAs, AlInAs or GalnAlAsPN low-temperature layers.
  • aluminum arsenide, boron aluminum arsenide and also boron arsenite are considered as compressively tensioning low-temperature layers. However, it can also be used for materials in the nitridic system.
  • the thermal stress but also the strain induced by lattice mismatch, can be reduced again and again to such an extent that layers of any thickness can be deposited, which are then essentially unstressed overall.
  • the second task mentioned at the outset is achieved by first depositing a III-V semiconductor layer on a non-III-V substrate, in particular on a silicon substrate, by introducing gaseous starting materials into the process chamber of a reactor.
  • This III-V semiconductor layer is deposited on a first substrate which has an orientation which is optimized for the deposition of the III-V layer.
  • a GaN layer is particularly suitable for a silicon substrate with an (III) orientation.
  • this semiconductor layer is detached from the substrate together with a thin film of the first substrate.
  • the thickness of the detached film is, for example, 50 ⁇ m.
  • the detached layer is applied to a second substrate together with the thin film of the first substrate.
  • This second substrate can be a silicon substrate with a (100) orientation.
  • the detached layer is preferably applied by gluing.
  • a masking step can follow this bonding.
  • it is provided that lateral areas of the applied layer are removed as far as the area of the second substrate. This removal is preferably done by etching.
  • a layer sequence with silicon technology is then applied to the (100) silicon crystal which then forms the surface.
  • These layers, which are adjacent to the III-V layer structures, can be insulation layers, electrically conductive layers or p- or n-doped silicon layers.
  • the deposited III-N layer is preferably a gallium nitride layer.
  • a seed layer made of gallium arsenide is first deposited on a silicon substrate.
  • a gallium arsenide buffer layer is deposited on this seed layer at the typical growth temperatures known in the literature for the deposition of high quality gallium arsenide layers in the MOCVD or VPE process or MBE.
  • a low-temperature intermediate layer is then deposited on this first III-V layer.
  • the temperature inside the process chamber i.e. the substrate temperature
  • the gases required for the growth of the intermediate layer are then introduced into the process chamber. Trimethylaluminium nium and arsine or a boron compound.
  • the intermediate layer is deposited at this reduced temperature until the desired layer thickness, which is between 5 and 50 nm, is reached.
  • the layer thickness is preferably between 10 and 20 nm.
  • the temperature inside the process chamber is raised again. This is done by heating the substrate holder accordingly. Then another gallium arsenide layer is pseudomorphically deposited on the low-temperature intermediate layer. This gallium arsenide layer is considerably thicker than the low-temperature intermediate layer. Their thickness can be a few ⁇ m.
  • a further low-temperature intermediate layer can be deposited on the last described gallium arsenide layer, which also has a smaller lattice constant than gallium arsenide.
  • Gallium arsenide can be deposited again on this intermediate layer. Overall, the process leads to a thick gallium arsenide layer with few dislocations.
  • FIG. 1 schematically shows in cross section a first substrate with an ( ⁇ ll) crystal orientation optimized for the deposition of a III-V layer
  • 2 shows the substrate with III-V layers deposited thereon
  • 3 shows the substrate with a III-V layer structure detached therefrom, together with a thin film of the first substrate
  • FIG. 5 shows an illustration according to FIG. 4 after a lateral structuring by etching.
  • a (III) silicon substrate is shown in regions and in cross section in FIG. 1.
  • Two III-V layers 2, 3 are deposited on this silicon substrate (see FIG. 2) in the exemplary embodiment.
  • These layers 2, 3 can be gallium arsenide, gallium nitride, indium phosphide or any other III-V composition.
  • This layer sequence 2, 3 is removed together with a thin film V of the first substrate 1.
  • the detached layer system V, 2, 3 is then glued onto a second substrate (see FIG. 4).
  • the second substrate is preferably a (100) silicon substrate.
  • the (100) silicon surface is suitable for the deposition of further, in particular silicon
  • the intermediate product shown in FIG. 4 is structured laterally; this can be done, for example, by masking. Then the glued layer sequence Y, 2, 3 is etched away. This layer sequence is removed as far as into the second substrate 4, so that the exposed surface is in it etched area 5 is a (100) silicon surface on which CMOS structures can be deposited.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Semiconductor Lasers (AREA)

Abstract

L'invention concerne un procédé de déposition de couches de semi-conducteurs III-V épaisses sur un substrat non III-V, notamment un substrat de silicium, par introduction de produits de départ gazeux dans la chambre de traitement d'un réacteur. L'invention vise à déposer de façon cristalline des couches de semi-conducteurs III-V épaisses sur un substrat de silicium, sans création de distorsions de réseau. A cet effet, une couche intermédiaire fine est déposée entre deux couches III-V à une température de croissance réduite.
EP02790389A 2001-12-21 2002-11-16 Procede de deposition de couches de semi-conducteurs iii-v sur un substrat non iii-v Withdrawn EP1459362A2 (fr)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
DE10163718 2001-12-21
DE10163718 2001-12-21
DE10206753 2002-02-19
DE10206753 2002-02-19
DE10219223A DE10219223A1 (de) 2001-12-21 2002-04-30 Verfahren zum Abscheiden von III-V-Halbleiterschichten auf einem Nicht-III-V-Substrat
DE10219223 2002-04-30
PCT/EP2002/012869 WO2003054929A2 (fr) 2001-12-21 2002-11-16 Procede de deposition de couches de semi-conducteurs iii-v sur un substrat non iii-v

Publications (1)

Publication Number Publication Date
EP1459362A2 true EP1459362A2 (fr) 2004-09-22

Family

ID=27214692

Family Applications (1)

Application Number Title Priority Date Filing Date
EP02790389A Withdrawn EP1459362A2 (fr) 2001-12-21 2002-11-16 Procede de deposition de couches de semi-conducteurs iii-v sur un substrat non iii-v

Country Status (6)

Country Link
US (1) US7078318B2 (fr)
EP (1) EP1459362A2 (fr)
JP (1) JP2006512748A (fr)
AU (1) AU2002366856A1 (fr)
TW (1) TWI265558B (fr)
WO (1) WO2003054929A2 (fr)

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Also Published As

Publication number Publication date
WO2003054929B1 (fr) 2004-06-10
AU2002366856A1 (en) 2003-07-09
US7078318B2 (en) 2006-07-18
JP2006512748A (ja) 2006-04-13
TW200301515A (en) 2003-07-01
AU2002366856A8 (en) 2003-07-09
WO2003054929A3 (fr) 2004-04-08
US20050026392A1 (en) 2005-02-03
WO2003054929A2 (fr) 2003-07-03
TWI265558B (en) 2006-11-01

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