EP1160871A2 - Charge compensation semiconductor device and method of making the same - Google Patents
Charge compensation semiconductor device and method of making the same Download PDFInfo
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- EP1160871A2 EP1160871A2 EP01112152A EP01112152A EP1160871A2 EP 1160871 A2 EP1160871 A2 EP 1160871A2 EP 01112152 A EP01112152 A EP 01112152A EP 01112152 A EP01112152 A EP 01112152A EP 1160871 A2 EP1160871 A2 EP 1160871A2
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 19
- 239000010703 silicon Substances 0.000 claims abstract description 19
- 239000011810 insulating material Substances 0.000 claims abstract description 3
- 238000000407 epitaxy Methods 0.000 claims description 10
- 238000002513 implantation Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 9
- 230000005669 field effect Effects 0.000 claims description 7
- 238000005530 etching Methods 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
Definitions
- the present invention relates to a compensation component and a process for its production.
- Compensation components are known for the fact that they have a drift path in the direction of current flow by side by side or one above the other and alternating n- and p-type areas is established. This n- and p-type regions are so highly doped that their charges compensate each other and, in the event of a lock, the entire drift section of cargo is cleared. In the event of passage bear the n- and p-conducting areas clearly higher than with conventional components areas of one Line type, for example, n-type areas, for Current flow at.
- Compensation components have a high blocking capacity a small on-resistance Ron.
- Compensation components can be known both as Design vertical components as well as lateral components (see also US 4,754,310 and US 5,216,275).
- For vertical components are for example source electrode and gate electrode on an upper side of a semiconductor body, while the drain electrode on the opposite side to the top Bottom is attached.
- the compensation areas are then n- and p-conductive layers, also called columns, which alternate with each other inside the semiconductor body extend in the direction between source and drain.
- two can be in one semiconductor body V-shaped trenches or trenches can be introduced, one of which Trench receives the source electrode and the gate electrode while the other trench is for the drain electrode is.
- the compensation areas are here superimposed and alternating n- and p-type layers in the area of the semiconductor body between the two trenches intended.
- the source electrode and the Drain electrode on the opposite surfaces of the semiconductor body manufactured much easier are used as source and drain in lateral structures.
- the generation of the reverse voltage absorbing drift distance from alternating n and p-type regions that extend in the vertical direction, using multiple epitaxy techniques subsequent ion implantation and diffusion z. B. in the so-called CoolMOS technology is relatively complex.
- Comparison of n- and p-type compensation areas to manufacture the structure of the vertical structures much easier, by n- and successively on a semiconductor wafer p-type layers are applied by epitaxy. Instead of an epitaxy may also include doping be made by implantation.
- the generation is for vertical structures the drift section is very complex, while with lateral structures the connections of source and drain pose significant problems pose.
- this object is achieved by a compensation component with the features of claim 1 or by a method with the features of claim 8 solved.
- drift zone With a field effect transistor as a compensation component are the two active zones between which there is the drift distance expands the source zone and the drain zone.
- the layer sequence forming the drift zone is then in the direction perpendicular to the line connecting the source zone and drain zone stacked, the individual layers with their Longitudinal expansion in the area between the source zone and the Drain zone run.
- a wide trench or trench is etched.
- the silicon semiconductor body is according to the desired voltage, for which the compensation component is to be used, selected.
- the KOH etchant is known to have the property of Silicon body to stop etching on a (111) plane while all other lattice planes of the silicon are etched. A so created on a (100) silicon substrate The trench or trench therefore has a wall inclination of approximately 55 ° on.
- each Layer that later form the drift path can adapted to the requirements of the compensation component become. Basically, the layers can be thinner the lower the temperature load.
- a planarization step is carried out, in which those applied to the semiconductor body Layers back up to the original surface of the Semiconductor body or wafers are removed.
- CMP chemical mechanical polishing
- anisotropic Etching can be used.
- the structure thus obtained now lies on the surface of the semiconductor body p- and n-type regions next to each other and can be easily connected laterally. These connections can be used for active zones at the same time for example a transistor can be used. So can a p-type trough across the p- and n-type areas, which later serves as a channel zone, for example by implantation be introduced. About another implantation can both the source zone and the connection for example n-type regions on the side of the drain zone respectively. Finally, there is also a gate electrode across the p- and n-conducting areas in the usual way manufactured.
- a compensation component in a vertical structure can be generated be by the semiconductor body after filling the trench or trenches with the p- and n-type layers thereof Back thinned so far by grinding and / or etching is that finally, for example, n-type regions of the back directly with a metal contact or indirectly via another n-type layer with a drain connection can be connected.
- the compensation component can is advantageously a MOS field effect transistor, a junction field effect transistor, an IGBT, an Schottky diode and so on.
- the compensation component can, for example, be designed for 600 V with a drift zone with a length of 40 ⁇ m .
- the n- and p-conducting regions have a thickness of approximately 2 ⁇ m and are each doped with 1.5 E 16 cm -3 charge carriers. Breakdown voltages of about 630 V can be achieved with a switch-on resistance Ron between drain and source of 7 ohm mm 2 .
- the doping in the individual layers can depend on the desired field of application for the compensation component can be varied.
- the electrical Field should be built so that it is in the whole structure from the layers and not only predominantly at the interface for an oxide filling in the remaining trench. Besides, is it is possible to take the longer path of the current through the deeper Layers due to increased doping Compensate layers and thus by a lower resistance (see also US 4,754,310).
- FIG. 1 shows a silicon semiconductor body 1 made of a (100) silicon substrate.
- this silicon body 1 with A wide trench was introduced using a KOH etchant.
- the etching with this etchant stops on one (111) plane, so that a trough-shaped trench 2 arises, the wall inclination is about 55 °.
- etchants other than KOH can also be used become.
- an isotropic etchant leads to a U-shape of the trench 2.
- the trench 2 not have a wall inclination of 55 °. Rather are other wall inclinations up to 90 ° possible, so that a U-shape for the trench.
- the silicon body 1 can be undoped. But he can also have an n-doping or a p-doping, which ultimately depends on the voltages for which the finished compensation component to be used.
- n-type layers 3 and p-type layers 4 are then successively applied either by doped epitaxy or by epitaxy and subsequent implantation or other doping.
- the thickness of these layers 3, 4 can be approximately 2 ⁇ m .
- a suitable doping concentration is approximately 1.5 U 16 cm -3 .
- other layer thicknesses and doping concentrations are also possible.
- a Planarization step in which the layers 3, 4 are etched back on the surface of the silicon body 1, so that the structure shown in Fig. 3 is formed.
- this planarization can possibly also be a CMP step and / or an anisotropic etching can be used. To this The structure shown in Fig. 3 is obtained.
- the remaining trench 2 is then covered with silicon dioxide or another insulating material. This filling the Residual trenches can also be made before planarization or completely eliminated. However, it is also possible after the epitaxial steps to form layers 3, 4 follow a further epitaxy step, in which the trench 2 is filled with low-doped silicon. The structure shown in FIG. 4 is thus obtained at an oxide layer 5 fills the remaining trench 2.
- the layers 3, 4 can, for example be endowed by oblique implantation.
- n-type layers 3 and the p-type layers 4 now lie on the surface of the silicon body 1, the n-type layers 3 and the p-type layers 4 as n-type and p-type regions next to each other and can be lateral, that is in Fig. 4 in Lateral direction, are interconnected. These connections can be used for source, body and drain zones at the same time of a MOS transistor can be used.
- a p-type well 6 are implanted, that in the finished compensation component as a BodyZone or channel is used. Over another implantation can then both a source zone 7 and a drain zone 8, which are both n-doped.
- the drain zone 8 serves as a connection for the n-conducting regions of the layers 3 on the drain side.
- the p-type regions of the layers 4 are connected via body zone 6.
- a gate electrode G can also cross to layers 3, 4 above the body zone 6 on a gate insulator made of, for example, silicon dioxide be attached.
- a compensation component is to be formed in a vertical structure then the structure of Fig. 4 is from the back thinned by grinding and etching until the n-type Layers 3 directly from the back with a metal contact or indirectly via another n-type Layer can be connected to a drain connection.
- This Thin is indicated in Fig. 4 by a chain line 9.
- the areas left and right of the insulator filling 5 with transistor cells as well as source and gate connection which in the same Way as in Fig. 5 or 6 can be done while on the Back, that is, in the area of the broken line 9, the drain connection is attached.
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Abstract
Description
Die vorliegende Erfindung betrifft ein Kompensationsbauelement sowie ein Verfahren zu dessen Herstellung. Kompensationsbauelemente zeichnen sich bekanntlich dadurch aus, daß sie eine Driftstrecke aufweisen, die in Stromflußrichtung durch neben- oder übereinander angeordnete und einander abwechselnde n- und p-leitende Gebiete aufgebaut ist. Diese n- und p-leitenden Gebiete sind dabei so hoch dotiert, daß sich ihre Ladungen gegenseitig kompensieren und im Sperrfall die gesamte Driftstrecke an Ladungen ausgeräumt wird. Im Durchlaßfall tragen die n- und p-leitenden Gebiete aber deutlich höher als bei herkömmlichen Bauelementen Gebiete des einen Leitungstyps also beispielsweise n-leitende Gebiete, zum Stromfluß bei.The present invention relates to a compensation component and a process for its production. Compensation components are known for the fact that they have a drift path in the direction of current flow by side by side or one above the other and alternating n- and p-type areas is established. This n- and p-type regions are so highly doped that their charges compensate each other and, in the event of a lock, the entire drift section of cargo is cleared. In the event of passage bear the n- and p-conducting areas clearly higher than with conventional components areas of one Line type, for example, n-type areas, for Current flow at.
Kompensationsbauelemente haben so bei hoher Sperrfähigkeit einen kleinen Einschaltwiderstand Ron.Compensation components have a high blocking capacity a small on-resistance Ron.
Kompensationsbauelemente lassen sich bekanntlich sowohl als Vertikalbauelemente als auch als Lateralbauelemente konzipieren (vgl. hierzu US 4 754 310 und US 5 216 275). Bei Vertikalbauelementen befinden sich beispielsweise Sourceelektrode und Gateelektrode auf einer Oberseite eines Halbleiterkörpers, während die Drainelektrode auf der zur Oberseite gegenüberliegenden Unterseite angebracht ist. Die Kompensationsgebiete sind dann n- und p-leitende Schichten, auch Säulen genannt, die sich einander abwechselnd im Innern des Halbleiterkörpers in der Richtung zwischen Source und Drain erstrekken.Compensation components can be known both as Design vertical components as well as lateral components (see also US 4,754,310 and US 5,216,275). For vertical components are for example source electrode and gate electrode on an upper side of a semiconductor body, while the drain electrode on the opposite side to the top Bottom is attached. The compensation areas are then n- and p-conductive layers, also called columns, which alternate with each other inside the semiconductor body extend in the direction between source and drain.
Bei Lateralbauelementen können in einem Halbleiterkörper zwei V-förmige Gräben oder Trenche eingebracht sein, von denen ein Trench die Sourceelektrode und die Gateelektrode aufnimmt, während der andere Trench für die Drainelektrode vorgesehen ist. Die Kompensationsgebiete sind hier als übereinander gelagerte und einander abwechselnde n- und p-leitende Schichten im Bereich des Halbleiterkörpers zwischen den beiden Trenchen vorgesehen.In the case of lateral components, two can be in one semiconductor body V-shaped trenches or trenches can be introduced, one of which Trench receives the source electrode and the gate electrode while the other trench is for the drain electrode is. The compensation areas are here superimposed and alternating n- and p-type layers in the area of the semiconductor body between the two trenches intended.
Für die Herstellung von Kompensationsbauelementen haben Vertikalstrukturen und Lateralstrukturen jeweils ihre eigenen Vor- und Nachteile:For the production of compensation components have vertical structures and lateral structures each have their own Advantages and disadvantages:
Bei Vertikalstrukturen können die Sourceelektrode und die Drainelektrode auf den einander gegenüberliegenden Oberflächen des Halbleiterkörpers erheblich einfacher hergestellt werden als Source und Drain in Lateralstrukturen. Jedoch ist bei Vertikalstrukturen die Erzeugung der die Sperrspannung aufnehmenden Driftstrecke aus einander abwechselnden n- und p-leitenden Gebieten, die sich in vertikaler Richtung erstrecken, in Aufbautechnik durch mehrfache Epitaxie mit jeweils nachfolgender Ionenimplantation und Diffusion z. B. in der sogenannten CoolMOS-Technologie relativ aufwendig. Bei Lateralstrukturen lassen sich dagegen die einander abwechselnden n- und p-leitenden Kompensationsgebiete im Vergleich zur Aufbautechnik der Vertikalstrukturen viel einfacher herstellen, indem auf einen Halbleiterwafer nacheinander n- und p-leitende Schichten durch Epitaxie aufgetragen werden. Anstelle einer Epitaxie kann gegebenenfalls auch eine Dotierung durch Implantation vorgenommen werden. Problematisch bei Lateralstrukturen sind aber, wie bereits oben erwähnt wurde, die Anschlüsse von Source und Drain, da die die Kompensationsgebiete bildenden Schichten möglichst niederohmig mit Source bzw. Drain verbunden werden müssen, was bisher nur mit Hilfe einer aufwendigen Trenchtechnologie mit anschließender Füllung möglich ist.With vertical structures, the source electrode and the Drain electrode on the opposite surfaces of the semiconductor body manufactured much easier are used as source and drain in lateral structures. However is in the case of vertical structures, the generation of the reverse voltage absorbing drift distance from alternating n and p-type regions that extend in the vertical direction, using multiple epitaxy techniques subsequent ion implantation and diffusion z. B. in the so-called CoolMOS technology is relatively complex. At Lateral structures, on the other hand, can be alternated Comparison of n- and p-type compensation areas to manufacture the structure of the vertical structures much easier, by n- and successively on a semiconductor wafer p-type layers are applied by epitaxy. Instead of an epitaxy may also include doping be made by implantation. Problematic with lateral structures but, as already mentioned above, the connections of source and drain, since that is the compensation areas layers with the lowest possible resistance Source or drain must be connected, which was previously only possible with With the help of an elaborate trench technology with subsequent Filling is possible.
Zusammenfassend ist also bei Vertikalstrukturen die Erzeugung der Driftstrecke sehr aufwendig, während bei Lateralstrukturen die Anschlüsse von Source und Drain erhebliche Probleme aufwerfen. In summary, the generation is for vertical structures the drift section is very complex, while with lateral structures the connections of source and drain pose significant problems pose.
Infolge der oben aufgezeigten Schwierigkeiten werden bisher Kompensationsbauelemente nur als Vertikaltransistoren hergestellt, wobei für den Aufbau der Driftstrecke mehrere Epitaxieschichten verwendet werden, in die jeweils mit Hilfe einer Implantation die im Endeffekt säulenartige Dotierung der n- und p-leitenden Gebiete eingebracht wird. Eine andere, ebenfalls aufwendige Methode zur Herstellung eines Vertikaltransistors besteht darin, für die Driftstrecke in sehr tief geätzte Trenches mittels verschiedener Verfahren die Dotierung einzubringen (vgl. US 4 754 310).As a result of the difficulties outlined above, so far Compensation components only manufactured as vertical transistors, with several epitaxial layers for the construction of the drift path used, each with the help of a Implantation the ultimately columnar doping of the n- and p-type areas. Another one, too elaborate method of manufacturing a vertical transistor is for the drift path in very deeply etched Trenches using different methods of doping to be introduced (cf. US 4,754,310).
Es ist Aufgabe der vorliegenden Erfindung, ein Kompensationsbauelement zu schaffen, bei dem Driftstrecke und Source- bzw. Drainanschluß auf einfache Weise herstellbar sind; außerdem soll ein vorteilhaftes Verfahren zum Erzeugen eines solchen Kompensationsbauelementes angegeben werden.It is an object of the present invention to provide a compensation component to create where the drift path and source or Drain connection can be produced in a simple manner; Moreover is intended to be an advantageous method for generating such Compensation component can be specified.
Diese Aufgabe wird erfindungsgemäß durch ein Kompensationsbauelement
mit den Merkmalen des Patentanspruches 1 bzw.
durch ein Verfahren mit den Merkmalen des Patentanspruches 8
gelöst.According to the invention, this object is achieved by a compensation component
with the features of
Bei einem Feldeffekttransistor als Kompensationsbauelement sind die beiden aktiven Zonen, zwischen denen sich die Driftstrecke ausdehnt, die Sourcezone und die Drainzone. Die die Driftzone bildende Schichtenfolge ist dann in der Richtung senkrecht zur Verbindungslinie zwischen Sourcezone und Drainzone gestapelt, wobei die einzelnen Schichten mit ihrer Längsausdehnung im Bereich zwischen der Sourcezone und der Drainzone verlaufen.With a field effect transistor as a compensation component are the two active zones between which there is the drift distance expands the source zone and the drain zone. The the The layer sequence forming the drift zone is then in the direction perpendicular to the line connecting the source zone and drain zone stacked, the individual layers with their Longitudinal expansion in the area between the source zone and the Drain zone run.
Vorteilhafte Weiterbildungen der Erfindung ergeben sich aus den Unteransprüchen.Advantageous developments of the invention result from the subclaims.
Bei der vorliegenden Erfindung wird also mittels beispielsweise eines KOH-Ätzmittels in einen Silizium-Halbleiterkörper ein breiter Graben bzw. Trench geätzt. Der Silizium-Halbleiterkörper ist dabei entsprechend der gewünschten Spannung, für die das Kompensationsbauelement eingesetzt werden soll, ausgewählt.In the present invention, for example of a KOH etchant in a silicon semiconductor body a wide trench or trench is etched. The silicon semiconductor body is according to the desired voltage, for which the compensation component is to be used, selected.
Das KOH-Ätzmittel hat bekanntlich die Eigenschaft, bei einem Siliziumkörper das Ätzen auf einer (111)-Ebene zu stoppen, während alle anderen Gitterebenen des Siliziums geätzt werden. Ein so auf einem (100)-Siliziumsubstrat entstehender Graben bzw. Trench weist daher eine Wandneigung von etwa 55° auf.The KOH etchant is known to have the property of Silicon body to stop etching on a (111) plane while all other lattice planes of the silicon are etched. A so created on a (100) silicon substrate The trench or trench therefore has a wall inclination of approximately 55 ° on.
Auf den auf diese Weise vorbereiteten und mit einem Trench mit einer Wandneigung von etwa 55° versehenen Siliziumkörper werden abwechselnd p- und n-leitende Schichten aufgebracht, was durch dotierte Epitaxie oder durch Epitaxie und nachfolgende Implantation geschehen kann. Die Schichtdicke der einzelnen Schichten, die später die Driftstrecke bilden, kann dabei den Anforderungen an das Kompensationsbauelement angepaßt werden. Grundsätzlich können die Schichten um so dünner sein, je geringer die Temperaturbelastung ist.In the way prepared and with a trench with a wall inclination of about 55 ° silicon body alternating p-type and n-type layers are applied, what through doped epitaxy or through epitaxy and subsequent Implantation can happen. The layer thickness of each Layers that later form the drift path can adapted to the requirements of the compensation component become. Basically, the layers can be thinner the lower the temperature load.
Nachdem in dem Graben bzw. Trench die gewünschte Anzahl von Schichten erzeugt ist, wird ein Planarisierungsschritt vorgenommen, bei dem die auf den Halbleiterkörper aufgetragenen Schichten zurück bis zu der ursprünglichen Oberfläche des Halbleiterkörpers oder Wafers abgetragen werden. Hier kann auch ein chemisch-mechanisches Polieren (CMP) oder eine anisotrope Ätzung eingesetzt werden.After the desired number of in the trench or trench Layers is created, a planarization step is carried out, in which those applied to the semiconductor body Layers back up to the original surface of the Semiconductor body or wafers are removed. Here can also chemical mechanical polishing (CMP) or anisotropic Etching can be used.
Sollte noch ein Graben übriggeblieben sein, so wird dieser mit Oxid gefüllt. Es ist aber auch möglich, einen solchen "Restgraben" bereits bei den Epitaxieschritten mit niedrig dotiertem Silizium aufzufüllen.If there is still a ditch left, it will be filled with oxide. But it is also possible to have one "Residual trench" with low epitaxial steps fill doped silicon.
Bei der so erhaltenen Struktur liegen nun an der Oberfläche des Halbleiterkörpers p- und n-leitende Gebiete nebeneinander und können ohne weiteres lateral miteinander verbunden werden. Diese Verbindungen können gleichzeitig für aktive Zonen beispielsweise eines Transistors verwendet werden. So kann quer zu den p- und n-leitenden Gebieten eine p-leitende Wanne, die später als Kanalzone dient, beispielsweise durch Implantation eingebracht werden. Über eine weitere Implantation kann sowohl die Sourcezone als auch der Anschluß für beispielsweise n-leitende Gebiete auf der Seite der Drainzone erfolgen. Schließlich wird noch eine Gateelektrode ebenfalls quer zu den p- und n-leitenden Gebieten in üblicher Weise hergestellt.The structure thus obtained now lies on the surface of the semiconductor body p- and n-type regions next to each other and can be easily connected laterally. These connections can be used for active zones at the same time for example a transistor can be used. So can a p-type trough across the p- and n-type areas, which later serves as a channel zone, for example by implantation be introduced. About another implantation can both the source zone and the connection for example n-type regions on the side of the drain zone respectively. Finally, there is also a gate electrode across the p- and n-conducting areas in the usual way manufactured.
Ein Kompensationsbauelement in Vertikalstruktur kann erzeugt werden, indem der Halbleiterkörper nach Füllen des Grabens bzw. Trenchs mit den p- und n-leitenden Schichten von dessen Rückseite her durch Schleifen und/oder Ätzen so weit gedünnt wird, daß schließlich beispielsweise n-leitende Gebiete von der Rückseite her direkt mit einem Metallkontakt oder indirekt über eine weitere n-leitende Schicht mit einem Drainanschluß verbunden werden können.A compensation component in a vertical structure can be generated be by the semiconductor body after filling the trench or trenches with the p- and n-type layers thereof Back thinned so far by grinding and / or etching is that finally, for example, n-type regions of the back directly with a metal contact or indirectly via another n-type layer with a drain connection can be connected.
Bei dem erfindungsgemäßen Kompensationsbauelement kann es sich in vorteilhafter Weise um einen MOS-Feldeffekttransistor, einen Junction-Feldeffekttransistor, einen IGBT, eine Schottky-Diode und so weiter, handeln.In the compensation component according to the invention, it can is advantageously a MOS field effect transistor, a junction field effect transistor, an IGBT, an Schottky diode and so on.
Das Kompensationsbauelement kann beispielsweise auf 600 V mit einer Driftzone mit einer Länge von 40 µm ausgelegt sein. Die n- und p-leitenden Gebiete haben dabei eine Dicke von etwa 2 µm und sind jeweils gleich hoch mit 1,5 E 16 cm-3 Ladungsträgern dotiert. Es können so Durchbruchsspannungen von etwa 630 V bei einem Einschaltwiderstand Ron zwischen Drain und Source von 7 Ohm mm2 erreicht werden.The compensation component can, for example, be designed for 600 V with a drift zone with a length of 40 μm . The n- and p-conducting regions have a thickness of approximately 2 μm and are each doped with 1.5 E 16 cm -3 charge carriers. Breakdown voltages of about 630 V can be achieved with a switch-on resistance Ron between drain and source of 7 ohm mm 2 .
Die Dotierung in den einzelnen Schichten kann abhängig von dem gewünschten Anwendungsgebiet für das Kompensationsbauelement variiert werden. Hierzu kann beispielsweise das elektrische Feld so aufgebaut werden, daß es in der ganzen Struktur aus den Schichten und nicht nur überwiegend an der Grenzfläche zu einer Oxidfüllung im Restgraben vorliegt. Außerdem ist es möglich, den längeren Weg des Stromes durch die tieferliegenden Schichten durch eine erhöhte Dotierung.in diesen Schichten und damit durch einen geringeren Widerstand zu kompensieren (vgl. hierzu auch US 4 754 310).The doping in the individual layers can depend on the desired field of application for the compensation component can be varied. For example, the electrical Field should be built so that it is in the whole structure from the layers and not only predominantly at the interface for an oxide filling in the remaining trench. Besides, is it is possible to take the longer path of the current through the deeper Layers due to increased doping Compensate layers and thus by a lower resistance (see also US 4,754,310).
Nachfolgend wird die Erfindung anhand der Zeichnungen näher erläutert. Es zeigen:
- Fig. 1 bis 4
- verschiedene schematische Schnittbilder, die die Herstellung des erfindungsgemäßen Kompensationsbauelementes veranschaulichen,
- Fig. 5
- eine vergrößerte Draufsicht auf einen lateralen Hochvolt-MOS-Transistor und
- Fig. 6
- einen vergrößerten Teilschnitt AA in dem Transistor von Fig. 5.
- 1 to 4
- various schematic sectional views which illustrate the production of the compensation component according to the invention,
- Fig. 5
- an enlarged plan view of a lateral high-voltage MOS transistor and
- Fig. 6
- 5 shows an enlarged partial section AA in the transistor from FIG. 5.
Fig. 1 zeigt einen Silizium-Halbleiterkörper 1 aus einem
(100)-Siliziumsubstrat. In diesem Siliziumkörper 1 wird mit
Hilfe eines KOH-Ätzmittels ein breiter Graben eingebracht.
Das mit diesem Ätzmittel vorgenommene Ätzen stoppt auf einer
(111)-Ebene, so daß ein trogförmiger Graben bzw. Trench 2
entsteht, dessen Wandneigung etwa 55° beträgt.1 shows a
Gegebenenfalls können auch andere Ätzmittel außer KOH verwendet
werden. Ein isotropes Ätzmittel führt beispielsweise zu
einer U-Form des Grabens 2.If necessary, etchants other than KOH can also be used
become. For example, an isotropic etchant leads to
a U-shape of the
Bei der vorliegenden Erfindung braucht also der Graben 2
nicht eine Wandneigung von 55° aufzuweisen. Vielmehr sind
auch andere Wandneigungen bis zu 90° möglich, so daß eine U-Form
für den Graben vorliegt. In the present invention, therefore, the
Der Siliziumkörper 1 kann undotiert sein. Er kann aber auch
eine n-Dotierung oder eine p-Dotierung aufweisen, was letztlich
davon abhängt, für welche Spannungen das fertige Kompensationsbauelement
eingesetzt werden soll.The
Auf die in Fig. 1 gezeigte Struktur werden sodann nacheinander
n-leitende Schichten 3 und p-leitende Schichten 4 entweder
durch dotierte Epitaxie oder durch Epitaxie und nachfolgende
Implantation oder sonstige Dotierung aufgebracht. Die
Dicke dieser Schichten 3, 4 kann bei etwa 2 µm liegen. Eine
geeignete Dotierungskonzentration beträgt etwa 1,5 E 16 cm-3.
Selbstverständlich sind aber auch andere Schichtdicken und
Dotierungskonzentrationen möglich.1, n-
In dem Beispiel von Fig. 2 sind lediglich fünf Schichten 3, 4
gezeigt. Gegebenenfalls können jedoch noch mehr Schichten in
den Graben 2 eingebracht werden, so daß dieser weitgehend mit
diesen Schichten 3, 4, die einander abwechseln, gefüllt ist.In the example of FIG. 2 there are only five
Nachdem die gewünschte Anzahl von Schichten 3, 4 in den Graben
2 bzw. auf den Siliziumkörper 1 aufgebracht ist, wird ein
Planarisierungsschritt vorgenommen, bei dem die Schichten 3,
4 auf der Oberfläche des Siliziumkörpers 1 zurückgeätzt werden,
so daß die in Fig. 3 gezeigte Struktur entsteht. Für
diese Planarisierung kann gegebenenfalls auch ein CMP-Schritt
und/oder eine anisotrope Ätzung eingesetzt werden. Auf diese
Weise wird die in Fig. 3 gezeigte Struktur erhalten.After the desired number of
Der noch verbliebene Graben 2 wird sodann mit Siliziumdioxid
oder einem anderen Isolierstoff gefüllt. Dieses Füllen des
Restgrabens kann auch vor der Planarisierung vorgenommen werden
oder aber ganz entfallen. Ebenso ist es aber auch möglich,
nach den Epitaxieschritten zur Bildung der Schichten 3,
4 einen weiteren Epitaxieschritt folgen zu lassen, in welchem
der Graben 2 mit niedrig dotiertem Silizium aufgefüllt wird.
Es wird damit die in Fig. 4 gezeigte Struktur erhalten, bei
der eine Oxidschicht 5 den Restgraben 2 füllt. The remaining
Bei einem U-förmigen Graben können die Schichten 3, 4 beispielsweise
durch Schrägimplantation dotiert werden.In the case of a U-shaped trench, the
Bei der in Fig. 4 gezeigten Struktur liegen nun an der Oberfläche
des Siliziumkörpers 1 die n-leitenden Schichten 3 und
die p-leitenden Schichten 4 als n-leitende und p-leitende Gebiete
nebeneinander und können lateral, also in Fig. 4 in
Seitenrichtung, miteinander verbunden werden. Diese Verbindungen
können gleichzeitig für Source-, Body- und Drain-Zonen
eines MOS-Transistors verwendet werden.4 now lie on the surface
of the
So kann, wie aus der Draufsicht von Fig. 5 und dem Schnitt
von Fig. 6 zu ersehen ist, quer zu den n- und p-leitenden
Schichten 3 bzw. 4 eine p-leitende Wanne 6 implantiert werden,
die bei dem fertigen Kompensationsbauelement als BodyZone
bzw. Kanal dient. Über eine weitere Implantation können
sodann sowohl eine Sourcezone 7 als auch eine Drainzone 8,
die beide n-dotiert sind, eingebracht werden. Die Drainzone 8
dient als Anschluß für die n-leitenden Gebiete der Schichten
3 auf der Drainseite. Die p-leitenden Gebiete der Schichten 4
sind über die Bodyzone 6 angeschlossen. Eine Gateelektrode G
kann ebenfalls quer zu den Schichten 3, 4 oberhalb der Bodyzone
6 auf einem Gateisolator aus beispielsweise Siliziumdioxid
angebracht werden.So, as from the top view of FIG. 5 and the
Soll ein Kompensationsbauelement in Vertikalstruktur gebildet
werden, dann wird die Struktur von Fig. 4 von der Rückseite
her durch Schleifen und Ätzen soweit gedünnt, daß die n-leitenden
Schichten 3 von der Rückseite her direkt mit einem Metallkontakt
oder indirekt über eine weitere n-leitende
Schicht mit einem Drainanschluß verbunden werden können. Dieses
Dünnen ist in Fig. 4 durch eine Strichpunktlinie 9 angedeutet.
Bei der auf diese Weise bis zu der Strichpunktlinie 9
gedünnten Struktur von Fig. 4 werden sodann die Bereiche
links und rechts von der Isolatorfüllung 5 mit Transistorzellen
sowie Source- und Gateanschluß versehen, was in gleicher
Weise wie in Fig. 5 bzw. 6 erfolgen kann, während auf der
Rückseite, also im Bereich der Strichlinie 9 der Drainanschluß
angebracht wird. A compensation component is to be formed in a vertical structure
then the structure of Fig. 4 is from the back
thinned by grinding and etching until the n-
- 11
- SiliziumkörperSilicon body
- 22nd
- Trench bzw. GrabenTrench or trench
- 33rd
- n-leitendes Gebiet bzw. n-leitende Schichtn-type region or n-type layer
- 44th
- p-leitendes Gebiet bzw. p-leitende Schichtp-type region or p-type layer
- 55
- OxidfüllungOxide filling
- 66
- BodyzoneBodyzone
- 77
- SourcezoneSource zone
- 88th
- DrainzoneDrain zone
- 99
- Strichpunktlinie für Dünnen von SiliziumkörperDash line for thin silicon body
Claims (11)
dadurch gekennzeichnet, dass
die Driftstrecke mit den p- und n-leitenden Gebieten (4, 3) um die Seitenflächen und die Bodenfläche des Trenches (2) geführt ist.Compensation component with a drift path provided between two active zones, consisting of a stacked layer sequence of p- and n-type regions (4, 3) and a trough-shaped trench (2),
characterized in that
the drift path with the p- and n-conducting regions (4, 3) is guided around the side surfaces and the bottom surface of the trench (2).
dadurch gekennzeichnet, dass
die Seitenflächen des Trenches (2) von der Bodenfläche aus im Wesentlichen schräg nach oben verlaufen, sodass die Öffnung des Trenches (2) breiter als die Bodenfläche ist.Compensation component according to claim 1,
characterized in that
the side surfaces of the trench (2) run essentially obliquely upwards from the base surface, so that the opening of the trench (2) is wider than the base surface.
dadurch gekennzeichnet, dass
der Trench (2) zusätzlich zu den n- und p-leitenden Gebieten (3, 4) mit einer Oxidfüllung (5) versehen ist.Compensation component according to claim 1 or 2,
characterized in that
the trench (2) is provided with an oxide filling (5) in addition to the n- and p-conducting regions (3, 4).
dadurch gekennzeichnet, dass
die Wandneigung der Seitenflächen des Trenches (2) etwa 55° beträgt.Compensation component according to one of Claims 1 to 3,
characterized in that
the wall slope of the side surfaces of the trench (2) is approximately 55 °.
dadurch gekennzeichnet, dass
es ein MOS-Feldeffekttransistor ist, bei dem die Sourcezone (7), die Bodyzone (6) und Gate (G) auf einer Seite des Trenches (2) und die Drainzone (8) auf der anderen Seite des Trenches oder bei dessen Bodenfläche vorgesehen sind.Compensation component according to one of Claims 1 to 4,
characterized in that
it is a MOS field effect transistor in which the source zone (7), the body zone (6) and gate (G) are provided on one side of the trench (2) and the drain zone (8) on the other side of the trench or on the bottom surface thereof are.
dadurch gekennzeichnet, dass
es ein MOS-Feldeffekttransistor,ein Junction-Feldeffekttransistor, ein IGBT oder eine Schottky-Diode ist.Compensation component according to one of Claims 1 to 4,
characterized in that
it is a MOS field effect transistor, a junction field effect transistor, an IGBT or a Schottky diode.
dadurch gekennzeichnet, dass
characterized in that
dadurch gekennzeichnet, dass
der Halbleiterkörper (1) von dessen Rückseite bis zu der untersten Schicht (3) unter der Bodenfläche des verbliebenen Trenches (2) gedünnt wird, um eine Vertikalstruktur der Driftstrecke zu erhalten.Method according to claim 7,
characterized in that
the semiconductor body (1) is thinned from its rear side to the lowermost layer (3) below the bottom surface of the remaining trench (2) in order to obtain a vertical structure of the drift path.
dadurch gekennzeichnet, dass
als Ätzmittel KOH verwendet wird.Method according to claim 7 or 8,
characterized in that
KOH is used as the etchant.
dadurch gekennzeichnet, dass
die p- und n-leitenden Schichten durch dotierte Epitaxie oder durch Epitaxie und Implantation hergestellt werden.Method according to one of claims 7 to 9,
characterized in that
the p- and n-type layers are produced by doped epitaxy or by epitaxy and implantation.
dadurch gekennzeichnet, dass
zum Herstellen eines Feldeffekttransistors auf einer Seite des Trenches (2) quer zu den p- und n-leitenden Schichten (4, 3) eine Sourcezone (7) und eine Bodyzone (6) und auf der anderen Seite des Trenches (2) eine Drainzone (8) eingebracht werden.Method according to one of claims 7 to 9,
characterized in that
for producing a field effect transistor on one side of the trench (2) transverse to the p- and n-conducting layers (4, 3) a source zone (7) and a body zone (6) and on the other side of the trench (2) a drain zone (8) can be introduced.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE10026924A DE10026924A1 (en) | 2000-05-30 | 2000-05-30 | Compensation component |
| DE10026924 | 2000-05-30 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| EP1160871A2 true EP1160871A2 (en) | 2001-12-05 |
| EP1160871A3 EP1160871A3 (en) | 2003-08-13 |
| EP1160871B1 EP1160871B1 (en) | 2004-11-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP01112152A Expired - Lifetime EP1160871B1 (en) | 2000-05-30 | 2001-05-17 | Charge compensation semiconductor device and method of making the same |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US6465869B2 (en) |
| EP (1) | EP1160871B1 (en) |
| DE (2) | DE10026924A1 (en) |
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| US6316807B1 (en) * | 1997-12-05 | 2001-11-13 | Naoto Fujishima | Low on-resistance trench lateral MISFET with better switching characteristics and method for manufacturing same |
| US6005279A (en) * | 1997-12-18 | 1999-12-21 | Advanced Micro Devices, Inc. | Trench edge spacer formation |
| EP0973203A3 (en) * | 1998-07-17 | 2001-02-14 | Infineon Technologies AG | Semiconductor layer with lateral variable doping and its method of fabrication |
-
2000
- 2000-05-30 DE DE10026924A patent/DE10026924A1/en not_active Withdrawn
-
2001
- 2001-05-17 DE DE50104523T patent/DE50104523D1/en not_active Expired - Lifetime
- 2001-05-17 EP EP01112152A patent/EP1160871B1/en not_active Expired - Lifetime
- 2001-05-30 US US09/867,502 patent/US6465869B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4754310A (en) * | 1980-12-10 | 1988-06-28 | U.S. Philips Corp. | High voltage semiconductor device |
| GB2309336A (en) * | 1996-01-22 | 1997-07-23 | Fuji Electric Co Ltd | Drift regions in semiconductor devices |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1160871A3 (en) | 2003-08-13 |
| US20010048144A1 (en) | 2001-12-06 |
| EP1160871B1 (en) | 2004-11-17 |
| DE50104523D1 (en) | 2004-12-23 |
| US6465869B2 (en) | 2002-10-15 |
| DE10026924A1 (en) | 2001-12-20 |
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