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EP1010204A1 - Semiconductor structure comprising an alpha silicon carbide zone, and use of said semiconductor structure - Google Patents

Semiconductor structure comprising an alpha silicon carbide zone, and use of said semiconductor structure

Info

Publication number
EP1010204A1
EP1010204A1 EP98928113A EP98928113A EP1010204A1 EP 1010204 A1 EP1010204 A1 EP 1010204A1 EP 98928113 A EP98928113 A EP 98928113A EP 98928113 A EP98928113 A EP 98928113A EP 1010204 A1 EP1010204 A1 EP 1010204A1
Authority
EP
European Patent Office
Prior art keywords
silicon carbide
semiconductor structure
semiconductor
polytype
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98928113A
Other languages
German (de)
French (fr)
Inventor
Reinhold SCHÖRNER
Dietrich Stephani
Dethard Peters
Peter Friedrichs
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SiCED Electronics Development GmbH and Co KG
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Publication of EP1010204A1 publication Critical patent/EP1010204A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors

Definitions

  • the invention relates to a semiconductor structure which contains an interface between a region made of a predetermined ⁇ -silicon carbide polytype and an electrically insulating region, the electrical conductivity in the silicon carbide region being induced at the interface by
  • Such semiconductor structures are e.g. from "IEEE Electronic Electronics Letters", Vol. 1 8, No. 3, March 1991, pages 93 to 95. Furthermore, the invention relates to the use of the aforementioned semiconductor structure.
  • Silicon carbide in monocrystalline form is a semiconductor material with excellent physical properties, which make this semiconductor material appear interesting, particularly for power electronics, especially in power electronics applications due to its low breakthrough field strength and good thermal conductivity. Since the commercial availability of single-crystal substrate wafers, especially those made from 6H and 4H silicon carbide polytypes, has increased, power semiconductor components based on silicon carbide, such as e.g. Silicon carbide Schottky diodes, increasing attention. However, the previously known unipolar silicon carbide power MOSFETs still have problems with regard to important properties, such as the forward resistance.
  • a unipolar MOSFET is presented, for example, which was produced on the basis of a 6H-silicon-carbide wafer by double ion implantation (so-called D-MOSFET).
  • D-MOSFET double ion implantation
  • the current is controlled in a semiconductor region made of silicon carbide with a lateral current flow, the so-called channel zone, which is located in the silicon carbide region at an interface between the silicon carbide semiconductor region and an electrically insulating region (for example S ⁇ 0 2 ).
  • the current is passed vertically through the component in a second silicon carbide semiconductor region, the so-called drift zone.
  • the 4H-silicon carbide polytype with a volume conductivity Tuning mobility of the free charge carriers of about 800 cm 2 V -1 s ⁇ clearly has an advantage over 6H-Silicum carbide, which only has a mobility of about 100 cnXXs -1 .
  • the influence of the polytype selection on the second influencing variable which is decisive for the forward resistance is not taken into account here, namely the conductivity m of the channel zone, which, apart from geometrical variables, is essentially determined by the properties of the boundary layer between the silicon carbide semiconductor region and the electrically insulating region.
  • the invention is based on the object of designing the semiconductor structure with the features mentioned at the outset in such a way that improved properties, in particular an improved forward resistance, result compared to the prior art.
  • the invention is based on the knowledge that the distribution of the electrically effective defects (traps) at the interface between a semiconductor region and an electrically insulating region determines the conductivity of the semiconductor at the interface and thus essentially the forward resistance of the complete semiconductor structure.
  • Studies on silicon carbide have shown that, regardless of the polytype, an energetic band of high defect density forms, which is at a fixed energetic distance from the valence band. This band has an energetically comparatively sharply defined lower edge, which is approximately 2.9 eV above the valence band edge.
  • the selection of the polytype according to the invention ensures that the defect band is energetically within the conduction band and thus has a significantly lower influence on the conductivity than is the case with the polytypes with a higher bandgap commonly used.
  • the ⁇ -silicon carbide polytype is selected in accordance with the invention, advantageous semiconductor structures are obtained with the features mentioned in the preamble, which have improved properties compared to the prior art.
  • the on-resistance can be advantageous, e.g. can be reduced by a factor of 20.
  • the ⁇ -silicon carbide semiconductor region has a band gap which is at least 5 meV smaller than the 6H-silicon carbide polytype.
  • the rhomboed ⁇ ⁇ -silicon carbide polytypes are particularly advantageous, in particular the 15R type or the 21R type.
  • 15R-silicon carbide has a band gap of 2.79 eV at room temperature, which is therefore below the comparison value of 6H-S1I1-cium carbide (2.91 eV) according to the invention.
  • the 4H or 6H silicon carbide polytypes excluded according to the invention are not suitable polytypes due to their high bandgap of 3.15 eV (4H silicon carbide) and 2.91 eV (6H silicon carbide), although they have so far been used in the area of silicon carbide performance electronics have been used almost exclusively for reasons of commercial availability.
  • Another advantageous embodiment takes advantage of the fact that in order to achieve the advantageous conductivity at the interface, only a narrow semiconductor region in the immediate vicinity of the electrically insulating region has to be formed from the claimed ⁇ -silicon carbide polytype.
  • Semiconductor regions which are adjacent to this narrow region can thus consist either of the same or at least partially of a different silicon carbide polytype or also of a different semiconductor material than silicon carbide or of a complex structure with at least one semiconductor material other than silicon carbide .
  • the semiconductor structure according to the invention can be designed as a MOSFET structure, in particular as a D-MOSFET structure or as a U-MOSFET structure, or as an IGBT structure. Such Structures are often used in power electronics.
  • the semiconductor structure according to the invention is used to construct a semiconductor component or a complex semiconductor circuit.
  • D-MOSFET components such as the semiconductor structure indicated in the figure and designated HS, are important unipolar power components.
  • the current is controlled by means of a lateral current flow I L and on the other hand in the drift zone composed of a silicon carbide semiconductor layer 3 and a silicon carbide substrate 2 it is guided through the component by means of a vertical current flow I.
  • vertical current flow is understood to mean a current flow in a direction that is perpendicular to an interface 20 of the silicon carbide semiconductor layer 3.
  • lateral is understood to mean a direction that runs parallel to a direction within this interface 20.
  • One of the determining variables for the forward resistance of the D-MOSFET component is the conductivity in the area of the lateral current conduction I L , the so-called channel. In the switched-on state, these channels are formed as regions of larger base regions 11 adjacent to interfaces 20 due to induced charges.
  • the decisive interfaces 20 are shown in the figure by a stronger line. highlighted.
  • the semiconductor structure is located precisely in these areas of the D-MOSFET component. At least this region of the base region 11 near the interface, which adjoins the electrically insulating region formed by a first oxide layer 13a, consists of an ⁇ -silicon carbide polytype with a smaller band gap than that of 6H silicon carbide. For example, a 15R silicon carbide poly type is suitable.
  • the electrically insulating region arranged above the base region 11 can, as in the exemplary embodiment shown in the figure, be constructed from only a single layer. According to other advantageous embodiments, however, several layers, preferably also made of different materials, can be provided for this area.
  • the first oxide layer 13a shown in the figure, the so-called gate oxide can advantageously consist of SiO 2 material, in particular thermal SiO 2 material. In other embodiments, however, this layer can also consist of a non-oxide, electrically insulating material, in particular of SiN 4 .
  • Source regions are denoted by 10, base regions by 11, base contact regions by 12, a first oxide layer by 13a, a second oxide layer by 13b, a gate electrode by 14, a source electrode by 15 and a drain electrode by 16.
  • the second oxide layer 13b (insulating oxide) serves for insulation between the gate electrode 14 and the source electrode 15 and consists of an SiO 2 deposited by means of an LPCVD process (Low Pressure Chemical Vapor Deposition).
  • Each base region 11 is implanted as a 15R silicon carbide semiconductor region in a silicon carbide layer 3 grown epitaxially on a silicon carbide substrate 2 and is doped in the opposite way to the silicon carbide layer 3.
  • the pn junctions 17 each formed between the base regions 11 and the silicon carbide layer 3 essentially absorb the reverse voltage when the D-MOSFET component is blocked.
  • At least one source region 10 is implanted in each base region 11, which is doped opposite to the base region 11 and therefore forms a pn junction 18 with the associated base region 11.
  • Each source region 10 is electrically short-circuited with the associated base region 11 via the source electrode.
  • the base regions 11 are preferably doped with boron and consequently p-type.
  • they can be more heavily doped and thus p + -le ⁇ tend.
  • the source regions 10 and the silicon carbide layer 3 are preferably doped with nitrogen and thus n-type.
  • the drain electrode 16 is arranged on the side of the silicon carbide substrate 2 facing away from the silicon carbide layer 3.
  • the silicon carbide substrate 2 can also be provided with an implanted, highly doped dramatic region.
  • the D-MOSFET thus has a vertical structure.
  • the silicon carbide substrate 2 m in the illustrated embodiment is of the same conductivity type as the grown silicon carbide layer 3, then there is a MOSFET structure.
  • the silicon carbide substrate 2 is of the opposite conductivity type as the silicon carbide layer 3, an additional pn junction between the source electrode 15 and the drain electrode 16 is connected between the layer 3 and the substrate 2 e. Then there is an IGBT structure.

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention concerns a semiconductor structure (HS) comprising at least an alpha silicon carbide zone (3, 10, 11) and an electrical insulation zone (13a), consisting for example of an oxide coating, between which is located an interface (20). The selection of an alpha silicon carbide polytype, whereof the forbidden band is smaller than that of H6 silicon carbide polytype, for at least one zone close to the interface, results in high mobility of charge carriers in said zone.

Description

Beschreibungdescription

HALBLEITERSTRUKTUR MIT EINEM ALPHA-SILIZIUMCARBIDBEREICH SOWIE VERWENDUNG DIESER HALBLEΠΈRSTRUKTURSEMICONDUCTOR STRUCTURE WITH AN ALPHA-SILICON CARBIDE AREA AND USE OF THIS SEMICONDUCTOR STRUCTURE

Die Erfindung bezieht sich auf eine Halbleiterstruktur, die eine Grenzflache zwischen einem Bereich aus einem vorbestimmten α-Siliciumcarbid-Polytyp und einem elektrisch isolierenden Bereich enthalt, wobei die elektrische Leitfähigkeit im Siliciumcarbidbereich an der Grenzflache durch induzierteThe invention relates to a semiconductor structure which contains an interface between a region made of a predetermined α-silicon carbide polytype and an electrically insulating region, the electrical conductivity in the silicon carbide region being induced at the interface by

Ladungen veränderbar ist. Derartige Halbleiterstrukturen sind z.B. aus „ IEEE El ectron Devi ce Let ters " , Vol . 1 8, No . 3 , März 1991 , Sei ten 93 bis 95, bekannt. Ferner bezieht sich die Erfindung auf die Verwendung der vorgenannten Halbleiter- Struktur.Charges is changeable. Such semiconductor structures are e.g. from "IEEE Electronic Electronics Letters", Vol. 1 8, No. 3, March 1991, pages 93 to 95. Furthermore, the invention relates to the use of the aforementioned semiconductor structure.

Siliciumcarbid m einkristalliner Form ist ein Halbleiter- material mit hervorragenden physikalischen Eigenschaften, die dieses Halbleitermateπal unter anderem aufgrund seiner nohen Durchbruchfeldstarke und seiner guten thermischen Leitfähigkeit besonders für die Leistungselektronik auch noch bei Anwendungen im kV-Bereich interessant erscheinen lassen. Da die kommerzielle Verfügbarkeit einkristallmer Substratwafer speziell aus 6H- und 4H-Sιlιcιumcarbιd-Polytypen gestiegen ist, finden nun auch Leistungshalbleiterbauelemente auf Sili- ciu carbidbasis, wie z.B. Siliciumcarbid-Schottky-Dioden, zunehmend an Beachtung. Bei den bislang bekannten unipolaren Siliciumcarbid-Leistungs-MOSFETs bestehen jedoch noch Probleme, was wichtige Eigenschaften, wie etwa den Durchlaß- widerstand, betrifft.Silicon carbide in monocrystalline form is a semiconductor material with excellent physical properties, which make this semiconductor material appear interesting, particularly for power electronics, especially in power electronics applications due to its low breakthrough field strength and good thermal conductivity. Since the commercial availability of single-crystal substrate wafers, especially those made from 6H and 4H silicon carbide polytypes, has increased, power semiconductor components based on silicon carbide, such as e.g. Silicon carbide Schottky diodes, increasing attention. However, the previously known unipolar silicon carbide power MOSFETs still have problems with regard to important properties, such as the forward resistance.

Im folgenden wird des öfteren von Bandabstanden von Silicium- carbid-Polytypen die Rede sein. Es versteht sich dabei, daß die für den Vergleich heranzuziehenden Bandabstandswerte unter der Prämisse gleicher Praparations-, Meß- sowie Umgebungsbedingungen zu ermitteln sind. Die im folgenden genannten diesbezüglichen Werte gelten jeweils für Raumtemperatur. In „Properties of Silicon Carbide " , edi ted by G. L . Harri s , Verlag INSPEC, London, GB, 1995, Sei ten 74 -80 sind dieThe following will often refer to the bandgaps of silicon carbide polytypes. It goes without saying that the bandgap values to be used for the comparison under the premise of the same preparation, measurement and environmental conditions. The relevant values given below apply to room temperature. In "Properties of Silicon Carbide", edited by G. L. Harris, Publisher INSPEC, London, GB, 1995, pages 74-80 are the

Bandabstande bei einer Temperatur von 4 K für verschiedene Siliciumcarbid-Polytypen dokumentiert .Bandgaps documented at a temperature of 4 K for different silicon carbide polytypes.

In IEEE Electron Device Letters, Vol. 18, No . 3, März 1997, Seiten 93 bis 95, wird z.B. ein unipolarer MOSFET vorgestellt, der auf Basis eines 6H-Sιlιcιumcarbιd-Wafers durch eine doppelte Ionenimplantation hergestellt wurde (sogenannte D-MOSFET) . Bei einem derartigen D-MOSFET wird der Strom m einem Halbleiterbereich aus Siliciumcarbid mit lateralem Stromfluß, der sogenannten Kanalzone, die sich im Silicium- carbidbereich an einer Grenzflache zwischen dem Silicium- carbidhalbleiterbereich und einem elektrisch isolierenden Bereich (z.B. Sι02) befindet, gesteuert. Im Anschluß daran wird der Strom m einem zweiten Siliciumcarbidhalbleiter- bereich, der sogenannten Driftzone, vertikal durch das Bauelement gefuhrt.In IEEE Electron Device Letters, Vol. 18, No. 3, March 1997, pages 93 to 95, a unipolar MOSFET is presented, for example, which was produced on the basis of a 6H-silicon-carbide wafer by double ion implantation (so-called D-MOSFET). In such a D-MOSFET, the current is controlled in a semiconductor region made of silicon carbide with a lateral current flow, the so-called channel zone, which is located in the silicon carbide region at an interface between the silicon carbide semiconductor region and an electrically insulating region (for example Sι0 2 ). Subsequently, the current is passed vertically through the component in a second silicon carbide semiconductor region, the so-called drift zone.

Mit dem vorgestellten D-MOSFET konnte gegenüber dem Stand der Technik bereits eine Verbesserung m bezug auf den Durchlaß- widerstand erzielt werden. Weitere Verbesserungen speziell des Durchlaßwiderstandes, der im wesentlichen von der Leitfähigkeit der Kanal- und der Driftzone abhangt, werden m „IEEE Electron Device Letters", Vol. 18, No . 3, März 1997, Seiten 93 bis 95 durch einen Mateπalwechsel vom 6H-Sιlιcιum- carbid-Polytyp auf den 4H-Sιlιcιumcarbιd-Polytyp m Aussicht gestellt. Diese Aussage basiert dabei auf Überlegungen, die lediglich die (Volumen) -Leitfähigkeit m der Driftzone m Betracht ziehen. Bei einem vertikalen Stromfluß m Richtung der kristallographischen c-Achse ist hier der 4H-Sιlιcιum- carbid-Polytyp mit einer die Volumenleitfahigkeit be- stimmenden Beweglichkeit der freien Ladungsträger von etwa 800 cm2V-1s~ deutlich im Vorteil gegenüber 6H-Sιlιcιumcarbιd, das lediglich eine Beweglichkeit von etwa 100 cnXXs-1 aufweist. Unberücksichtigt bleibt hierbei jedoch der Einfluß der Polytypenauswahl auf die zweite für den Durchlaßwiderstand maßgebliche Einflußgroße, nämlich die Leitfähigkeit m der Kanalzone, die außer durch geometrische Großen wesentlich durch die Eigenschaften der Grenzschicht zwischen dem Sili- ciumcarbidhalbleiterbereich und dem elektrisch isolierenden Bereich bestimmt wird.With the D-MOSFET presented, an improvement m in relation to the forward resistance could already be achieved compared to the prior art. Further improvements, particularly of the forward resistance, which essentially depends on the conductivity of the channel and the drift zone, are described in "IEEE Electron Device Letters", vol. 18, no. 3, March 1997, pages 93 to 95 by a change of material from 6H- Sιlιcιum-carbid-polytype placed on the 4H-Sιlιcιumcarbιd-polytype m prospect.This statement is based on considerations that only take into account the (volume) conductivity m of the drift zone m. With a vertical current flow m is the direction of the crystallographic c-axis here the 4H-silicon carbide polytype with a volume conductivity Tuning mobility of the free charge carriers of about 800 cm 2 V -1 s ~ clearly has an advantage over 6H-Silicum carbide, which only has a mobility of about 100 cnXXs -1 . However, the influence of the polytype selection on the second influencing variable which is decisive for the forward resistance is not taken into account here, namely the conductivity m of the channel zone, which, apart from geometrical variables, is essentially determined by the properties of the boundary layer between the silicon carbide semiconductor region and the electrically insulating region.

Der Erfindung liegt nun die Aufgabe zugrunde, die Halbleiter- struktur mit den eingangs genannten Merkmalen dahingehend auszugestalten, daß gegenüber dem Stand der Technik verbes- serte Eigenschaften, insbesondere ein verbesserter Durchlaßwiderstand, resultieren.The invention is based on the object of designing the semiconductor structure with the features mentioned at the outset in such a way that improved properties, in particular an improved forward resistance, result compared to the prior art.

Diese Aufgabe wird erfmdungsgemaß mit den Merkmalen des Anspruchs 1 gelost. Für den Silic u carbidbereich ist ein vom 4H- und 6H- verschiedener α-Siliciumcarbid-Polytyp vorgesehen, dessen Bandabstand höchstens dem des 6H-Sιlιcιumcarbιd- Polytyps entspricht.This object is achieved according to the invention with the features of claim 1. For the silicon and carbide range, an α-silicon carbide polytype different from 4H and 6H is provided, the bandgap of which corresponds at most to that of the 6H-silicon carbide polytype.

Die Erfindung beruht dabei auf der Erkenntnis, daß die Ver- teilung der elektrisch wirksamen Defekte (Haftstellen) an der Grenzflache zwischen einem Halbleiterbereich und einem elektrisch isolierenden Bereich die Leitfähigkeit des Halbleiters an der Grenzflache und somit wesentlich den Durchlaßwiderstand der kompletten Halbleiterstruktur bestimmt. Unter- suchungen an Siliciumcarbid haben gezeigt, daß sich unabhängig vom Polytyp ein energetisches Band hoher Defektdichte ausbildet, welches sich im festen energetischen Abstand zum Valenzband befindet. Dieses Band hat eine energetisch ver- altnismaßig scharf begrenzte Unterkante, die bei ca. 2,9 eV oberhalb der Valenzbandkante liegt. Da die energetische Lage des Valenzbandes bei Siliciumcarbid unabhängig vom Polytyp ist, gewährleistet die erfmdungsgemaße Auswahl des Polytyps, daß das Defektband energetisch innerhalb des Leitungsbandes liegt und somit die Leitfähigkeit deutlich geringer beem- flußt, als das bei den üblicherweise verwendeten Polytypen mit höherem Bandabstand der Fall ist.The invention is based on the knowledge that the distribution of the electrically effective defects (traps) at the interface between a semiconductor region and an electrically insulating region determines the conductivity of the semiconductor at the interface and thus essentially the forward resistance of the complete semiconductor structure. Studies on silicon carbide have shown that, regardless of the polytype, an energetic band of high defect density forms, which is at a fixed energetic distance from the valence band. This band has an energetically comparatively sharply defined lower edge, which is approximately 2.9 eV above the valence band edge. Because the energetic situation of the valence band in silicon carbide is independent of the polytype, the selection of the polytype according to the invention ensures that the defect band is energetically within the conduction band and thus has a significantly lower influence on the conductivity than is the case with the polytypes with a higher bandgap commonly used.

Bei erfmdungsgemaßer Auswahl des α-Siliciumcarbid-Polytyps ergeben sich vorteilhafte Halbleiterstrukturen mit den im Oberbegriff genannten Merkmalen, die gegenüber dem Stand der Technik verbesserte Eigenschaften aufweisen. Insbesondere kann der Durchlaßwiderstand vorteilhaft, z.B. um den Faktor 20, reduziert werden.When the α-silicon carbide polytype is selected in accordance with the invention, advantageous semiconductor structures are obtained with the features mentioned in the preamble, which have improved properties compared to the prior art. In particular, the on-resistance can be advantageous, e.g. can be reduced by a factor of 20.

Vorteilhafte Ausgestaltungen der erfmdungsgemaßen Halblei- tertruktur gehen aus den abhangigen Patentansprüchen hervor. Als besonders vorteilhaft sind die nachfolgend angesprochenen Ausfuhrungsformen anzusehen.Advantageous configurations of the semiconductor structure according to the invention emerge from the dependent patent claims. The embodiments discussed below are particularly advantageous.

Bei der Halbleiterstruktur besitzt der α-Siliciumcarbidhalb- leiterbereich einen um mindestens 5 meV kleineren Bandabstand als der 6H-Sιlιcιumcarbιd-Polytyp . Besonders vorteilhaft sind d e rhomboedπschen α-Siliciumcarbid-Polytypen (R-Typ) , insbesondere der 15R-Typ oder der 21R-Typ. 15R-Sιlιcιumcarbιd besitzt bei Raumtemperatur einen Bandabstand von 2,79 eV, der somit unter dem erfmdungsgemaßen Vergleichswert von 6H-S1I1- ciumcarbid (2,91 eV) liegt. Die erfmdungsgemäß ausgeschlossenen 4H- bzw. 6H-Sιlιcιumcarbιd-Polytypen sind aufgrund ihrer hohen Bandabstande von 3,15 eV (4H-Sιlιcιumcarbιd) und von 2,91 eV ( 6H-Sιlιcιumcarbιd) keine geeigneten Polytypen, trotzdem sie bislang im Bereich der Siliciumcarbidleistungs- elektronik aus Gründen der kommerziellen Verfügbarkeit praktisch ausschließlich eingesetzt worden sind. Vorteilhafte Ladungstragerbeweglichkeiten senkrecht zur kristallographi- sehen c-Achse im Bereich der Grenzfläche (Kanalzone) der erfindungsgemäßen Halbleiterstruktur ergeben sich somit für den 15R-Siliciumcarbid-Polytyp (> 40 crnXX"1) , wohingegen die entsprechenden Werte für 4H-Siliciumcarbid (< 1 cm2V_1s-1) und für 6H-Siliciumcarbid (> 20 cm2V_1s_1) deutlich niedriger liegen. Bislang wurde die Ladungsträgerbeweglichkeit in der sich anschließenden Driftzone durch das Substratvolumen parallel zur kristallographischen c-Achse, die mit 800 cm2V-1s~" bei 4H-Siliciumcarbid im Vergleich zu 330 cm2V_1s_1 bei 15R- Siliciumcarbid günstiger liegt, als maßgeblich für denIn the semiconductor structure, the α-silicon carbide semiconductor region has a band gap which is at least 5 meV smaller than the 6H-silicon carbide polytype. The rhomboedπ α-silicon carbide polytypes (R type) are particularly advantageous, in particular the 15R type or the 21R type. 15R-silicon carbide has a band gap of 2.79 eV at room temperature, which is therefore below the comparison value of 6H-S1I1-cium carbide (2.91 eV) according to the invention. The 4H or 6H silicon carbide polytypes excluded according to the invention are not suitable polytypes due to their high bandgap of 3.15 eV (4H silicon carbide) and 2.91 eV (6H silicon carbide), although they have so far been used in the area of silicon carbide performance electronics have been used almost exclusively for reasons of commercial availability. Advantageous charge carrier mobility perpendicular to the crystallographic The c-axis in the area of the interface (channel zone) of the semiconductor structure according to the invention thus results for the 15R silicon carbide polytype (> 40 crnXX "1 ), whereas the corresponding values for 4H silicon carbide (<1 cm 2 V _1 s -1 ) and for 6H silicon carbide (> 20 cm 2 V _1 s _1 ) are significantly lower. So far the charge carrier mobility in the subsequent drift zone has been parallel to the crystallographic c-axis due to the substrate volume, which with 800 cm 2 V -1 s ~ " with 4H silicon carbide compared to 330 cm 2 V _1 s _1 with 15R silicon carbide is more favorable than is decisive for the

Durchlaßwiderstand erachtet. Trotzdem ergibt sich jedoch aufgrund der beschriebenen Grenztlächeneinflüsse auf die Ladungsträgerbeweglichkeit in der Kanalzone für 4H-Silicium- carbid ein um den Faktor 20 höherer Durchlaßwiderstand als für 15R-Siliciumcarbid.ON resistance considered. Nonetheless, due to the boundary surface influences described on the charge carrier mobility in the channel zone, the forward resistance for 4H silicon carbide is 20 times higher than for 15R silicon carbide.

Eine weitere vorteilhafte Ausführungsform nutzt die Tatsache aus, daß zur Erzielung der vorteilhaften Leitfähigkeit an der Grenzfläche nur ein schmaler Halbleiterbereich in unmittel- barer Nachbarschaft zum elektrisch isolierenden Bereich aus dem beanspruchten α-Siliciumcarbid-Polytyp ausgebildet sein muß. Halbleiterbereiche, die sich im Anschluß an diesen schmalen Bereich befinden, können somit entweder aus dem gleichen oder zumindest teilweise aus einem anderen Silicium- carbid-Polytyp oder auch aus einem anderen Halbleitermaterial als Siliciumcarbid oder aus einem komplexen Aufbau mit mindestens einem anderen Halbleitermaterial als Siliciumcarbid bestehen.Another advantageous embodiment takes advantage of the fact that in order to achieve the advantageous conductivity at the interface, only a narrow semiconductor region in the immediate vicinity of the electrically insulating region has to be formed from the claimed α-silicon carbide polytype. Semiconductor regions which are adjacent to this narrow region can thus consist either of the same or at least partially of a different silicon carbide polytype or also of a different semiconductor material than silicon carbide or of a complex structure with at least one semiconductor material other than silicon carbide .

Die erfindungsgemäße Halbleiterstruktur kann in einer weiteren vorteilhaften Ausführungsform als eine MOSFET-Struktur, insbesondere als D-MOSFET-Struktur oder als U-MOSFET-Struk- tur, oder als IGBT-Struktur ausgebildet sein. Derartige Strukturen werden häufig in der Leistungselektronik eingesetzt.In a further advantageous embodiment, the semiconductor structure according to the invention can be designed as a MOSFET structure, in particular as a D-MOSFET structure or as a U-MOSFET structure, or as an IGBT structure. Such Structures are often used in power electronics.

Besonders vorteilhaft ist es außerdem, wenn man die erfin- dungsgemäße Halbleiterstruktur zum Aufbau eines Halbleiterbauelementes oder einer komplexen Halbleiterschaltung verwendet .It is also particularly advantageous if the semiconductor structure according to the invention is used to construct a semiconductor component or a complex semiconductor circuit.

Ein Ausführungsbeispiel der Erfindung wird nachfolgend anhand der Zeichnung erläutert, deren einzige Figur einen D-MOSFET schematisch darstellt.An embodiment of the invention is explained below with reference to the drawing, the only figure of which schematically represents a D-MOSFET.

D-MOSFET-Bauelemente, wie die in der Figur angedeutete und mit HS bezeichnete Halbleiterstruktur, sind wichtige uni- polare Leistungsbauelemente. Bei solchen Bauelementen wird zum einen der Strom mittels eines lateralen Stromflusses IL gesteuert und zum anderen in der sich aus einer Silicium- carbidhalbleiterschicht 3 und einem Siliciumcarbidsubstrat 2 zusammensetzenden Driftzone mittels eines vertikalen Stro - flusses I durch das Bauelement geführt.D-MOSFET components, such as the semiconductor structure indicated in the figure and designated HS, are important unipolar power components. In the case of such components, on the one hand the current is controlled by means of a lateral current flow I L and on the other hand in the drift zone composed of a silicon carbide semiconductor layer 3 and a silicon carbide substrate 2 it is guided through the component by means of a vertical current flow I.

Unter vertikalem Stromfluß ist in diesem Zusammenhang ein Stromfluß in eine Richtung , die senkrecht zu einer Grenzfläche 20 der Siliciumcarbidhalbleiterschicht 3 verläuft, zu verstehen. Entsprechend ist unter lateral eine Richtung zu verstehen, die parallel zu einer Richtung innerhalb dieser Grenzfläche 20 verläuft.In this context, vertical current flow is understood to mean a current flow in a direction that is perpendicular to an interface 20 of the silicon carbide semiconductor layer 3. Accordingly, lateral is understood to mean a direction that runs parallel to a direction within this interface 20.

Eine der bestimmenden Größen für den Durchlaßwiderstand des D-MOSFET-Bauelementes ist die Leitfähigkeit im Bereich der lateralen Stromführung IL, dem sogenannten Kanal. Diese Kanäle bilden sich im eingeschalteten Zustand aufgrund induzierter Ladungen als zu Grenzflächen 20 benachbarte Bereiche größerer Basisgebiete 11 aus. Die entscheidenden Grenzflächen 20 sind in der Figur durch eine stärkere Strichführung her- vorgehoben. Die Halbleiterstruktur befindet sich genau in diesen Bereichen des D-MOSFET-Bauelementes . Mindestens dieser grenzflächennahe Bereich des Basisgebietes 11, der an den durch eine erste Oxidschicht 13a ausgebildeten elektrisch isolierenden Bereich angrenzt, besteht aus einem α-Silicium- carbid-Polytyp mit einem kleineren Bandabstand als der von 6H-Siliciumcarbid. Z.B. ist ein 15R-Siliciumcarbid-Polytyp geeignet. Damit ist zu gewährleisten, daß sich die gewünschte vorteilhaft hohe Kanalleitfähigkeit und als Folge davon der niedrige Durchlaßwiderstand der Struktur einstellt. Der über dem Basisgebiet 11 angeordnete elektrisch isolierende Bereich kann wie in dem dargestellten Ausführungsbeispiel der Figur nur aus einer einzigen Schicht aufgebaut sein. Gemäß anderer vorteilhafter Ausführungsformen können jedoch für diesen Bereich auch mehrere Schichten, vorzugsweise auch aus verschiedenen Materialien, vorgesehen werden. Die in der Figur dargestellte erste Oxidschicht 13a, das sogenannte Gateoxid, kann vorteilhaft aus Si02-Material, insbesondere thermischem Si02-Material, bestehen. Diese Schicht kann aber auch in an- deren Ausführungsformen aus einem nichtoxidischen elektrisch isolierenden Material, insbesondere aus SiN4, bestehen.One of the determining variables for the forward resistance of the D-MOSFET component is the conductivity in the area of the lateral current conduction I L , the so-called channel. In the switched-on state, these channels are formed as regions of larger base regions 11 adjacent to interfaces 20 due to induced charges. The decisive interfaces 20 are shown in the figure by a stronger line. highlighted. The semiconductor structure is located precisely in these areas of the D-MOSFET component. At least this region of the base region 11 near the interface, which adjoins the electrically insulating region formed by a first oxide layer 13a, consists of an α-silicon carbide polytype with a smaller band gap than that of 6H silicon carbide. For example, a 15R silicon carbide poly type is suitable. This ensures that the desired advantageously high channel conductivity and, as a result, the low on-state resistance of the structure is established. The electrically insulating region arranged above the base region 11 can, as in the exemplary embodiment shown in the figure, be constructed from only a single layer. According to other advantageous embodiments, however, several layers, preferably also made of different materials, can be provided for this area. The first oxide layer 13a shown in the figure, the so-called gate oxide, can advantageously consist of SiO 2 material, in particular thermal SiO 2 material. In other embodiments, however, this layer can also consist of a non-oxide, electrically insulating material, in particular of SiN 4 .

Im folgenden wird die Funktionsweise des D-MOSFET-Bauelementes von Figur 1 näher erläutert. Es sind Sourcegebiete mit 10, Basisgebiete mit 11, Basiskontaktgebiete mit 12, eine erste Oxidschicht mit 13a, eine zweite Oxidschicht mit 13b, eine Gateelektrode mit 14, eine Sourceelektrode mit 15 und eine Drainelektrode mit 16 bezeichnet. Die zweite Oxidschicht 13b (Isolieroxid) dient zur Isolation zwischen Gateelektrode 14 und Sourceelektrode 15 und besteht aus einem mittels eines LPCVD-Verfahrens (Low Pressure Chemical Vapor Deposition) abgeschiedenen Si02. Jedes Basisgebiet 11 ist als 15R-Silicium- carbidhalbleitergebiet in eine epitaktisch auf einem Sili- ciumcarbidsubstrat 2 aufgewachsene Siliciumcarbidschicht 3 implantiert und ist entgegengesetzt dotiert zur Silicium- carbidschicht 3. Die zwischen den Basisgebieten 11 und der Siliciumcarbidschicht 3 jeweils gebildeten pn-Ubergange 17 nehmen im Sperrfall des D-MOSFET-Bauelementes im wesentlichen die Sperrspannung auf. In jedes Basisgebiet 11 ist wenigstens em Sourcegebiet 10 implantiert, das entgegengesetzt zum Basisgebiet 11 dotiert ist und deshalb mit dem zugehörigen Basisgebiet 11 jeweils einen pn-Ubergang 18 bildet. Jedes Sourcegebiet 10 ist m t dem zugehörigen Basisgebiet 11 über die Sourceelektrode elektrisch kurzgeschlossen. Die Basis- gebiete 11 sind vorzugsweise mit Bor dotiert und folglich p-leitend. Sie können überdies für eine höhere Latch-up- Festigkeit unterhalb des Sourcegebietes 10 und im Basis- kontaktgebiet 12 an der Sourceelektrode 15 durch zusatz liehe Implantation von Aluminium starker dotiert und somit p+-leιtend sein. Die Sourcegebiete 10 und die Siliciumcarbidschicht 3 sind vorzugsweise mit Stickstoff dotiert und somit n-leitend. Die Drainelektrode 16 ist an der von der Siliciumcarbidschicht 3 abgewandten Seite des Siliciumcarbidsubstrats 2 angeordnet. Insbesondere kann dem Sil ciumcarbidsubstrat 2 noch e implantiertes hoher dotiertes Dramgebiet vorgesehen sein. Der D-MOSFET hat somit einen vertikalen Aufbau.The mode of operation of the D-MOSFET component of FIG. 1 is explained in more detail below. Source regions are denoted by 10, base regions by 11, base contact regions by 12, a first oxide layer by 13a, a second oxide layer by 13b, a gate electrode by 14, a source electrode by 15 and a drain electrode by 16. The second oxide layer 13b (insulating oxide) serves for insulation between the gate electrode 14 and the source electrode 15 and consists of an SiO 2 deposited by means of an LPCVD process (Low Pressure Chemical Vapor Deposition). Each base region 11 is implanted as a 15R silicon carbide semiconductor region in a silicon carbide layer 3 grown epitaxially on a silicon carbide substrate 2 and is doped in the opposite way to the silicon carbide layer 3. The pn junctions 17 each formed between the base regions 11 and the silicon carbide layer 3 essentially absorb the reverse voltage when the D-MOSFET component is blocked. At least one source region 10 is implanted in each base region 11, which is doped opposite to the base region 11 and therefore forms a pn junction 18 with the associated base region 11. Each source region 10 is electrically short-circuited with the associated base region 11 via the source electrode. The base regions 11 are preferably doped with boron and consequently p-type. In addition, for a higher latch-up strength below the source region 10 and in the base contact region 12 at the source electrode 15 by additional implantation of aluminum, they can be more heavily doped and thus p + -leιtend. The source regions 10 and the silicon carbide layer 3 are preferably doped with nitrogen and thus n-type. The drain electrode 16 is arranged on the side of the silicon carbide substrate 2 facing away from the silicon carbide layer 3. In particular, the silicon carbide substrate 2 can also be provided with an implanted, highly doped dramatic region. The D-MOSFET thus has a vertical structure.

Wenn das Siliciumcarbidsubstrat 2 m der dargestellten Ausfuhrungsform vom gleichen Leitungstyp wie die aufgewachsene Siliciumcarbidschicht 3 ist, so liegt eine MOSFET-Struktur vor. Ist das Siliciumcarbidsubstrat 2 dagegen vom entgegengesetzten Leitungstyp wie die Siliciumcarbidschicht 3, so wird zwischen Schicht 3 und Substrat 2 e zusätzlicher pn- Ubergang zwischen Sourceelektrode 15 und Drainelektrode 16 geschaltet. Dann liegt eine IGBT-Struktur vor.If the silicon carbide substrate 2 m in the illustrated embodiment is of the same conductivity type as the grown silicon carbide layer 3, then there is a MOSFET structure. In contrast, if the silicon carbide substrate 2 is of the opposite conductivity type as the silicon carbide layer 3, an additional pn junction between the source electrode 15 and the drain electrode 16 is connected between the layer 3 and the substrate 2 e. Then there is an IGBT structure.

Es versteht sich, daß die Leitungstypen aller genannten Halb- leitergebiete auch jeweils vertauscht werden können. It goes without saying that the line types of all the semiconductor regions mentioned can also be interchanged in each case.

Claims

Patentansprüche claims 1. Halbleiterstruktur, die eine Grenzfläche zwischen einem Bereich aus einem vorbestimmten α-Siliciumcarbid-Polytyp und einem elektrisch isolierenden Bereich enthält, wobei die elektrische Leitfähigkeit im Siliciumcarbidbereich an der Grenzfläche durch induzierte Ladungen veränderbar ist, d a d u r c h g e k e n n z e i c h n e t , daß für den Siliciumcarbidbereich (3, 10, 11,) ein vom 4H- und 6H- ver- schiedener α-Siliciumcarbid-Polytyp vorgesehen ist, dessen Bandabstand höchstens dem des 6H-Siliciumcarbid-Polytyps entspricht .1.Semiconductor structure which contains an interface between a region composed of a predetermined α-silicon carbide polytype and an electrically insulating region, the electrical conductivity in the silicon carbide region at the interface being changeable by induced charges, characterized in that for the silicon carbide region (3, 10 , 11,) an α-silicon carbide polytype different from the 4H- and 6H- is provided, the band gap of which corresponds at most to that of the 6H-silicon carbide polytype. 2. Halbleiterstruktur nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t , daß für den α-Siliciumcarbid- bereich ein Polytyp gewählt ist, dessen Bandabstand gegenüber dem des 6H-Siliciumcarbid-Polytyps kleiner, vorzugsweise um mindestens 5 meV, ist.2. The semiconductor structure as claimed in claim 1, so that a polytype is selected for the α-silicon carbide region whose band gap is smaller than that of the 6H silicon carbide polytype, preferably by at least 5 meV. 3. Halbleiterstruktur nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t , daß der α-Siliciumcarbid- Polytyp ein R-Typ ist.3. The semiconductor structure according to claim 1, that the α-silicon carbide polytype is an R-type. 4. Halbleiterstruktur nach Anspruch 3, d a d u r c h g e k e n n z e i c h n e t , daß der R-Typ ein 15R-Typ oder ein 21R-Typ ist.4. The semiconductor structure according to claim 3, wherein the R type is a 15R type or a 21R type. 5. Halbleiterstruktur nach einem der vorangehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t , daß der elek- trisch isolierende Bereich durch mehrere Schichten, vorzugsweise aus verschiedenen Materialien, gebildet ist.5. The semiconductor structure as claimed in one of the preceding claims, that the electrical insulating region is formed by a plurality of layers, preferably made of different materials. 6. Halbleiterstruktur nach einem der vorangehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t , daß für den elektrisch isolierenden Bereich (13a) ein oxidisches Material vorgesehen ist.6. Semiconductor structure according to one of the preceding claims, characterized in that for the an oxidic material is provided in the electrically insulating region (13a). 7. Halbleiterstruktur nach Anspruch 6, d a d u r c h g e k e n n z e i c h n e t , daß als oxidisches Material Si02 vorgesehen ist.7. Semiconductor structure according to claim 6, characterized in that Si0 2 is provided as the oxidic material. 8. Halbleiterstruktur nach Anspruch 7, d a d u r c h g e k e n n z e i c h n e t , daß als Si02-Material ein thermisches Si02 vorgesehen ist.8. Semiconductor structure according to claim 7, characterized in that a thermal Si0 2 is provided as Si0 2 material. 9. Halbleiterstruktur nach einem der vorangehenden Ansprüche, g e k e n n z e i c h n e t durch einen Aufbau mit dem gleichen α-Siliciumcarbid-Polytyp .9. Semiconductor structure according to one of the preceding claims, g e k e n n z e i c h n e t by a structure with the same α-silicon carbide polytype. 10. Halbleiterstruktur nach einem der Ansprüche 1 bis 8, g e k e n n z e i c h n e t durch einen Aufbau mit zumindest einem α-Siliciumcarbid-Polytyp .10. Semiconductor structure according to one of claims 1 to 8, g e k e n n z e i c h n e t by a structure with at least one α-silicon carbide polytype. 11. Halbleiterstruktur nach einem der vorangehenden Ansprüche, g e k e n n z e i c h n e t durch eine Ausbildung als eine MOSFET-Struktur oder als eine IGBT-Struktur .11. Semiconductor structure according to one of the preceding claims, g e k e n n z e i c h n e t by training as a MOSFET structure or as an IGBT structure. 12. Halbleiterstruktur nach Anspruch 11, d a d u r c h g e k e n n z e i c h n e t , daß die MOSFET-Struktur als D- oder U-MOSFET-Struktur ausgebildet ist.12. The semiconductor structure as claimed in claim 11, so that the MOSFET structure is designed as a D- or U-MOSFET structure. 13. Verwendung der Halbleiterstruktur nach einem der vorangehenden Ansprüche zum Aufbau eines Halbleiterbauelements oder einer Halbleiterschaltung. 13. Use of the semiconductor structure according to one of the preceding claims for the construction of a semiconductor component or a semiconductor circuit.
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CN1267397A (en) 2000-09-20
US6316791B1 (en) 2001-11-13

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