EP0976122B1 - Matrix display addressing device - Google Patents
Matrix display addressing device Download PDFInfo
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- EP0976122B1 EP0976122B1 EP96942417A EP96942417A EP0976122B1 EP 0976122 B1 EP0976122 B1 EP 0976122B1 EP 96942417 A EP96942417 A EP 96942417A EP 96942417 A EP96942417 A EP 96942417A EP 0976122 B1 EP0976122 B1 EP 0976122B1
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- 101100294408 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) MOT2 gene Proteins 0.000 description 3
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Images
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2003—Display of colours
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0439—Pixel structures
- G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0202—Addressing of scan or signal lines
- G09G2310/0205—Simultaneous scanning of several lines in flat panels
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/393—Arrangements for updating the contents of the bit-mapped memory
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/399—Control of the bit-mapped memory using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
Definitions
- the present invention relates to a device for addressing a matrix screen such as a screen of the LCD or plasma type.
- the display surfaces of such screens generally comprise a plurality of sub-pixels P (i, j) representing one of the primary colors R, G or B and addressed through a crossed network of N horizontal lines and M vertical columns. , each sub-pixel receiving through a switch which connects it to the adjacent column, during the addressing phase (line time), a sampled video signal.
- the spatial resolution of such screens depends on the number and mode of combinations of addressable sub-pixels used to make displayable pixels whose successive sequences constitute the lines and video columns of the image to be displayed.
- the figure 1 illustrates a known mode of subpixel combination, called L mode, used to address an orthogonal screen and consisting of making a displayable pixel by combining three subpixels R, V and B on the same line.
- L mode a known mode of subpixel combination
- the horizontal resolution, denoted Hr is equal to M / 3
- Hv the vertical resolution
- this Combination mode requires a high number of subpixels which significantly increases the cost of the screen.
- the Figures 2 and 3 respectively illustrate a first variant and a second variant of a second known mode of subpixel combination, called Delta mode, used to address a DELTA type screen.
- Delta mode a second known mode of subpixel combination
- a displayable pixel is obtained by combining three sub-pixels R, V and B located on the same horizontal line.
- R, V and B located on the same horizontal line.
- two successive lines are offset horizontally with respect to each other by half a sub-pixel
- two sucessive lines are horizontally offset from each other by one subpixel and a half.
- a column of displayable pixels has a width equal to three and a half times the width of a subpixel while in the second case, a column of displayable pixels has a width equal to four times and half that of a sub-pixel.
- the horizontal resolution is reduced by three and a half times the vertical resolution
- the horizontal resolution is reduced by four and a half times the vertical resolution.
- the object of the invention is to provide a device for addressing a matrix screen to improve the horizontal resolution without degrading the vertical resolution.
- the device comprises a storage stage 70 and 198 receiving, via a demultiplexing stage 220, a plurality of digital data sequences representing the luminance video signals previously digitized and delivering said luminance video signals to a multiplexing stage 230 for selecting a sequence digital data corresponding to a given combination of sub-pixels of the image to be displayed using, according to said given combination, the digital data previously stored in said storage stage 70 and 198.
- the device according to the invention allows to select a combination of sub-pixels to obtain a better compromise between the vertical resolution and the horizontal resolution regardless of the type of screen used.
- the figure 10 schematically illustrates a device for addressing a matrix screen whose surface comprises a plurality of sub-pixels R, V and B each receiving a luminance video signal. These pixels are distributed over the surface of the screen in a network of N physical lines and M physical columns at the intersections of which are arranged switches such as TFT (Thin Film Transistors in English) in the case of LCD screens. These switches make it possible to connect, during the addressing phase, the pixels addressed to the physical columns.
- TFT Thin Film Transistors in English
- the addressing device comprises a storage stage 70 and 198 receiving, via a demultiplexing stage 220, a plurality of digital data sequences representing the luminance video signals previously digitized and delivering said luminance video signals to a multiplexing stage 230 for selecting a sequence of digital data corresponding to a given combination of subpixels among the plurality of digital data sequences previously stored in said storage stage 70 and 198.
- the storage stage 70 comprises a first memory 80 dedicated to the storage of the digital data resulting from the sampling of the signals sent to the sub-pixels R, a second memory 82 dedicated to the storage of the digital data resulting from the sampling of the signals sent to the sub-pixels V and a third memory 84 dedicated to storing the digital data resulting from the sampling of the signals sent to the sub-pixels B.
- the storage stage 70 is connected, on the one hand, to a writing control means 72, digital data in the memories 80, 82 and 84 and, on the other hand, to a reading control means 74 of said data from the memories 80, 82 and 84, said write control means 72 and read 74 are connected to a first synchronization means 76 write phases and p reading hashes.
- each of the memories 80, 82 and 84 comprises two distinct zones, ie a first zone 102 in which the digital data relating to the subpixels R, G and B of a given video line are written during a phase. given writing, and a second zone 104 from which are read, during said write phase, the digital data relating to the sub-pixels R, G and B of a video line written during the previous write phase.
- the storage stage 198 comprises two parallel branches, ie a first branch in which is arranged a block 200 comprising at least three FIFO cells, or a first stack 202, a second stack 204 and a third stack 206 for respectively holding the video data relating to the sub-pixels R, G and B located on one of the physical lines constituting an even video line, and a second branch in which is arranged a block 210 also comprising at least three FIFO cells, namely a fourth stack 212, a fifth stack 214 and a sixth stack 216 intended respectively to hold the video data relating to the sub-pixels R, V and B located on one of the physical lines constituting an odd video line.
- a first branch in which is arranged a block 200 comprising at least three FIFO cells, or a first stack 202, a second stack 204 and a third stack 206 for respectively holding the video data relating to the sub-pixels R, G and B located on one of the physical lines constituting an even video line
- the demultiplexing stage 220 on the one hand, the data relating to the sub-pixels R, V and B belonging to the odd video columns to the block 200 so as to write said data, during a phase for writing a video line of duration D, respectively in the first stack 202, the second stack 204 and the third stack 206, and on the other hand, the data relating to the sub-pixels R, V and B belonging to the columns video pairs to the block 210, so as to write said data, during the write phase, respectively in the fourth stack 212, the fifth stack 214 and the sixth stack 21 6.
- a second synchronization means 240 is connected, on the one hand, to the demultiplexing stage 220 and delivers to this stage 220 a first periodic signal OW of frequency F controlling the writing of the relative video data.
- a first periodic signal OW of frequency F controlling the writing of the relative video data.
- sub-pixels R, V and B located on a odd video column respectively in the first stack 202, in the second stack 204 and in the third stack 206
- a second periodic signal EW of frequency F controlling the writing of the video data relating to the sub-pixels R, G and B located on a video column pair respectively in the fourth stack 212, in the fifth stack 214 and in the sixth stack 216.
- This second synchronization means 240 is connected on the other hand, to the multiplexing stage 230, and delivers to this stage 230 a third periodic signal RD of frequency 2 * F controlling the reading of the video data relating to the sub-pixels of an even (odd) video line selected by the multiplexing stage 230.
- the multiplexing stage 230 selects at a frequency 1 / D, starting from a date coinciding with half the duration D, a sequence of data representing the sub-pixels belonging to a video line to be displayed previously stored in the memory. one of the cells 202, 204, 206, 212, 214 or 216.
- the figure 12 illustrates an exemplary addressing of a Delta type screen, partially shown, by means of a device according to the invention.
- Each pixel is constituted by the combination of three sub-pixels Rk, Vk and Bk.
- the signals SIG1, SIG2, SIG3 represent the samples of the luminance signals sent respectively to the subpixels Rk, Vk and Rk, situated on the same video column.
- the sub-pixels of the physical line Li respectively receive three sequences SIG1, SIG2, SIG3 respectively comprising the samples R1, R3, R5, ..., V1, V3, V5, ..., and B2, B4, B6, ...
- the sub-pixels of the physical line Li + 1 respectively receive three sequences SIG1, SIG2, SIG3 respectively comprising the samples R2, R4, R6, ..., V2, V4, V6, ..., and B3, B5, B7.
- the figure 14 illustrates the phase during which the writing of the data relating to the sub-pixels R, V and B of a video line LV is performed, and secondly, the reading of the data relating to the sub-pixels. pixels R, V and B of the previous video line LV-1, then the next phase, during which is performed, on the one hand, the writing of the data relating to the sub-pixels R, G and B of a line LV + 1 video, and secondly, reading the data relating to the sub-pixels R, G and B of the video line LV written during the previous phase.
- the writing of said video line LV and the reading of said video line LV-1 are done simultaneously and are synchronized by the first synchronization means 76 which sends to the write control means 72 and the means 74, a signal W / R, shown in FIG. figure 14 , allowing, on the one hand, to progressively write the video data relating to the sub-pixels R, G or B, and on the other hand, to read said data corresponding to the respective spatial positions of each of the sub-pixels R , V and B on the screen.
- the write phase of the LV line is illustrated by the lines RSTW, WAB, WDA, and W / R while the reading phase of the line LV-1 is illustrated by the lines RSTR, RVAB, RVRDA, BDA, BRDA .
- the line RSTW represents an initialization signal of the write phase
- the line WAB represents the successive addresses in the memories 80, 82, 84 in which the digital data representing the samples Rk, Vk and Bk will be stored successively.
- the line WDA represents said digital data transported respectively by data buses 86, 88, 90.
- the line W / R represents the synchronization signal of the successive write and read phases sent by the first synchronization means 76.
- RSTR represents a signal initialization of the reading phase.
- the line RVAB represents the successive addresses in the memories 80, 82 and 84 in which are already stored the digital data representing the samples Rk, Vk.
- the line RVRDA represents the data Rk, Vk read respectively on data buses 94 and 96.
- the line BAB represents the successive addresses in the memories 80, 82 and 84 in which are already stored the digital data representing the samples Bk, the line BRDA the Bk data read on bus 92.
- the data Rk, Vk and Bk represented on the line WDA are written progressively, while the data RVRDA and BRDA, previously written, are read correlatively to their respective positions on the surface of the screen.
- the figure 1 5 partially illustrates a stack 202 and a stack 210 and the figure 16 illustrates the phase during which, on the one hand, the writing of the data relating to the subpixels R, G and B of a video line LV, and on the other hand, the phase during which the reading data relating to the sub-pixels R, G and B of said video line LV previously written in the cells 202 and 210, then the phase, during which is performed, on the one hand, the writing of the data relating to the sub -pixels R, V and B of the video line LV + 1, and secondly, the phase during which the data relating to the sub-pixels R, G and B of said video line LV + 1 are read, previously written in the cells 202 and 210.
- the synchronization of said write and read phases is performed by means of a second synchronization means 240 providing, on the one hand, to the demultiplexing stage 220 a first signal OW period of frequency F controlling the writing of the video data relating to the sub-pixels R, V and B situated on an odd video column respectively in the cells 202, 204 and 206, and a second periodic signal EW of frequency F controlling the writing of the video data relating to the subpixels R, G and B located on a video column pair respectively in the piles 212, 214 and 216, and on the other hand, at the multiplexing stage 230 a third periodic signal RD of frequency 2 * F controlling the reading of the video data relating to the sub-pixels of an even (odd) video column selected by the multiplexing stage 230.
- a third periodic signal RD of frequency 2 * F controlling the reading of the video data relating to the sub-pixels of an even (odd) video column selected by the multiplexing stage 230.
- the line IE represents an initialization signal of the write phase
- the line OW represents the control signal of the writing of the video data relating to the subpixels R, G and B located on an odd video column
- the EW line represents the control signal of the writing of the video data relating to the subpixels R, G and B located on an even video column
- the line WDA represents the digital data to be written in the cells 202 and 210
- the line IL represents an initialization signal of the read phase
- the line RDA represents the data read
- the line OEE represents a selection signal of the data relating to the subpixels R, V and B located on an odd video column
- the line EOE represents a signal for selecting the data relating to the subpixels R, V and B situated on an even video column.
- the writing in the stack 202 of the video data relating to the sub-pixels R, G and B located on an odd video column is synchronized on each rising edge of the signal OW.
- the writing, in the stack 210, of the video data relating to the subpixels R, V and B situated on an even video column is synchronized on each rising edge of the signal EW.
- the RD signal for reading the digital data has a frequency twice that of the OW and EW signals.
- the read phases start when the batteries 202 and 212 are half full. So in the example of the figure 16 , the odd data are read at each rising edge of the signal RD from a time coinciding with the writing, of the 321 nth data, located in this example at half of the stack 202, and when the OEE signal has a logic level High.
- the even data are read at each rising edge of the signal RD at a time coinciding with the writing, in the stack 212, of the 321 nd data when the signal EOE has a high logic level.
- the Figures 4 to 9 illustrate a combination of sub-pixels in which two physical lines Li and Li + 1 are used to form a video line of the image to be displayed, and said image is decomposed into an odd field 9, 11, 13, 15, 17, 19 and 20 comprising odd video lines 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47 and 49, and an even frame 40, 42, 44, 46, 48, 50 and 52 comprising paired video lines 54, 56, 58, 60, 62, 64, 65, 66, 67 and 68, said odd and even fields being shifted, relative to one another, physical line, so as to allow interleaving of the odd video lines with the even video lines.
- the physical lines Li used to constitute the video lines 54, 56, 58, 64, 65 and 67 are also used to constitute the physical lines Li + 1 of the odd video lines 21, 25, 29, 35, 39 and 43 respectively. This allows interleaving of said even video lines and said odd video lines.
- the multiplexing stage 220 selects the digital signal sequences relating to two contiguous sub-pixels located on the physical line Li (respectively Li + 1) and to a sub-pixel located on the physical line Li + 1 (respectively Li) , then the digital signal sequences relating to a sub-pixel located on the line Li (respectively Li + 1) and two sub-pixels located on the line Li + 1 (respectively Li) to address pixel of a video line of the image to display.
- the multiplexing stage 220 selects the digital signal sequences relating to a first sub-pixel located on the physical line Li and the digital signal sequences relating to a second sub-pixel adjacent to the first sub-pixel, and located on the physical line Li + 1 to address a pixel of the video line 43 and 45 (respectively 67).
- This combination mode is particularly suitable for uses that do not require a good colorimetry but rather require a good fineness of detail, insofar as on the one hand, it makes it possible to triple the horizontal resolution with respect to the modes of combination of the prior art described above, and secondly, it causes spectrum folds known as English colored aliasing producing an iridescence of the details of the displayed image.
- the sampling of the video signals sent to the combined sub-pixels is carried out either simultaneously or in spatial mode, that is to say at different times corresponding to the respective positions of said sub-pixels on the surface of the screen.
- the resolution is improved, regardless of the type of screen addressed.
- the resolution is equal to M * 2/3 and therefore twice the resolution obtained by the addressing modes of these screens by devices of the prior art and the vertical resolution is equal to at N / 2 for strictly vertical lines and at N for diagonal lines.
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- General Physics & Mathematics (AREA)
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Description
La présente invention concerne un dispositif d'adressage d'un écran matriciel tel qu'un écran du type LCD ou à plasma.The present invention relates to a device for addressing a matrix screen such as a screen of the LCD or plasma type.
Les surfaces d'affichage de tels écrans comportent généralement une pluralité de sous-pixels P(i,j) représentant l'une des couleurs primaires R, V ou B et adressés à travers un réseau croisé de N lignes horizontales et de M colonnes verticales, chaque sous-pixel recevant à travers un interrupteur qui le relie à la colonne adjacente, pendant la phase d'adressage (temps ligne), un signal vidéo échantillonné.The display surfaces of such screens generally comprise a plurality of sub-pixels P (i, j) representing one of the primary colors R, G or B and addressed through a crossed network of N horizontal lines and M vertical columns. , each sub-pixel receiving through a switch which connects it to the adjacent column, during the addressing phase (line time), a sampled video signal.
La résolution spatiale de tels écrans dépend du nombre et du mode de combinaisons de sous-pixels adressables utilisées pour réaliser des pixels affichables dont les séquences successives constituent les lignes et les colonnes vidéo de l'image à afficher.The spatial resolution of such screens depends on the number and mode of combinations of addressable sub-pixels used to make displayable pixels whose successive sequences constitute the lines and video columns of the image to be displayed.
La
Par ailleurs, dans la mesure où les écrans matriciels ne peuvent être adressés qu'en mode progressif, le mode de combinaison décrit à la
Les
Il est aussi décrit dans le brevet
Le but de l'invention est de réaliser un dispositif d'adressage d'un écran matriciel permettant d'améliorer la résolution horizontale sans trop dégrader la résolution verticale.The
It is also described in the patent
The object of the invention is to provide a device for addressing a matrix screen to improve the horizontal resolution without degrading the vertical resolution.
Le dispositif selon l'invention comporte un étage mémorisation 70 et 198 recevant, via un étage de démultiplexage 220, une pluralité de séquences de données numériques représentant les signaux vidéo de luminance préalablement numérisés et délivrant lesdits signaux vidéo de luminance à un étage de multiplexage 230 destiné à sélectionner une séquence de données numériques correspondant à une combinaison donnée de sous-pixels de l'image à afficher en utilisant, en fonction de ladite combinaison donnée, les données numériques préalablement stockées dans ledit étage de mémorisation 70 et 198.The device according to the invention comprises a
Ainsi, le dispositif selon l'invention, permet de sélectionner une combinaison de sous-pixels permettant d'obtenir un meilleur compromis entre la résolution verticale et la résolution horizontale quel que soit le type d'écran utilisé.Thus, the device according to the invention allows to select a combination of sub-pixels to obtain a better compromise between the vertical resolution and the horizontal resolution regardless of the type of screen used.
D'autres caractéristiques et avantages de l'invention ressortiront de la description qui va suivre, prise à titre d'exemple non limitatif, en référence aux figures annexées dans lesquelles :
- la
figure 1 illustre partiellement un premier mode de combinaison des sous-pixels R, V et B d'un écran matriciel du type orthogonal, utilisé dans l'art antérieur ; - les
figures 2 illustrent une application du mode de combinaison de sous-pixels de laet 3figure 1 à un écran du type Delta ; - la
figure 4 illustre partiellement un premier mode de combinaison des sous-pixels R, V et B d'un écran matriciel réalisé par un dispositif d'adressage conforme à l'invention appliqué à un écran du type orthogonal ; - la
figure 5 illustre partiellement une première variante du mode de combinaison des sous-pixels R, V et B illustré à lafigure 4 ; - la
figure 6 illustre une deuxième variante du mode de combinaison des sous-pixels R, V et B illustré à lafigure 4 ; - les
figures 7a et7b illustrent partiellement une troisième et une quatrième variante du mode de combinaison des sous-pixels R, V et B illustré à lafigure 4 appliqué à un écran matriciel du type Delta ; - la
figure 8 illustre partiellement un deuxième mode de combinaison des sous-pixels R, V et B réalisé par un dispositif d'adressage conforme à l'invention appliqué à un écran matriciel du type orthogonal ; - la
figure 9 illustre partiellement une cinquième variante du mode de combinaison des sous-pixels R, V et B illustré à lafigure 4 appliqué à un écran matriciel du type Delta ; - la
figure 10 représente partiellement un premier mode de réalisation d'un dispositif d'adressage conforme à l'invention ; - la
figure 11 représente partiellement un deuxième mode de réalisation d'un dispositif d'adressage conforme à l'invention ; - les
figures 12 à 14 représentent des schémas explicatifs du fonctionnement du dispositif d'adressage de lafigure 10 ; - les
figures 15 et16 représentent des schémas explicatifs du fonctionnement du dispositif d'adressage de lafigure 11 .
- the
figure 1 partially illustrates a first mode of combining the R, G and B sub-pixels of an orthogonal type matrix screen used in the prior art; - the
Figures 2 and 3 illustrate an application of the subpixel combination mode of thefigure 1 a Delta type screen; - the
figure 4 partially illustrates a first combination mode of the sub-pixels R, G and B of a matrix screen produced by an addressing device according to the invention applied to a screen of the orthogonal type; - the
figure 5 partially illustrates a first variant of the combination mode of the sub-pixels R, V and B illustrated in FIG.figure 4 ; - the
figure 6 illustrates a second variant of the combination mode of the sub-pixels R, V and B illustrated in FIG.figure 4 ; - the
figures 7a and7b partially illustrate a third and a fourth variant of the combination mode of sub-pixels R, V and B shown infigure 4 applied to a matrix screen of the Delta type; - the
figure 8 partially illustrates a second combination mode of the subpixels R, V and B made by an addressing device according to the invention applied to an orthogonal type matrix screen; - the
figure 9 partially illustrates a fifth variant of the combination mode of the sub-pixels R, V and B illustrated in FIG.figure 4 applied to a matrix screen of the Delta type; - the
figure 10 partially represents a first embodiment of an addressing device according to the invention; - the
figure 11 partially represents a second embodiment of an addressing device according to the invention; - the
Figures 12 to 14 represent diagrams explaining the operation of the addressing device of thefigure 10 ; - the
figures 15 and16 represent diagrams explaining the operation of the addressing device of thefigure 11 .
La
Selon l'invention, le dispositif d'adressage comporte un étage de mémorisation 70 et 198 recevant, via un étage de démultiplexage 220, une pluralité de séquences de données numériques représentant les signaux vidéo de luminance préalablement numérisés et délivrant lesdits signaux vidéo de luminance à un étage de multiplexage 230 destiné à sélectionner une séquence de données numériques correspondant à une combinaison donnée de sous-pixels parmi la pluralité de séquences de données numériques préalablement stockées dans ledit étage de mémorisation 70 et 198.According to the invention, the addressing device comprises a
Selon un premier mode de réalisation du dispositif d'adressage conforme à l'invention, l'étage de mémorisation 70 comporte une première mémoire 80 dédiée au stockage des données numériques résultant de l'échantillonnage des signaux envoyés aux sous-pixels R, une deuxième mémoire 82 dédiée au stockage des données numériques résultant de l'échantillonnage des signaux envoyés aux sous-pixels V et une troisième mémoire 84 dédiée au stockage des données numériques résultant de l'échantillonnage des signaux envoyés aux sous-pixels B. Dans ce mode de réalisation, l'étage de mémorisation 70 est relié, d'une part, à un moyen de commande d'écriture 72 des données numériques dans les mémoires 80, 82 et 84 et, d'autre part, à un moyen de commande de lecture 74 desdites données à partir des mémoires 80, 82 et 84, lesdits moyen de commande d'écriture 72 et de lecture 74 sont reliés à un premier moyen de synchronisation 76 des phases d'écriture et des phases de lecture.
Selon ce mode de réalisation chacune des mémoires 80, 82 et 84 comporte deux zones distinctes, soit une première zone 102 dans laquelle sont écrites les données numériques relatives aux sous-pixels R, V et B d'une ligne vidéo donnée pendant une phase d'écriture donnée, et une deuxième zone 104 à partir de laquelle sont lues, pendant ladite phase d'écriture, les données numériques relatives aux sous-pixels R, V et B d'une ligne vidéo écrite pendant la phase d'écriture précédente.According to a first embodiment of the addressing device according to the invention, the
According to this embodiment, each of the
Selon un deuxième mode de réalisation du dispositif d'adressage conforme à l'invention, l'étage de mémorisation 198 comporte deux branches parallèles, soit une première branche dans laquelle est agencé un bloc 200 comportant au moins trois piles FIFO, soit une première pile du 202, une deuxième pile 204 et une troisième pile 206 destinées respectivement à contenir les données vidéo relatives aux sous-pixels R, V et B situés sur l'une des lignes physiques constituant une ligne vidéo paire, et une deuxième branche dans laquelle est agencé un bloc 210 comportant également au moins trois piles FIFO, soit une quatrième pile 212, une cinquième pile 214 et une sixième pile 216 destinées respectivement à contenir les données vidéo relatives aux sous-pixels R, V et B situés sur l'une des lignes physiques constituant une ligne vidéo impaire.According to a second embodiment of the addressing device according to the invention, the
Dans ce mode de réalisation, l'étage de démultiplexage 220 aiguille, d'une part, les données relatives aux sous-pixels R, V et B appartenant aux colonnes vidéo impaires vers le bloc 200 de manière à écrire lesdites données, pendant une phase d'écriture d'une ligne vidéo de durée D, respectivement dans la première pile 202, la deuxième pile 204 et la troisième pile 206, et d'autre part, les données relatives aux sous-pixels R, V et B appartenant aux colonnes vidéo paires vers le bloc 210, de manière à écrire lesdites données, pendant la phase d'écriture, respectivement dans la quatrième pile 212, la cinquième pile 214 et la sixième pile 21 6.In this embodiment, the
Selon ce deuxième mode de réalisation, un deuxième moyen de synchronisation 240 est relié, d'une part, à l'étage de démultiplexage 220 et délivre à cet étage 220 un premier signal périodique OW de fréquence F commandant l'écriture des données vidéo relatives aux sous-pixels R, V et B situés sur une colonne vidéo impaire respectivement dans la première pile 202, dans la deuxième pile 204 et dans la troisième pile 206, et un deuxième signal périodique EW de fréquence F commandant l'écriture des données vidéo relatives aux sous-pixels R, V et B situés sur une colonne vidéo paire respectivement dans la quatrième pile 212, dans la cinquième pile 214 et dans la sixième pile 216. Ce deuxième moyen de synchronisation 240 est relié d'autre part, à l'étage de multiplexage 230, et délivre à cet étage 230 un troisième signal périodique RD de fréquence 2*F commandant la lecture des données vidéo relatives aux sous-pixels d'une ligne vidéo paire (respectivement impaire) sélectionnée par l'étage de multiplexage 230.According to this second embodiment, a second synchronization means 240 is connected, on the one hand, to the
L'étage de multiplexage 230 sélectionne à une fréquence 1/D, à partir d'une date coïncidant avec à la moitié de la durée D, une séquence de données représentant les sous-pixels appartenant à une ligne vidéo à afficher préalablement stockées dans l'une des piles 202, 204, 206, 212, 214 ou 216.The
La
La
Comme cela a été expliqué précédemment l'écriture de ladite ligne vidéo LV et la lecture de ladite ligne vidéo LV-1 se font simultanément et sont synchronisées par le premier moyen de synchronisation 76 qui envoie au moyen de commande d'écriture 72 et au moyen de commande de lecture 74 un signal W/R, représenté à la
La phase d'écriture de la ligne LV est illustrée par les lignes RSTW, WAB, WDA, et W/R tandis que la phase de lecture de la ligne LV-1 est illustrée par les lignes RSTR, RVAB, RVRDA, BDA, BRDA.The write phase of the LV line is illustrated by the lines RSTW, WAB, WDA, and W / R while the reading phase of the line LV-1 is illustrated by the lines RSTR, RVAB, RVRDA, BDA, BRDA .
La ligne RSTW représente un signal d'initialisation de la phase d'écriture, la ligne WAB représente les adresses successives dans les mémoires 80, 82, 84 dans lesquelles vont être stockées successivement les données numériques représentant les échantillons Rk, Vk et Bk. La ligne WDA représente lesdites données numériques transportées respectivement par des bus de données 86, 88, 90. La ligne W/R représente le signal de synchronisation des phases d'écriture et de lecture successives envoyé par le premier moyen de synchronisation 76. La ligne RSTR représente un signal d'initialisation de la phase de lecture. La ligne RVAB représente les adresses successives dans les mémoires 80, 82 et 84 dans lesquelles sont déjà stockées les données numériques représentant les échantillons Rk, Vk. La ligne RVRDA représente les données Rk, Vk lues respectivement sur des bus de données 94 et 96. La ligne BAB représente les adresses successives dans les mémoires 80, 82 et 84 dans lesquelles sont déjà stockées les données numériques représentant les échantillons Bk, la ligne BRDA les données Bk lues sur le bus 92.The line RSTW represents an initialization signal of the write phase, the line WAB represents the successive addresses in the
Les données Rk, Vk et Bk représentées sur la ligne WDA sont écrites progressivement, tandis que les données RVRDA et BRDA, préalablement écrites, sont lues corrélativement à leurs positions respectives sur la surface de l'écran.The data Rk, Vk and Bk represented on the line WDA are written progressively, while the data RVRDA and BRDA, previously written, are read correlatively to their respective positions on the surface of the screen.
La
Sur la
Les
The
Comme on peut le voir sur chacune des
Selon un premier exemple d'application du dispositif d'adressage conforme à l'invention illustré par les
Selon un deuxième exemple d'application du dispositif d'adressage conforme à l'invention illustré par la
Ce mode de combinaison est particulièrement adapté à des utilisations ne nécessitant pas une bonne colorimétrie mais requérant plutôt une bonne finesse de détail, dans la mesure où d'une part, il permet de tripler la résolution horizontale par rapport aux modes de combinaison de l'art antérieur décrit précédemment, et d'autre part, il provoque des repliements de spectre connus sous le terme anglais aliasing coloré produisant une irisation des détails de l'image affichée.This combination mode is particularly suitable for uses that do not require a good colorimetry but rather require a good fineness of detail, insofar as on the one hand, it makes it possible to triple the horizontal resolution with respect to the modes of combination of the prior art described above, and secondly, it causes spectrum folds known as English colored aliasing producing an iridescence of the details of the displayed image.
L'échantillonnage des signaux vidéo envoyés aux sous-pixels combinés est réalisé, soit simultanément, soit en mode spatial, c'est-à-dire à des instants différents correspondant aux positions respectives desdits sous-pixels sur la surface de l'écran.The sampling of the video signals sent to the combined sub-pixels is carried out either simultaneously or in spatial mode, that is to say at different times corresponding to the respective positions of said sub-pixels on the surface of the screen.
Ainsi, en désignant par i et par j les positions relatives des sous-pixels respectivement sur les lignes et sur les colonnes physiques de l'écran matriciel, pour j variant périodiquement de 1 à M, et pour deux lignes physiques Li et Li + 1 données situées sur la trame impaire 19, dans un premier exemple d'adressage, on échantillonne :
- les signaux vidéo envoyés aux sous-pixels p(i,j) et p(i + 1, j) représentant respectivement les couleurs primaires R et V pour constituer les premiers pixels affichables de la ligne vidéo impaire 43
et 45, puis les signaux vidéo envoyés aux sous-pixels p(i,j + 1) et p(i + 1,j + 1) représentant respectivement les couleurs primaires V et B pour constituer les deuxièmes pixels affichables desdites lignes vidéo impaires 43et 45, et pour deux lignes physiques Li et Li + 1 données située sur la trame paire 50, on échantillonne :- les signaux vidéo envoyés aux sous-pixels p(i,j) et p(i + 1 ,j) représentant respectivement les couleurs primaires V et R pour constituer le premier pixel affichable de la ligne vidéo paire 67, puis les signaux vidéo envoyés aux sous-pixels p(i, j + 1) et p(i + 1 ,j + 1) représentant respectivement les couleurs primaires B et V pour constituer le deuxième pixel affichable de ladite ligne vidéo paire 67.
- the video signals sent to the subpixels p (i, j) and p (i + 1, j) respectively representing the primary colors R and V to constitute the first displayable pixels of the
43 and 45, and then the video signals sent to the subpixels p (i, j + 1) and p (i + 1, j + 1) respectively representing the primary colors V and B to form the second displayable pixels of the saidodd video line 43 and 45, and for two lines physical Li and Li + 1 data located on theodd video lines even frame 50, is sampled:- the video signals sent to the sub-pixels p (i, j) and p (i + 1, j) respectively representing the primary colors V and R to constitute the first displayable pixel of the
video line pair 67, and then the video signals sent to the subpixels p (i, j + 1) and p (i + 1, j + 1) respectively representing the primary colors B and V to constitute the second displayable pixel of said evenvideo line 67.
- the video signals sent to the sub-pixels p (i, j) and p (i + 1, j) respectively representing the primary colors V and R to constitute the first displayable pixel of the
Dans un deuxième exemple d'adressage, appliqué à un écran du type orthogonal, illustré par la
- les signaux vidéo envoyés aux sous-pixels p(i,j), p(i, j + 1) et p(i + 1, j) représentant respectivement les couleurs primaires R, V et B pour constituer le premier pixel affichable de la ligne vidéo impaire 21
et 23, puis les signaux vidéo envoyés aux sous-pixels p(i,j + 2), p(i + 1,j + 1) et p(i + 1,j + 2) représentant respectivement les couleurs primaires B, R et V pour constituer le pixel suivant de ladite ligne vidéo impaire 21et 23, et pour deux lignes physiques Li et Li + 1 données situées sur la trame paire 40, on échantillonne :- les signaux vidéo envoyés aux sous-pixels p(i,j), p(i + 1, j) et p(i + 1 ,j + 1) représentant respectivement les couleurs primaires B, R et V pour constituer le premier pixel affichable de la ligne vidéo paire 54, puis les signaux vidéo envoyés aux sous-pixels p(i,j + 1), p(i,j + 2) et p(i + 1,j + 2) représentant respectivement les couleurs primaires R, V et B pour constituer le pixel suivant de ladite ligne vidéo paire 54.
- the video signals sent to the sub-pixels p (i, j), p (i, j + 1) and p (i + 1, j) respectively representing the primary colors R, V and B to constitute the first displayable pixel of the
21 and 23, then the video signals sent to the sub-pixels p (i, j + 2), p (i + 1, j + 1) and p (i + 1, j + 2) respectively representing the colors B, R and V primary to constitute the next pixel of saidodd video line 21 and 23, and for two physical lines Li and Li + 1 data located on theodd video line even frame 40, is sampled:- the video signals sent to the sub-pixels p (i, j), p (i + 1, j) and p (i + 1, j + 1) respectively representing the primary colors B, R and V to constitute the first displayable pixel of the
video line pair 54, then the video signals sent to the sub-pixels p (i, j + 1), p (i, j + 2) and p (i + 1, j + 2) respectively representing the primary colors R , V and B to constitute the next pixel of said pairedvideo line 54.
- the video signals sent to the sub-pixels p (i, j), p (i + 1, j) and p (i + 1, j + 1) respectively representing the primary colors B, R and V to constitute the first displayable pixel of the
Dans un troisième exemple d'adressage, appliqué à un écran du type orthogonal, illustré par la
- les signaux vidéo envoyés aux sous-pixels p(i,j + 1), p(i + 1 ,j) et p(i+1 ,j+1) représentant respectivement les couleurs primaires V, B et R pour constituer le premier pixel affichable de la ligne vidéo impaire 25
et 27, puis les signaux vidéo envoyés aux sous-pixels p(i,j+2), p(i,j + 3) et p(i + 1, j + 2) représentant respectivement les couleurs primaires B, R et V pour constituer le pixel suivant de ladite ligne vidéo impaire 25et 27, et pour deux lignes physiques Li et Li + 1 données situées sur la trame paire 42, on échantillonne :- les signaux vidéo envoyés aux sous-pixels p(i,j), p(i, j + 1) et p(i + 1 ,j + 1) représentant respectivement les couleurs primaires B, R et V pour constituer le premier pixel affichable de la ligne vidéo paire 56, puis les signaux vidéo envoyés aux sous-pixels p(i,j + 2), p(i + 1 ,j + 2) et p(i +1 ,j+3) représentant respectivement les couleurs primaires V, B et R pour constituer le pixel suivant de ladite ligne vidéo paire 56.
- the video signals sent to the sub-pixels p (i, j + 1), p (i + 1, j) and p (i + 1, j + 1) respectively representing the primary colors V, B and R to constitute the first display pixel of the
25 and 27, then the video signals sent to the sub-pixels p (i, j + 2), p (i, j + 3) and p (i + 1, j + 2) representing respectively the primary colors B, R and V to constitute the next pixel of saidodd video line 25 and 27, and for two physical lines Li and Li + 1 data located on theodd video line even frame 42, the following samples are sampled:- the video signals sent to the sub-pixels p (i, j), p (i, j + 1) and p (i + 1, j + 1) respectively representing the primary colors B, R and V to constitute the first displayable pixel of the
video line pair 56, then the video signals sent to the sub-pixels p (i, j + 2), p (i + 1, j + 2) and p (i +1, j + 3) respectively representing the colors primary V, B and R to constitute the next pixel of said evenvideo line 56.
- the video signals sent to the sub-pixels p (i, j), p (i, j + 1) and p (i + 1, j + 1) respectively representing the primary colors B, R and V to constitute the first displayable pixel of the
Dans un cinquième exemple d'adressage, appliqué à un écran du type orthogonal, illustré par la
- les signaux vidéo envoyés aux sous-pixels p(i,j), p(i + 1, j) et p(i + 1 ,j + 1) représentant respectivement les couleurs primaires R, V et B pour constituer le premier pixel affichable de la ligne vidéo impaire 29, puis les signaux vidéo envoyés aux sous-pixels p(i,j + 1), p(i,j + 2) et p(i + 1,j + 2) représentant respectivement les couleurs primaires V, B et R pour constituer le deuxième pixel de ladite ligne vidéo impaire 29, puis les signaux vidéo envoyés aux sous-pixels p(i,j), p(i + 1,j) et p(i + 1,j + 1) représentant respectivement les couleurs primaires B, R et V pour constituer le premier pixel de la ligne vidéo impaire suivante 31, puis les signaux vidéo envoyés aux sous-pixels p(i,j + 1), p(i,j + 2) et p(i + 1 ,j + 2) représentant respectivement les couleurs primaires R, V et B pour constituer le deuxième pixel affichable de la ligne vidéo impaire 31, puis les signaux vidéo envoyés aux sous-pixels p(i,j), p(i + 1 ,j) et p(i + 1,j + 1) représentant respectivement les couleurs primaires V, B et R pour constituer le premier pixel de ladite ligne vidéo impaire 33, puis les signaux vidéo envoyés aux sous-pixels p(i,j + 1), p(1,j + 2) et p(i + 1 ,j + 2) représentant respectivement les couleurs primaires B, R et V pour constituer le deuxième pixel de ladite ligne vidéo impaire 33, et pour six lignes physiques Li et Li + 1, Li + 2, Li + 3, Li + 4, Li + 5 données situées sur la trame paire 44, on échantillonne :
- les signaux vidéo envoyés aux sous-pixels p(i,j), p(i + 1 ,j) et p(i + 1, j + 1) représentant respectivement les couleurs primaires V, B et R pour constituer le premier pixel affichable de la ligne vidéo paire 58, puis les signaux vidéo envoyés aux sous-pixels p(i, j + 1), p(i, j + 2) et p(i + 1 ,j + 2) représentant respectivement les couleurs primaires B, R et V pour constituer le deuxième pixel de ladite ligne vidéo paire 58, puis les signaux vidéo envoyés aux sous-pixels p(i,j), p(i + 1,j) et p(i + 1,j + 1) représentant respectivement les couleurs primaires R, V et B pour constituer le premier pixel de la ligne vidéo paire suivante 60, puis les signaux vidéo envoyés aux sous-pixels p(i,j + 1), p(i,j + 2) et p(i + 1,j + 2) représentant respectivement les couleurs primaires V, B et R pour constituer le deuxième pixel affichable de la ligne vidéo paire 60, puis les signaux vidéo envoyés aux sous-pixels p(i,j), p(i + 1,j) et p(i + 1,j + 1) représentant respectivement les couleurs primaires B, R et V pour constituer le premier pixel de ladite ligne vidéo paire 62, puis les signaux vidéo envoyés aux sous-pixels p(i,j + 1), p(i,j + 2) et p(i + 1,j + 2) représentant respectivement les couleurs primaires R, V et B pour constituer le deuxième pixel de ladite ligne vidéo paire 62.
- the video signals sent to the sub-pixels p (i, j), p (i + 1, j) and p (i + 1, j + 1) respectively representing the primary colors R, V and B to constitute the first displayable pixel of the odd video line 29, then the video signals sent to the sub-pixels p (i, j + 1), p (i, j + 2) and p (i + 1, j + 2) respectively representing the primary colors V , B and R to constitute the second pixel of said odd video line 29, then the video signals sent to the sub-pixels p (i, j), p (i + 1, j) and p (i + 1, j + 1 ) respectively representing the primary colors B, R and V to constitute the first pixel of the next odd video line 31, then the video signals sent to the sub-pixels p (i, j + 1), p (i, j + 2) and p (i + 1, j + 2) respectively representing the primary colors R, V and B to constitute the second displayable pixel of the odd video line 31, then the video signals sent to the sub-pixels p (i, j), p (i + 1, j) and p (i + 1, j + 1) respectively representing the primary colors V, B and R to constitute the first pixel of said odd video line 33, then the video signals sent to the sub-pixels p (i, j + 1), p (1, j + 2) ) and p (i + 1, j + 2) respectively representing the primary colors B, R and V to constitute the second pixel of said odd video line 33, and for six physical lines Li and Li + 1, Li + 2, Li + 3, Li + 4, Li + 5 data located on the even frame 44, we sample:
- the video signals sent to the sub-pixels p (i, j), p (i + 1, j) and p (i + 1, j + 1) respectively representing the primary colors V, B and R to constitute the first displayable pixel of the video line pair 58, then the video signals sent to the sub-pixels p (i, j + 1), p (i, j + 2) and p (i + 1, j + 2) respectively representing the primary colors B , R and V to constitute the second pixel of said paired video line 58, then the video signals sent to the sub-pixels p (i, j), p (i + 1, j) and p (i + 1, j + 1 ) respectively representing the primary colors R, V and B to form the first pixel of the next pair of video lines 60, and then the video signals sent to the sub-pixels p (i, j + 1), p (i, j + 2) and p (i + 1, j + 2) respectively representing the primary colors V, B and R to constitute the second displayable pixel of the video line 60, then the video signals sent to the sub-pixels p (i, j), p (i + 1, j) and p (i + 1, j + 1) representing respectively t the primary colors B, R and V to constitute the first pixel of said paired video line 62, then the video signals sent to the sub-pixels p (i, j + 1), p (i, j + 2) and p ( i + 1, j + 2) respectively representing the primary colors R, V and B to constitute the second pixel of said paired video line 62.
Dans un sixième exemple d'adressage, appliqué à un écran du type Delta représenté à la
- les signaux vidéo envoyés aux sous-pixels p(i,j), p(i,j + 1) et p(i + 1,j) représentant respectivement les couleurs primaires R, V et B pour constituer le premier pixel affichable la ligne vidéo impaire 35
et 37, puis les signaux vidéo envoyés aux sous-pixels p(i,j + 2), p(i+1,j+1) et p(i + 1,j + 2) représentant respectivement les couleurs primaires B, R et V pour constituer le pixel suivant de ladite ligne vidéo impaire 35et 37, et pour deux lignes physiques Li et Li + 1 situées sur la trame paire 46, on échantillonne :- les signaux vidéo envoyés aux sous-pixels p(i,j), p(i + 1 ,j) et p(i + 1 ,j + 1) représentant respectivement les couleurs primaires B, R et V pour constituer le premier pixel affichable la ligne vidéo paire 64, puis les signaux vidéo envoyés aux sous-pixels p(i,j + 1), p(i,j + 2) et p(i + 1 ,j + 2) représentant respectivement les couleurs primaires R, V et B pour constituer le pixel suivant de ladite ligne vidéo paire 64.
- the video signals sent to the subpixels p (i, j), p (i, j + 1) and p (i + 1, j) respectively representing the primary colors R, V and B to constitute the first pixel that can be displayed on the line
35 and 37, then the video signals sent to the sub-pixels p (i, j + 2), p (i + 1, j + 1) and p (i + 1, j + 2) respectively representing the primary colors B, R and V to constitute the next pixel of saidodd video 35 and 37, and for two physical lines Li and Li + 1 located on theodd video line even frame 46, we sample:- the video signals sent to the sub-pixels p (i, j), p (i + 1, j) and p (i + 1, j + 1) respectively representing the primary colors B, R and V to constitute the first displayable pixel the
video line pair 64, then the video signals sent to the sub-pixels p (i, j + 1), p (i, j + 2) and p (i + 1, j + 2) respectively representing the primary colors R, V and B to constitute the next pixel of saidvideo line pair 64.
- the video signals sent to the sub-pixels p (i, j), p (i + 1, j) and p (i + 1, j + 1) respectively representing the primary colors B, R and V to constitute the first displayable pixel the
Dans un septième exemple d'adressage, appliqué à un écran du type Delta représenté à la
- les signaux vidéo envoyés aux sous-pixels p(i,j), p(i,j + 1) et p(i + 1 ,j) représentant respectivement les couleurs primaires R, V et B pour constituer le premier pixel affichable la ligne vidéo impaire 39, puis les signaux vidéo envoyés aux sous-pixels p(i,j+2), p(i+1,j+1) et p(i+1,j+2) représentant respectivement les couleurs primaires B, R et V pour constituer le deuxième pixel affichable la ligne vidéo impaire 39, puis les signaux vidéo envoyés aux sous-pixels p(i,j + 1), p(i + 1,j) et p(i + 1,j + 1) représentant respectivement les couleurs primaires V, B et R pour constituer le premier pixel affichable la ligne vidéo impaire 41, puis les signaux vidéo envoyés aux sous-pixels p(i,j + 2), p(i,j + 3) et p(i + 1,j + 2) représentant respectivement les couleurs primaires B, R et V pour constituer le deuxième pixel affichable la ligne vidéo impaire 41, et pour deux lignes physiques Li et Li + 1 situées sur la trame vidéo paire 48, on échantillonne :
- les signaux vidéo envoyés aux sous-pixels p(i,j), p(i + 1,j) et p(i + 1,j + 1) représentant respectivement les couleurs primaires B, R et V pour constituer le premier pixel affichable la ligne vidéo impaire 65, puis les signaux vidéo envoyés aux sous-pixels p(i,j + 1), p(i,j + 2) et p(i + i,j + 2) représentant respectivement les couleurs primaires R, V et B pour constituer le deuxième pixel affichable la ligne vidéo impaire 65, puis les signaux vidéo envoyés aux sous-pixels p(i,j), p(i,j + 1) et p(i + 1 , j + 1) représentant respectivement les couleurs primaires B, R et V pour constituer le premier pixel affichable la ligne vidéo impaire 66, puis les signaux vidéo envoyés aux sous-pixels p(i,j + 2), p(i + 1 ,j + 2) et p(i + 1 ,j + 3) représentant respectivement les couleurs primaires V, B et R pour constituer le deuxième pixel affichable de la ligne vidéo impaire 66.
- the video signals sent to the subpixels p (i, j), p (i, j + 1) and p (i + 1, j) respectively representing the primary colors R, V and B to constitute the first pixel that can be displayed on the line
odd video 39, then the video signals sent to the sub-pixels p (i, j + 2), p (i + 1, j + 1) and p (i + 1, j + 2) respectively representing the primary colors B, R and V to form the second displayable pixelodd video line 39, then the video signals sent to the sub-pixels p (i, j + 1), p (i + 1, j) and p (i + 1, j + 1) respectively representing the primary colors V, B and R to form the first displayable pixel odd video line 41, then the video signals sent to the sub-pixels p (i, j + 2), p (i, j + 3) and p (i + 1, j + 2) respectively representing the primary colors B, R and V to form the second displayable pixel odd video line 41, and for two physical lines Li and Li + 1 located on thevideo frame 48, is sampled:- the video signals sent to the sub-pixels p (i, j), p (i + 1, j) and p (i + 1, j + 1) respectively representing the primary colors B, R and V to constitute the first displayable pixel the odd video line 65, then the video signals sent to the sub-pixels p (i, j + 1), p (i, j + 2) and p (i + i, j + 2) respectively representing the primary colors R, V and B to constitute the second display pixel the odd video line 65, then the video signals sent to the sub-pixels p (i, j), p (i, j + 1) and p (i + 1, j + 1) respectively representing the primary colors B, R and V to constitute the first displayable pixel odd video line 66, then the video signals sent to sub-pixels p (i, j + 2), p (i + 1, j + 2) and p (i + 1, j + 3) respectively representing the primary colors V, B and R to constitute the second displayable pixel of the odd video line 66.
Dans un huitième exemple d'adressage, appliqué à un écran du type Delta représenté à la
- les signaux vidéo envoyés aux sous-pixels p(i,j), p(i,j + 1) et p(i + 1,j) représentant respectivement les couleurs primaires R, V et B pour constituer le premier pixel affichable la ligne vidéo impaire 47, puis les signaux vidéo envoyés aux sous-pixels p(i + 1, j + 1), p(i + 1,j + 2) et p(i + 2,j + 2) représentant respectivement les couleurs primaires R, V et B pour constituer le deuxième pixel affichable commun à la ligne vidéo impaire 47, puis les signaux vidéo envoyés aux sous-pixels p(i + 2,j), p(i + 2,j + 1) et p(i + 3,j) représentant respectivement les couleurs primaires R, V et B pour constituer le premier pixel affichable la ligne vidéo impaire 49, puis les signaux vidéo envoyés aux sous-pixels p(i + 3, j + 1), p(i + 3,j + 2) et p(i + 4, j + 2) représentant respectivement les couleurs primaires R, V et B pour constituer le deuxième pixel affichable de la lignes vidéo impaire 49, et pour trois lignes physiques Li, Li + 1 et Li + 2 situées sur la trame vidéo paire 52, on échantillonne :
- les signaux vidéo envoyés aux sous-pixels p(i,j), p(i + 1,j) et p(i + 1,j + 1) représentant respectivement les couleurs primaires B, R et V pour constituer le premier pixel affichable la ligne vidéo paire 68, puis les signaux vidéo envoyés aux sous-pixels p(i + 1, j + 2), p(i + 2, j + 1) et p(i + 2, j + 2) représentant respectivement les couleurs primaires B, R et V pour constituer le deuxième pixel affichable la ligne vidéo impaire 68.
- the video signals sent to the subpixels p (i, j), p (i, j + 1) and p (i + 1, j) respectively representing the primary colors R, V and B to constitute the first pixel that can be displayed on the line odd video 47, then the video signals sent to the sub-pixels p (i + 1, j + 1), p (i + 1, j + 2) and p (i + 2, j + 2) respectively representing the primary colors R, V and B to constitute the second displayable pixel common to the odd video line 47, then the video signals sent to the sub-pixels p (i + 2, j), p (i + 2, j + 1) and p ( i + 3, j) respectively representing the primary colors R, G and B to constitute the first displayable pixel odd video line 49, then the video signals sent to the sub-pixels p (i + 3, j + 1), p ( i + 3, j + 2) and p (i + 4, j + 2) respectively representing the primary colors R, V and B to constitute the second display pixel of the odd video lines 49, and for three physical lines Li, Li + 1 and Li + 2 located on the video frame 52, the following samples are taken:
- the video signals sent to the sub-pixels p (i, j), p (i + 1, j) and p (i + 1, j + 1) respectively representing the primary colors B, R and V to constitute the first displayable pixel the
video line pair 68, then the video signals sent to the sub-pixels p (i + 1, j + 2), p (i + 2, j + 1) and p (i + 2, j + 2) respectively representing the primary colors B, R and V to form the second displayable pixelodd video line 68.
- the video signals sent to the sub-pixels p (i, j), p (i + 1, j) and p (i + 1, j + 1) respectively representing the primary colors B, R and V to constitute the first displayable pixel the
Grâce au dispositif selon l'invention, la résolution est améliorée, quel que soit le type d'écran adressé. En particulier, pour les écrans du type Delta, la résolution est égale à M*2/3 et donc double de la résolution obtenue par les modes d'adressage de ces écrans par des dispositif de l'art antérieur et la résolution verticale est égale à N/2 pour des lignes strictement verticales et à N pour des lignes diagonales.Thanks to the device according to the invention, the resolution is improved, regardless of the type of screen addressed. In particular, for the screens of the Delta type, the resolution is equal to M * 2/3 and therefore twice the resolution obtained by the addressing modes of these screens by devices of the prior art and the vertical resolution is equal to at N / 2 for strictly vertical lines and at N for diagonal lines.
Claims (6)
- Device for addressing a matrix screen suitable for displaying images having a plurality of video rows and columns whose constituent pixels are obtained by combining a plurality of subpixels corresponding to primary colors (R, G and B), each receiving a luminance video signal and distributed in a network of N physical rows and M physical columns, the device including between a demultiplexing stage (220)and a multiplexing stage (230) at least a memory stage (70, 198), characterized in that the memory stage (70, 198) is adapted to receive, via a demultiplexing stage (220), and to store a plurality of sequences of digital data, each representing a previously digitised luminance video signal and to deliver the said luminance video signals to a multiplexing stage (230), this one being designed to select a sequence of digital data corresponding to a given combination of subpixels of the image to display, using according to the said data combination, the digital data previously stored in the said memory stage (70, 198).
- Device according to Claim 1, wherein the memory stage (198) includes two parallel branches, that is to say a first branch in which is arranged a first unit (200) having at least three FIFO cells, that is to say a first cell (202), a second cell (204) and a third cell (206) intended respectively to contain the video data relating to the subpixels corresponding to primary colors (R, G and B) situated on one of the physical rows constituting an even video row, and a second branch in which is arranged a second unit (210) also having at least three FIFO cells, that is to say a fourth cell (212), a fifth cell (214) and a sixth cell (216) intended respectively to contain the video data relating to the subpixels corresponding to primary colors (R, G and B) situated on one of the physical rows constituting an odd video row.
- Device according to Claim 1, also comprising means (72) of controlling the writing of the digital data to the memories (80, 82, 84) of the memory stage and means (74) of controlling the reading of the said data from said memories (80, 82, 83), said write control means (72) and read control means (74) are connected to a first means (76) of synchronizing the writing and reading phases.
- Device according to Claim 3, wherein each of said memories (80, 82 and 84) includes two distinct areas, that is to say a first area (102) in which there are written the digital data relating to the subpixels corresponding to the primary colors (R, G and B) of a given video row during a given writing phase, and a second area (104) from which there are read, during the said writing phase, the digital data relating to the subpixels corresponding to the primary colors (R, G and B) of a video row written during the previous writing phase.
- Device according to Claim 2, wherein the demultiplexing stage (220) is adapted to switch on the one hand the data relating to the subpixels corresponding to the primary colors (R, G and B) belonging to the odd video columns to the first unit (200) so as to write the said data, during a phase of writing a video row of duration D, respectively to the first cell (202), the second cell (204) and the third cell (206), and on the other hand the data relating to the subpixels corresponding to the primary colors (R, G and B) belonging to the even video columns to the second unit (210), so as to write the said data, during the writing phase, respectively to the fourth cell (212), the fifth cell (214) and the sixth cell (216).
- Device according to Claim 2 or to claim 5, also including a synchronization means (240) connected on the one hand to the demultiplexing stage (220) and delivering to this stage (220) a first periodic signal OW of frequency F controlling the writing of the video data relating to the subpixels corresponding to the primary colors (R, G and B) situated on an odd video column respectively to the first cell (202), the second cell (204) and the third cell (206), and a second periodic signal EW of frequency F controlling the writing of the video data relating to the subpixels corresponding to the primary colors (R, G and B) situated on an even video column respectively to the fourth cell (212), the fifth cell (214) and the sixth cell (216), this synchronization means (240) is connected moreover to the multiplexing stage (230), and delivering to this stage (230) a third periodic signal RD of frequency 2*F controlling the reading of the video data relating to the subpixels of an even (or respectively odd) video row selected by the multiplexing stage (230).
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9515405A FR2742910B1 (en) | 1995-12-22 | 1995-12-22 | METHOD AND DEVICE FOR ADDRESSING A MATRIX SCREEN |
FR9515405 | 1995-12-22 | ||
PCT/FR1996/002013 WO1997023861A1 (en) | 1995-12-22 | 1996-12-18 | Matrix display addressing device |
Publications (2)
Publication Number | Publication Date |
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EP0976122A1 EP0976122A1 (en) | 2000-02-02 |
EP0976122B1 true EP0976122B1 (en) | 2009-03-04 |
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Application Number | Title | Priority Date | Filing Date |
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EP96942417A Expired - Lifetime EP0976122B1 (en) | 1995-12-22 | 1996-12-18 | Matrix display addressing device |
Country Status (7)
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US (1) | US6252613B1 (en) |
EP (1) | EP0976122B1 (en) |
JP (1) | JP4105228B2 (en) |
KR (1) | KR100425248B1 (en) |
DE (1) | DE69637857D1 (en) |
FR (1) | FR2742910B1 (en) |
WO (1) | WO1997023861A1 (en) |
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DE19746329A1 (en) * | 1997-09-13 | 1999-03-18 | Gia Chuong Dipl Ing Phan | Display device for e.g. video |
DE19746576A1 (en) * | 1997-10-22 | 1999-04-29 | Zeiss Carl Fa | Process for image formation on a color screen and a suitable color screen |
JP4158874B2 (en) * | 2000-04-07 | 2008-10-01 | 株式会社日立プラズマパテントライセンシング | Image display method and display device |
US7027013B2 (en) | 2000-12-22 | 2006-04-11 | Ifire Technology, Inc. | Shared pixel electroluminescent display driver system |
US6720972B2 (en) | 2001-02-28 | 2004-04-13 | Honeywell International Inc. | Method and apparatus for remapping subpixels for a color display |
JP2003043990A (en) * | 2001-07-31 | 2003-02-14 | Fujitsu Ltd | Color image display method |
KR100489445B1 (en) | 2001-11-29 | 2005-05-17 | 엘지전자 주식회사 | A Driving Method Of Plasma Display Panel |
JP2005351920A (en) * | 2004-06-08 | 2005-12-22 | Semiconductor Energy Lab Co Ltd | Control circuit for display device and display device and electronic equipment containing the same and driving method for the same |
US7705821B2 (en) * | 2005-01-31 | 2010-04-27 | Semiconductor Energy Laboratory Co., Ltd. | Driving method using divided frame period |
CN101523478B (en) * | 2006-10-13 | 2011-09-21 | 夏普株式会社 | Display device, and signal converting device |
JP5441312B2 (en) * | 2007-02-09 | 2014-03-12 | 株式会社ジャパンディスプレイ | Display device |
TWI395195B (en) * | 2008-07-30 | 2013-05-01 | Orise Technology Co Ltd | Method for applying the same dithering table for different flat panels and display driving method thereof |
WO2012067038A1 (en) * | 2010-11-15 | 2012-05-24 | シャープ株式会社 | Multi-primary color display device |
CN102903318B (en) * | 2011-07-29 | 2015-07-08 | 深圳云英谷科技有限公司 | Method for arranging and displaying sub-pixels of display |
US20180168855A1 (en) * | 2016-12-15 | 2018-06-21 | Penguin Fingers, Llc | Joint compress cold pack |
WO2019042072A1 (en) * | 2017-08-31 | 2019-03-07 | 昆山国显光电有限公司 | Pixel structure, oled display device, and driving method |
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DE3634092A1 (en) * | 1986-10-07 | 1988-04-14 | Thomson Brandt Gmbh | CIRCUIT ARRANGEMENT FOR DELAYING A DIGITAL SIGNAL |
DE3761279D1 (en) * | 1987-01-08 | 1990-02-01 | Hosiden Electronics Co | FLAT DISPLAY DEVICE. |
US4792856A (en) * | 1987-04-14 | 1988-12-20 | Rca Licensing Corporation | Sampled data memory system as for a television picture magnification system |
JP2702941B2 (en) * | 1987-10-28 | 1998-01-26 | 株式会社日立製作所 | Liquid crystal display |
JPH0248863A (en) * | 1988-08-10 | 1990-02-19 | Nec Corp | Digital video signal processing circuit |
DE68923683T2 (en) * | 1988-11-05 | 1996-02-15 | Sharp Kk | Control device and method for a liquid crystal display panel. |
US5841480A (en) * | 1989-09-07 | 1998-11-24 | Advanced Television Technology Center | Film to video format converter using least significant look-up table |
EP0428324A2 (en) * | 1989-11-13 | 1991-05-22 | DELCO ELECTRONICS CORPORATION (a Delaware corp.) | Matrix addressable display and driver having CRT compatibility |
JPH06332843A (en) | 1992-06-24 | 1994-12-02 | Seiko Epson Corp | Moving image video data transfer device and computer system |
FR2703814B1 (en) * | 1993-04-08 | 1995-07-07 | Sagem | COLOR MATRIX DISPLAY. |
JP3219640B2 (en) * | 1994-06-06 | 2001-10-15 | キヤノン株式会社 | Display device |
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1995
- 1995-12-22 FR FR9515405A patent/FR2742910B1/en not_active Expired - Fee Related
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1996
- 1996-12-18 WO PCT/FR1996/002013 patent/WO1997023861A1/en active IP Right Grant
- 1996-12-18 JP JP52335497A patent/JP4105228B2/en not_active Expired - Fee Related
- 1996-12-18 KR KR10-1998-0704070A patent/KR100425248B1/en not_active IP Right Cessation
- 1996-12-18 DE DE69637857T patent/DE69637857D1/en not_active Expired - Lifetime
- 1996-12-18 EP EP96942417A patent/EP0976122B1/en not_active Expired - Lifetime
- 1996-12-18 US US09/077,379 patent/US6252613B1/en not_active Expired - Lifetime
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WO1997023861A1 (en) | 1997-07-03 |
FR2742910A1 (en) | 1997-06-27 |
KR19990071791A (en) | 1999-09-27 |
DE69637857D1 (en) | 2009-04-16 |
US6252613B1 (en) | 2001-06-26 |
JP4105228B2 (en) | 2008-06-25 |
FR2742910B1 (en) | 1998-04-17 |
JP2000502813A (en) | 2000-03-07 |
EP0976122A1 (en) | 2000-02-02 |
KR100425248B1 (en) | 2004-07-27 |
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