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EP0889531A1 - Dispositif semiconducteur controlé MOS - Google Patents

Dispositif semiconducteur controlé MOS Download PDF

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Publication number
EP0889531A1
EP0889531A1 EP98810484A EP98810484A EP0889531A1 EP 0889531 A1 EP0889531 A1 EP 0889531A1 EP 98810484 A EP98810484 A EP 98810484A EP 98810484 A EP98810484 A EP 98810484A EP 0889531 A1 EP0889531 A1 EP 0889531A1
Authority
EP
European Patent Office
Prior art keywords
collector
fingers
base layer
emitter
finger
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98810484A
Other languages
German (de)
English (en)
Inventor
Friedhelm Dr. Bauer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ABB Asea Brown Boveri Ltd
ABB AB
Original Assignee
ABB Asea Brown Boveri Ltd
Asea Brown Boveri AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ABB Asea Brown Boveri Ltd, Asea Brown Boveri AB filed Critical ABB Asea Brown Boveri Ltd
Publication of EP0889531A1 publication Critical patent/EP0889531A1/fr
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Definitions

  • the invention relates to the field of power semiconductor technology. It is based on a MOS-controlled power semiconductor component the preamble of the first claim.
  • a generic power semiconductor component is, for example, in the German published application DE 195 00 588 A1.
  • IGBT bipolar transistor with an isolated control electrode
  • the IGBT has a three-dimensional MOS structure. The dimensions the three-dimensional structure perpendicular to the axial direction about the same size. Column-shaped ones are particularly preferred Structures.
  • a MOS-controlled power semiconductor component is likewise from EP 0 494 597 B1 known with trench structure.
  • EP 0 494 597 B1 known with trench structure.
  • Such trench or trench IGBTs allow due to the plasma enrichment on the cathode side the forward voltage drop in the range of GTOs to push. Maximization would be to further reduce forward losses the total accumulation area, i.e. Trench floor and also trench wall) while minimizing the p-base area in the through the trenches formed fingers desired. This would be an optimized one Trench geometry due to deep and wide trenches as well as narrow fingers featured. However, such a geometry is extremely difficult to manufacture.
  • the object of the invention is therefore a MOS controlled power semiconductor component to be indicated by low transmission losses and a high Blocking voltage distinguishes, but still with reasonable technical Effort can be made. This task is characterized by the characteristics of independent claims solved.
  • the essence of the invention is therefore that two types of fingers are provided, namely so-called emitter fingers and collector fingers. All fingers will contacted by the cathode and driven by the same gate. But only the emitter fingers have source regions. These are missing from the collector fingers Areas.
  • the collector fingers can_but with a thin, highly doped Layer should be equipped, which has good electrical contact to the cathode enables. At least one, preferably, are between two emitter fingers at least three, cathode fingers arranged.
  • Figure 1 shows a section of an inventive, MOS-controlled Power semiconductor component in section. It is in particular a so-called trench IGBT.
  • a semiconductor body 1 In a semiconductor body 1 are between a first main surface 2 and a second main surface 3 a number of different doped semiconductor layers and regions arranged. n-doped Layers and areas are with from top left to bottom right Hatched lines, while p-doped areas with from top right to left hatched lines are hatched. The density of the hatching indicates the strength of the doping.
  • a p + doped follows from the second main area Anode emitter 4, a first, n doped base layer 5 and a second, p doped base layer 6.
  • the first main surface 2 has a cathode metallization 13, the second main surface 3 is covered with an anode metallization 14. From the first main surface 2 there are also trenches in the semiconductor body 1 embedded. The trenches are lined with an insulating film 8 and with a control or gate electrode 9, e.g. filled with polysilicon. Form the trenches Fingers 7 and 11, two types of fingers being provided according to the invention are: Emitter finger 7 and collector finger 11. The two types of fingers differ in the type of strata and areas that differ in their area are located. N + doped source regions 10 are arranged in the emitter fingers 7. The collector fingers 11 have a higher instead of the source areas with the same polarity as the second base layer 6 doped collector region 12 on. The number of cathode fingers arranged between two emitter fingers 7 11 is basically not limited. However, at least one, preferably, are preferred three cathode fingers 11 between two emitter fingers 7.
  • the cathode fingers according to the invention perform the following function: In the culvert, the component is connected to a positive gate voltage (e.g. 15V) operated. To switch off, a negative voltage (e.g. -15V) is applied to the gate created. In the pass band, the positive gate voltage causes the inversion layers (second base layer 6) and the accumulation layers (first base layer 5) a two-dimensional electron gas of high concentration trains.
  • the path resistance for the holes in the collector fingers 11 must now be so high that there is only a negligibly small hole current in the passage flows through the collector fingers 11. This can be achieved that the sheet resistance, i.e. the resistance that the holes experience in the collector fingers 11 is chosen at least ten times larger than in the Emitter fingers 7.
  • This parameter can be determined by dimensioning the cross section the collector finger 11 can be influenced. So in the culvert it will entire area occupied by the collector fingers 11 as an accumulation area used.
  • the structure according to the invention thus corresponds to the optimal one Geometry for a trench IGBT, based on that of the collector fingers provided, comparatively large accumulation area both a minimal forward voltage drop and a reduction in Saturation current density can be achieved.
  • the trench geometry of a realized exemplary embodiment is characterized by a trench depth of 3.5 ⁇ m. With a cell spacing of 2 ⁇ m and an oxide thickness of the insulation film 8 of 0.3 ⁇ m, the trenches and the fingers 7 and 11 have a width of 0.7 ⁇ m.
  • the second base layer 6 of the exemplary embodiment has a Gaussian profile with a depth of 2.5 ⁇ m and an edge concentration of 5-10 16 cm -3 .
  • the depth of the highly doped source region 10 and collector regions 12 is 0.2 ⁇ m.
  • the advantage of the structure according to the invention over a conventional one Trench IGBT without a collector finger is, in particular, that the emitter finger 7 through the presence and participation of the MOS-controlled collector fingers 11 be significantly relieved when switching off. That is even a Snubber-free operation of the MOS-controlled power semiconductor component according to the invention possible.
  • the collector fingers 11 block in the passage (positive gate voltage) as explained the hole current almost completely, so that this mainly over the emitter fingers flows. When switched off, however, the collector fingers become conductive and take over a large part of the hole stream. Because of this knowledge can the emitter fingers 7 and the collector fingers 11 with regard to further properties can be optimized by geometric measures:
  • FIGS. 2 to 4 show further variants of emitter fingers in detail.
  • FIG. 2 shows the emitter finger 7 already explained second base layer 6, two source regions 10 are provided per finger, which run along a longitudinal direction of the finger.
  • the second base layer 6 penetrates between the two source areas in the transverse direction of the fingers first main surface 2.
  • the source regions 10 are used to increase the latch-up strength interrupted along the longitudinal axis of the emitter finger 7.
  • structuring is inherent source regions extending in the transverse direction of the fingers over the entire width 10 along the finger axis is advantageous (see Figure 4).
  • FIGS. 5 to 8 Different variants of the collector fingers 11 are shown in FIGS. 5 to 8.
  • Figure 5 shows the basic variant with in a collector region 12, the is arranged above the second base layer 6 and extends in the longitudinal direction of the Collector finger 11 extends the full length of the finger.
  • Figure 6 can also interrupt the collector region 12 in the longitudinal direction of the finger be executed. This turns the strips into collector cells. This will the accumulation area increases. At the same time, however, the resistance rises the collector path because of the reduced cross-sectional area. That profit can be used to increase the critical width of the collector fingers.
  • FIG. 7 shows a corresponding embodiment in which the Collector region 12 is arranged directly after the first base layer 5 is. A further increase in the sheet resistance in the collector fingers 11 can be achieved in that between the collector areas 12 and first base layer 5 a transition zone doped higher than the first base layer 5 15 is provided.
  • Figure 8 shows the corresponding embodiment.
  • the structure according to the invention results in a MOS-controlled one Trench power semiconductor device, in which the passage losses strong can be reduced and switched on and off without any problems can.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thyristors (AREA)
EP98810484A 1997-06-30 1998-05-25 Dispositif semiconducteur controlé MOS Withdrawn EP0889531A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19727676 1997-06-30
DE1997127676 DE19727676A1 (de) 1997-06-30 1997-06-30 MOS gesteuertes Leistungshalbleiterbauelement

Publications (1)

Publication Number Publication Date
EP0889531A1 true EP0889531A1 (fr) 1999-01-07

Family

ID=7834036

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98810484A Withdrawn EP0889531A1 (fr) 1997-06-30 1998-05-25 Dispositif semiconducteur controlé MOS

Country Status (3)

Country Link
EP (1) EP0889531A1 (fr)
JP (1) JPH1168107A (fr)
DE (1) DE19727676A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001052306A2 (fr) * 2000-01-14 2001-07-19 Rockwell Science Center, Llc Transistor bipolaire a tranchee a grille isolee equipe d'une zone de fonctionnement protegee amelioree
EP1032047A3 (fr) * 1999-02-17 2001-11-28 Hitachi, Ltd. Dispositif semiconducteur et convertisseur de puissance l'utilisant
WO2006008888A1 (fr) * 2004-07-16 2006-01-26 Toyota Jidosha Kabushiki Kaisha Transistor bipolaire à grille isolée
WO2006059300A2 (fr) * 2004-12-02 2006-06-08 Koninklijke Philips Electronics N.V. Transistors a effet de champ a grille isolee
US10468511B2 (en) 2016-03-16 2019-11-05 Kabushiki Kaisha Toshiba Semiconductor device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1708276A4 (fr) * 2003-12-22 2008-04-16 Matsushita Electric Ind Co Ltd Dispositif semi-conducteur a grille verticale et procede pour fabriquer ce dispositif
CN107644903B (zh) * 2017-09-14 2020-03-17 全球能源互联网研究院 具有高抗短路能力的沟槽栅igbt器件及其制备方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991003078A1 (fr) * 1989-08-17 1991-03-07 Ixys Corporation Thyristor a grille isolee interruptible
EP0536668A2 (fr) * 1991-10-07 1993-04-14 Nippondenso Co., Ltd. Dispositif semi-conducteur vertical
DE19500588A1 (de) * 1995-01-11 1996-07-18 Abb Management Ag Bipolartransistor mit isolierter Steuerelektrode (IGBT) und dreidimensionaler MOS Struktur
EP0746030A2 (fr) * 1995-06-02 1996-12-04 SILICONIX Incorporated MOSFET de puissance à grille entenée avec diode de protection
EP0746042A2 (fr) * 1995-06-02 1996-12-04 SILICONIX Incorporated MOSFET de puissance avec tranchée bloquant bidirectionnel
US5585651A (en) * 1991-08-08 1996-12-17 Kabushiki Kaisha Toshiba Insulated-gate semiconductor device having high breakdown voltages
DE19722441A1 (de) * 1996-06-11 1997-12-18 Mitsubishi Electric Corp Halbleitervorrichtung und Verfahren zur Herstellung derselben

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69233105T2 (de) * 1991-08-08 2004-05-06 Kabushiki Kaisha Toshiba, Kawasaki Bipolartransistor mit isoliertem Graben-Gate
JP2810821B2 (ja) * 1992-03-30 1998-10-15 三菱電機株式会社 半導体装置及びその製造方法
JP3156487B2 (ja) * 1994-03-04 2001-04-16 富士電機株式会社 絶縁ゲート型バイポーラトランジスタ
US5468982A (en) * 1994-06-03 1995-11-21 Siliconix Incorporated Trenched DMOS transistor with channel block at cell trench corners
US5581100A (en) * 1994-08-30 1996-12-03 International Rectifier Corporation Trench depletion MOSFET
JP3850054B2 (ja) * 1995-07-19 2006-11-29 三菱電機株式会社 半導体装置
JP3384198B2 (ja) * 1995-07-21 2003-03-10 三菱電機株式会社 絶縁ゲート型半導体装置およびその製造方法
JP3410286B2 (ja) * 1996-04-01 2003-05-26 三菱電機株式会社 絶縁ゲート型半導体装置
JP3352592B2 (ja) * 1996-05-16 2002-12-03 三菱電機株式会社 半導体装置およびその製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991003078A1 (fr) * 1989-08-17 1991-03-07 Ixys Corporation Thyristor a grille isolee interruptible
US5585651A (en) * 1991-08-08 1996-12-17 Kabushiki Kaisha Toshiba Insulated-gate semiconductor device having high breakdown voltages
EP0536668A2 (fr) * 1991-10-07 1993-04-14 Nippondenso Co., Ltd. Dispositif semi-conducteur vertical
DE19500588A1 (de) * 1995-01-11 1996-07-18 Abb Management Ag Bipolartransistor mit isolierter Steuerelektrode (IGBT) und dreidimensionaler MOS Struktur
EP0746030A2 (fr) * 1995-06-02 1996-12-04 SILICONIX Incorporated MOSFET de puissance à grille entenée avec diode de protection
EP0746042A2 (fr) * 1995-06-02 1996-12-04 SILICONIX Incorporated MOSFET de puissance avec tranchée bloquant bidirectionnel
DE19722441A1 (de) * 1996-06-11 1997-12-18 Mitsubishi Electric Corp Halbleitervorrichtung und Verfahren zur Herstellung derselben

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1032047A3 (fr) * 1999-02-17 2001-11-28 Hitachi, Ltd. Dispositif semiconducteur et convertisseur de puissance l'utilisant
EP1811572A3 (fr) * 1999-02-17 2007-09-19 Hitachi, Ltd. Dispositif à semi-conducteur et convertisseur de puissance utilisant ce même dispositif à semi-conducteur
WO2001052306A2 (fr) * 2000-01-14 2001-07-19 Rockwell Science Center, Llc Transistor bipolaire a tranchee a grille isolee equipe d'une zone de fonctionnement protegee amelioree
WO2001052306A3 (fr) * 2000-01-14 2002-01-03 Rockwell Science Center Llc Transistor bipolaire a tranchee a grille isolee equipe d'une zone de fonctionnement protegee amelioree
WO2006008888A1 (fr) * 2004-07-16 2006-01-26 Toyota Jidosha Kabushiki Kaisha Transistor bipolaire à grille isolée
CN100449778C (zh) * 2004-07-16 2009-01-07 丰田自动车株式会社 绝缘栅双极晶体管
DE112005001621B4 (de) * 2004-07-16 2010-09-23 Toyota Jidosha Kabushiki Kaisha, Toyota-shi Isolierschicht-Bipolartransistor
US7804108B2 (en) 2004-07-16 2010-09-28 Toyota Jidosha Kabushiki Kaisha Semiconductor devices
WO2006059300A2 (fr) * 2004-12-02 2006-06-08 Koninklijke Philips Electronics N.V. Transistors a effet de champ a grille isolee
WO2006059300A3 (fr) * 2004-12-02 2008-07-03 Koninkl Philips Electronics Nv Transistors a effet de champ a grille isolee
US10468511B2 (en) 2016-03-16 2019-11-05 Kabushiki Kaisha Toshiba Semiconductor device
US10573733B2 (en) 2016-03-16 2020-02-25 Kabushiki Kaisha Toshiba Semiconductor device

Also Published As

Publication number Publication date
DE19727676A1 (de) 1999-01-07
JPH1168107A (ja) 1999-03-09

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