EP0771463B1 - Process and device for storing and rotating bit configurations - Google Patents

Description

The invention relates to a method and device for Save and rotate bit patterns. The bit patterns are in Matrix cells of a memory matrix are writable and again readable. A bit pattern represents one in its individual Pixels (image points) resolved image information. Such image information are for example in the case of screen devices and other display units and for copying and printing devices for reproducing the image information on a recording medium processed.

An electrographic printer is known from US Pat. No. 5,012,434. the image information to be printed by a data processing device receives. This coded image information is from converted into a bit pattern by a printer controller and, if necessary turned. The bit pattern is sent to a subordinate Playback device read out the bit pattern and thus transmits the image information to a recording medium.

Memory matrices are usually used to rotate bit patterns used on their matrix cells with the help of peripheral Selection elements can be accessed at will. So is it is possible, for example, whole rows or whole columns write and read in parallel from the memory matrix. For this purpose, each matrix cell has exactly one memory cell in which a pixel is in the form of a logical zero or one is discardable. Each matrix cell is via a first line with a line multiplexer and via a second line connected to a column multiplexer. The column multiplexers and line multiplexers serve as peripheral selection elements. Therefore, depending on the size of the memory matrix a large number of lines from the matrix cells to the matrix periphery needed. This makes the size a realizable one Matrix limited.

A storage unit for use is known from US-A-4 935 897 known in a printer. The storage unit can act as a buffer memory be used for image data. At every matrix point A pixel can be stored in the memory unit will. Through targeted control using a row decoder and a column decoder can read out pixels that there is an image rotation.

From US-A-4 875 190 is a two-dimensional storage unit known which contains memory modules arranged in matrix form. Each memory chip is itself a matrix organized two-dimensional memory with random Access. All memory chips are the same and are created using of a nine bit wide address bus, whereby at the same time always a specific one, in all memory modules same matrix cell can be selected.

The present invention has for its object a Device and method for storing and rotating To show bit patterns, with the matrix size remaining the same, the number of connecting lines between the Matrix cells and the matrix periphery is reduced.

This object is achieved by the in the claims 1 and 4 specified features solved. Executions and developments of the invention are specified in the subclaims.

By combining several memory cells in one Matrix cell with only one output and an internal data selection, the global wiring effort is drastically reduced. It can, given the technical possibilities larger storage matrices can be realized.

Which information is stored in which matrix cell can be optimized for quick readability. As indicated in the subclaims, row by column Readability is desired, only pixels whose information does not have to be read out simultaneously in the memory locations summarized in a matrix cell. By folding the original square matrix over at least one of their Diagonals, such pixels are found. The one after folding Pixels lying congruently one above the other can be in one Matrix cell can be summarized. With correspondingly frequent folded original matrix become pixels of a matrix position for several directions of rotation in the storage cells summarized in a matrix cell. Choosing which memory cell to connect to the data output of the matrix cell is by the internal provided in the matrix cell Selection element made. The number of necessary Control lines is compared to the number of saved connecting lines between matrix cells and Low matrix periphery.

Figur 1

eine Speichermatrix gemäß dem Stand der Technik,

Figur 2

eine schematische Darstellung einer Speichermatrix mit einer ersten Diagonale,

Figur 3

eine bereits einmal geklappte Speichermatrix mit einer weiteren Diagonale,

Figur 4

eine bereits zweimal geklappte Speichermatrix mit einer weiteren Diagonale,

Figur 5

eine einmal geklappte Speichermatrix mit Leitungsverbindungen von den Matrixzellen zu den peripheren Auswahlelementen,

Figur 6

eine zweimal geklappte Matrix mit Verbindungsleitungen von den Matrixzellen zu der Matrixperipherie,

Figur 7

eine zweimal geklappte Matrix mit Steuerleitungen zu den Auswahlelementen der Matrixzellen,

Figur 8

ein Schaltungsbeispiel einer Matrixzelle mit zwei Speicherzellen,

Figur 9

ein Schaltungsbeispiel einer Matrixzelle mit vier Speicherzellen,

Figur 10

eine Auslesesteuereinrichtung für eine Speichermatrix gemäß den Figuren 6 und 7,

Figur 11

eine Darstellung der Einzeloperationen beim Auslesen der Speichermatrix für verschiedene Drehrichtungen und

Figur 12

eine schematische Darstellung der Bildgenerierung eines Druckers.

An example of the invention is explained in more detail below with reference to the drawing. Show

Figure 1

a memory matrix according to the prior art,

Figure 2

1 shows a schematic representation of a memory matrix with a first diagonal,

Figure 3

an already folded memory matrix with another diagonal,

Figure 4

a memory matrix already folded twice with another diagonal,

Figure 5

a once folded memory matrix with line connections from the matrix cells to the peripheral selection elements,

Figure 6

a twice folded matrix with connecting lines from the matrix cells to the matrix periphery,

Figure 7

a twice folded matrix with control lines to the selection elements of the matrix cells,

Figure 8

1 shows a circuit example of a matrix cell with two memory cells,

Figure 9

1 shows a circuit example of a matrix cell with four memory cells,

Figure 10

a readout control device for a memory matrix according to FIGS. 6 and 7,

Figure 11

a representation of the individual operations when reading out the memory matrix for different directions of rotation and

Figure 12

a schematic representation of the image generation of a printer.

Figure 12 schematically shows the structure of the image generation a printer. Image information is sent from a computer HOST in coded form to a channel interface HI (host Interface). On a downstream grid module RM the coded image information is converted into a bit pattern. This raster module RM contains, among other things Storage matrix for storage and described below Rotate bit patterns. The generated in the RM module Bit pattern is sent to a playback unit WG, for example a printer (PRINTER).

Figure 1 shows an original square matrix with n = 8 Columns COL and n = 8 rows ROW. Each column is a row multiplexer Assigned to RMUX. Every line multiplexer is RMUX via second lines LT2 with data outputs from matrix cells MZ connected. Using the 8: 1 RMUX line multiplexer thus one data output each from a matrix cell MZ with the Output of the line multiplexer RMUX can be connected. In order to can use the line multiplexer RMUX one of the lines ROW (0..7) of the memory matrix can be read out.

There are also eight column multiplexers in the matrix periphery CMUX arranged. An input of a column multiplexer CMUX is each with a matrix cell MZ of a row ROW Memory matrix connected via a first line LT1. Thereby can the output of the column multiplexer CMUX with one of the Matrix cells MZ of the respective row ROW are connected. With the help of the column multiplexer CMUX is thus a column COL (0..7) of the memory matrix can be read out. With this memory matrix according to the prior art are thus twice as much many lines LT1, LT2 between the matrix cells MZ and Row or column multiplexers RMUX, CMUX required, such as Matrix cells MZ are available.

With such an original square matrix, a Rotate the bit pattern stored in the memory matrix in made in a known manner. For example, instead of a column ROW (0..7) selected a column COL (0..7) and then the bit order in the read data word is reversed.

According to the present invention, the original can now Matrix can be folded over its diagonals. An original Matrix is shown in Figure 2. In every matrix cell MZ a cell index is entered. The matrix cell MZ of the column Zero COL (0) and the row zero ROW (0) is with the index 00 designated. The other matrix cells MZ are corresponding designated. The matrix cells MZ of row two are ROW (2) each marked by a hatched circle. This The marking corresponds to a position of row 2 rotated by 0 ° ROW (2). The matrix cells MZ, in which this row ROW (2) after a rotation of a further 90 ° are in the following Marked way: A hatched rectangle corresponds to one Rotation by 90 °, a square box corresponds to one Rotation by 180 °, a circle corresponds to a rotation by 270 °. Diagonally across the storage matrix runs from the matrix cell MZ with the index 00 to the matrix cell MZ with the index 77 a first diagonal D1. About this first diagonal D1 the original matrix worked. The result of this folding process is shown in Figure 3.

In the matrix cells MZ of the memory matrix according to FIG. 3 the cell indices of the original matrix are entered. The markings row 2 ROW (2) according to FIG. 2 inclusive their rotational positions have been maintained. The matrix cells MZ along the diagonal D1 are unchanged. In the rest However, matrix cells MZ have two cell indices each. One recognizes by the markings of the different ones Direction of rotation of row 2 ROW (2) that the cell indices a column COL or a row ROW each in different Matrix cells MZ are located. Each column COL or row ROW can thus be read out in parallel. The memory matrix can now along a second diagonal D2 from the matrix cell MZ with the cell indices 34, 43 to the matrix cell MZ with the Cell indexes 07, 70 runs, be folded a second time. The result of this folding process is shown in Figure 4.

One can see that in the marginal cells that run along the two Diagonals D1, D2 are arranged, two cell indices each are registered. The remaining matrix cells contain MZ four cell indices each. The markings of the different Direction of rotation of row 2 ROW (2) according to Figure 2, were maintained. This also ensures that the cell indices a row ROW or column COL are in different matrix cells MZ are located. Columns COL or rows ROW can thus can be read out in parallel. The matrix according to FIG. 4 can be used for corresponding size along a third diagonal D3, D3 ' continue to be folded. The third diagonal D3 runs from the matrix cell MZ with the indices 12,21,56,65 to the matrix cell MZ with the cell indices 03,30,47,74 and the diagonal D3 'runs from the matrix cell MZ with the cell indices 04,40,37,73 to the matrix cell MZ with the cell indices 15.51.26.62.

The wiring of the folded memory arrays according to the Figures 3 and 4 for connecting the data outputs DOUT from Matrix cells MZ with the playback device WG is in the Figures 5 and 6 shown. The cell indices of column 2 COL (2) and row 2 ROW (2) of the original matrix each together in a matrix cell MZ. The corresponding Matrix cells MZ are hatched in FIGS. 5 and 6 shown.

In the embodiment according to FIG. 5, the matrix cells are MZ over third lines LT3 with column / row multiplexers RCMUX connected. By folding the memory matrix once the number of peripheral multiplexers RCMUX increases eight pieces halved because of outside the memory matrix no longer differentiate between columns COL and rows ROW must become. This distinction is made in the matrix cells MZ, as explained in more detail below.

The twice folded matrix according to FIG eight columns / row multiplexer RCMUX required. This However, RCMUX column / row multiplexers only show half of the inputs of the column / row multiplexer RCMUX at the once folded matrix according to Figure 5. By the second Folding process is the number of matrix cells MZ of the memory matrix so reduced that from the outside only between four rows ROW or columns COL must be distinguished. In A matrix cell MZ has up to four cell indices Matrix cells MZ of the original matrix are available. So For example, the cell indices of row 2 ROW (2) stand for hatched all directions of rotation of this row ROW (2) shown matrix cells MZ (Figure 4).

The construction of a matrix cell MZ with two memory cells SZ (two indices) is shown in Figure 8. A memory cell SZ consists of a flip-flop FF (0..1) and a load multiplexer LM (0..1). The flip-flops FF (0..1) is a clock CLK fed. The output of each flip-flop FF (0..1) is one Input of the load multiplexer LM (0..1) returned. Of the other input of the load multiplexer LM (0..1) is via a Data line D (0..1) connected to the periphery. The charging multiplexer LM (0..1) is connected by means of a charging line LD (0..1) between a charging function and a holding function from the outside switched. So should pixels in a memory cell SZ are written, then there is an LD (0..1) on the charging line to create appropriate information, which means that at the Data line D (0..1) image information present in the memory cell SZ is written. The charging lines LD (0..1) are coupled to a charging control, not shown. The outputs of the flip-flops FF (0..1) are each with an input of one serving as an internal selection element Cell multiplexer ZMUX connected. With the help of this cell multiplexer ZMUX becomes one of the outputs of the flip-flops FF (0..1) switched through to the data output DOUT of the matrix cell MZ. The selection is made with the help of a selection management SEL.

A matrix cell MZ that contains four memory cells SZ is constructed as shown in Figure 9. The structure of each Memory cells SZ of this matrix cell MZ corresponds to this described above according to Figure 8. Only the cell multiplexer ZMUX points according to the number of memory cells SZ four inputs, optionally with the data output DOUT are connectable. To select a memory cell SZ two selection lines SEL (1..0) are required. These selection lines SEL (1..0) are with a readout control device coupled according to Figure 10.

FIG. 10 shows a readout control device for reading out a twice folded matrix according to FIGS. 4, 6 and 7. The readout controller becomes a binary coded address ADDR (2..0) fed the one logical line to be read ROW indicates. The two least significant address bits ADDR (1..0) become a negating and a non-negating input an address multiplexer AMUX supplied. Which of the entrances is switched through to the output of the address multiplexer determined by the most significant address bit ADDR (2). The exit of the address multiplexer AMUX is with the control lines ADDR_L (1..0) of the row / column multiplexer RCMUX and with the Input of a decoder DEC connected. Depending on the address ADDR (2..0) thus becomes a logical line L_ROW (0..7) of the Storage matrix selected.

The inputs of two more are at the output of the decoder DEC Address multiplexer AMMUX1, AMMUX2 coupled. The least significant Image of the DEC decoder is not used. Each of these another address multiplexer AMMUX has a non-inverting and an inverting input, which is optional can be switched through to the output. The output of an address multiplexer AMMUX1 is with a first control line bundle MIR1 (3..1) coupled. The output of the second address multiplexer AMMUX2 is with a second control line bundle MIR2 (3..1) coupled. The two address multiplexers AMMUX1, AMMUX2 are dependent on the most significant address bit ADDR (2) and from one of the rotating lines RED (1..0) Rotation information switched. The most significant address bit ADDR (2) and the rotation information are passed through four EXCLUSIVE-OR gates XOR1, XOR2, XOR3, XOR4 linked together. The rotation lines RED (1..0) are at the two inputs of the first EXCLUSIVE-OR gate XOR1 and to one input each of the second EXCLUSIVE-OR gate XOR2 and the fourth EXCLUSIVE-OR gate XOR4 coupled. The exit of the first EXCLUSIVE-OR gate XOR1 is with one input of the third EXCLUSIVE-OR gate XOR3 coupled. The most valuable Address bit ADDR (2) is at one input of the second, third and fourth EXCLUSIVE-OR gate XOR2, XOR3, XOR4. The output of the second EXCLUSIVE-OR gate XOR2 switches the address multiplexer AMMUX1 and is connected to the line MIRROR1 coupled. The output of the third EXCLUSIVE-OR gate XOR3 switches over the address multiplexer AMMUX2 and is the MIRROR2 line coupled. The output of the fourth EXCLUSIVE-OR gate XOR4 is coupled to the MIRROR3 'line.

As FIG. 7 shows, the control lines MIR1, MIR2, MIRROR1, MIRROR2 with the selection lines SEL (1..0) of the Cell multiplexer ZMUX coupled. The memory matrix is in divided into two symmetrical parts. The left Half form the columns COL (0 ... 3) and the right one Half of the columns are COL (4..7). Each of the matrix cells MZ The left half of the memory matrix is the fourth Control line MIRROR2 coupled. The fourth control line MIRROR2 is included in the edge cells (two memory cells) the selection line SEL and in the core cells (four memory cells) with the selector line SEL1 of the cell multiplexer ZMUX connected. The selection lines SEL0 of the core cells of the left half of the memory matrix are column by column connected to one of the first control lines MIR1 (3..1).

The selection lines SEL of the edge cells and the selection lines SEL0 of the core cells of the right half of the memory matrix, are connected to the third control line MIRROR1. The selector lines SEL1 of the core cells of the right half of the memory matrix are in columns with one of the second control lines MIR2 (3..1) connected.

The fifth control line MIRROR3 'controls a not shown Multiplexer arrangement constructed in line width. On the inputs of the 2: 1 multiplexer arrangement are the outputs of the row / column multiplexer RCMUX connected so that the first inputs of the multiplexer arrangement with the logical Line L_ROW (0..7) are coupled in ascending order and at the second inputs of the multiplexer arrangement logical line L_ROW (7..0) coupled in reverse order are. By signal reversal on the fifth control line MIRROR3 'can therefore read the bit sequence of a logical Line L_ROW (0..7) or L_ROW (7..0) can be reversed.

Figure 11 shows a schematic representation of the rotation of a bit pattern. Are one above the other in the vertical direction four different rotational positions, namely one rotation 0 °, 90 ° rotation, 180 ° rotation and 1 rotation represented by 270 °. In the horizontal direction they are related operations are shown, starting from a rotation of 0 ° are required to get to the desired one To reach the rotational position. For a rotation of 0 ° are therefore no operations required. For a 90 ° turn is a reflection on the second diagonal D2 (MIRROR2) and then mirroring the line bisector (runs between row3 and row4) of the memory matrix (MIRROR3 ') is required. With a rotation of 180 ° there is a reflection the first and the second diagonal (MIRROR1, MIRROR2) required. A reflection is on for a rotation of 270 ° the first diagonal D1 (MIRROR1) with subsequent mirroring of the lines at the line bisector of the memory matrix (MIRROR3 ') required. The reflection on the line bisector (MIRROR3 ') corresponds to a reflection at the column bisector in the original matrix because of this reflection a reflection on the first or on the second diagonal D1, D2 precedes.

The respective operations can be carried out with the aid of the memory matrix according to the invention and its readout control device. This readout process is explained below with reference to FIGS. 4, 4a, 6, 7 and 10. The address ADDR (2..0) for the selected row 2 ROW (2) is 010. There is a rotation by 180 °. There is a logic 1 on the rotation line ROT (1) and a logic zero on the rotation line ROT (0). A logical 1 is accordingly present at the output of the first EXCLUSIVE-OR gate XOR1. There is consequently a logic 1 on the third control line MIRROR1, a logic 1 on the fourth control line MIRROR2 and a logic 0 on the fifth control line MIRROR3 '. The address multiplexer AMUX outputs the two low-order address bits ADDR (1..0) unchanged to the control line ADDR_L (1..0). The matrix cells MZ hatched in FIGS. 4, 6 and 7 are thereby selected. The decoder DEC works according to the following truth table: ADDR (1) ADDR (0) MSB LSB 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 0

The least significant bit LSB of this truth table is not required. The other three bits are negated by the address multiplexers AMMUX1, AMMUX2. Correspondingly, the following assignment applies to the logical states that are present on the first and second control lines: MIR1 (3) 1 MIR2 (3) 1 MIR1 (2) 0 MIR2 (2) 0 MIR1 (1) 1 MIR2 (1) 1

The individual memory cells SZ of the core cells according to FIG. 4 are arranged for easier understanding as shown in FIG. 4a. The most significant bit indicates the logical state on the second selection line SEL (1) and the least significant bit indicates the logical state on the first selection line SEL (0). According to the connections between the selection lines SEL (1..0) and the control lines MIR1 (3..1), MIRROR2 in the left half of the memory matrix described in the matrix cell MZ of column 2 COL (2) and row 7 or respectively . 0 ROW (7 0) following control signal:
SEL0 = 0 = MIRROR2 (2) and SEL1 = 1 = MIRROR2.

Accordingly, the memory cell SZ with the index 57 selected. The same applies to the other cells of the left half of the memory matrix.

The connections described above between the control lines MIRROR1, MIR2 (3..1) and the selection lines SEL (0), SEL (1) are implemented in the right half of the memory matrix. Accordingly, the following control signal is present, for example, in the matrix cell of column 5 COL (5) and row 6 or 1 ROW (6 1):
SEL0 = 1 = MIRROR1 and SEL1 = 0 = MIR2 (2)

Accordingly, the memory cell SZ with the index 51 selected. The same applies to the other cells of the right half of the memory matrix.

This means that RCMUX is at the output of the row / column multiplexer the content of row 5 ROW (5) rotated by 180 ° parallel to Available. In this way, all lines become 0 in succession or 7 ROW (0..7) rotated by 180 °.

With a rotation of 90 or 270 °, other logical states must be set accordingly on the rotation lines RED (1..0) according to the following table: rotation RED (1) RED (0) 0 ° 0 0 90 ° 0 1 180 ° 1 0 270 ° 1 1

These are made logical by means of the readout control device States of the rotation lines RED (1..0) implemented so that in In the case of a rotation of 90 °, a reflection on the second Diagonal D2 and, in the case of a rotation of 270 °, a reflection is carried out on the first diagonal D1. In both Cases is through the multiplexer arrangement on which means the fifth control line MIRROR3 'has a logic one, swapping the order of the read Bit information carried out.

Memory matrices of different sizes can be constructed in this way while saving a large number of lines. The table below shows the potential savings on cables, depending on the size of the matrix and the number of times the matrix is folded. Matrix size n 8th 16 32 64 Memory cells (SZ) n ^ 2 64 256 1024 4096 Output lines (LT) 2 * n ^ 2 128 512 2048 8192 Matrix cells (MZ) (n ^ 2/2) + (n / 2) 36 136 528 2080 Output lines (LT) n ^ 2 64 256 1024 4096 Control lines (MIR) n 8th 16 32 64 Matrix cells (MZ) (n ^ 2/4) + (n / 2) 20th 72 272 1056 Output lines (LT) n ^ 2/2 32 128 512 2048 Control lines (MIR) n + 1 9 17th 33 65 Output lines (LT) n ^ 2/2 ^ x Matrix cells (n ^ 2/2 ^ x) + (n / 2) Saved lines (LT) - (LT) 1) - (MIR) 1) 56 240 992 4032 Saved lines (LT) - (LT) 2) - (MIR) 2) 87 367 1503 6079

For example, in an original matrix with the Size n = 8, which was folded twice 87 output lines taking into account the additional control lines required ME saved.

Claims (8)

1. Method for storing and rotating bit patterns in a raster module (RM), which has a storage matrix that contains a plurality of matrix cells (MZ) and can be coupled to a reproduction device (WG) via peripheral selection elements (RCMUX), having the following method steps:

   storage of a bit pattern present in the form of pixels of an original matrix, in such a way that at least one pixel of the original matrix is stored in each matrix cell (MZ) of the storage matrix, and

   read-out of the bit pattern from the storage matrix, specific matrix cells (MZ) being selected as a function of a rotation information item,

   characterized in that, as a function of the rotation information item, a respective pixel within the selected matrix cells (MZ) is selected by means of an internal selection element (ZMUX) and is read out to the reproduction device (WG).
2. Method for storing and rotating bit patterns according to Claim 1, in which the pixels of the original matrix are stored in the matrix cells (MZ) of the storage matrix in such a way that each matrix cell (MZ) contains the pixels which are congruent with respect to one another after the original matrix has been folded across at least one of its diagonals (D).
3. Method for storing and rotating bit patterns according to either of Claims 1 and 2, with a raster module (RM) which is assigned to an electrographic printer, the bit pattern being stored in a row-by-row or column-by-column manner in the storage matrix of the said raster module and being read out in a row-by-row or column-by-column manner from the said raster module.
4. Raster module (RM) for storing and rotating bit patterns, which contains:

   a storage matrix that contains a plurality of matrix cells (MZ) and can be coupled to a reproduction device (WG) via peripheral selection elements (RCMUX),

   at least one storage cell (SZ) per matrix cell (MZ) for storing a bit pattern present in the form of pixels of an original matrix, in such a way that at least one pixel of the original matrix can be stored in each matrix cell (MZ) of the storage matrix, and

   internal selection elements (ZMUX) in the matrix cells (MZ) for selecting specific storage cells (SZ) within the matrix cells (MZ) and for coupling the outputs of these storage cells (SZ) to the reproduction device (WG),

   characterized by a read-out control device, which drives the selection elements (ZMUX, RCMUX) as a function of a rotation information item of the bit pattern.
5. Raster module (RM) for storing and rotating bit patterns, according to Claim 4, in which the bit patterns can be read out in a row-by-row or column-by-column manner to the reproduction device (WG), having

   matrix cells (MZ) which

   each have a data output (DOUT),

   each contain storage cells (SZ) for accommodating the pixels of an original square matrix which lie above one another when this original matrix is folded at at least one of its diagonals (D),

   each contain an internal selection element (ZMUX) for coupling its data output (DOUT) to in each case one of the storage cells (SZ) contained in it, and

   peripheral selection elements (RCMUX) for the optional coupling of the data outputs (DOUT) of matrix cells (MZ) to the reproduction device (WG).
6. Raster module (RM) for storing and rotating bit patterns, according to either of Claims 4 and 5, having an interchanging device that is arranged upstream of the reproduction device (WG) and optionally, as a function of its driving by the read-out control device, reverses the order of the pixels of a column (COL) or row (ROW) that is read out.
7. Raster module (RM) for storing and rotating bit patterns, according to one of Claims 4 to 6, having a storage matrix for storing an original matrix having n columns (COL) and n rows (ROW) which is folded x times at its diagonals (D), the storage matrix having n ² / 2 ^x + n / 2 matrix cells (MZ).
8. Electrographic printer having a raster module (RM) for storing and rotating bit patterns according to one of Claims 4 to 7.

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