EP0635819B1 - Driving method and apparatus for a microtip display - Google Patents

Description

Technical area

The present invention relates to a method and a device for control of a matrix display screen intended to display images having different gray levels, of the fluorescent microtip screen type. The images can be in black and white or in color, the expression "grayscale" meaning in the latter case "halftone of color".

State of the art

Microtip fluorescent screens are known and notably described by R. Meyer in the article entitled "Microtips Fluorescent Display "(" Japan Display "86, page 512).

We know that to control the display of images on a matrix screen we generally use a "one line at a time" addressing principle. The addressing of a microprint screen of L lines and M columns is therefore carried out line by line (line time = T _L ) during a frame of duration T _T greater than or equal to LxT _L. When addressing each line, the information to be displayed on the M pixels of this line is applied simultaneously to the M columns of the screen.

• un adressage analogique qui consiste à échantillonner, après amplification, un signal source analogique et à reporter sur la colonne considérée une tension directement proportionnelle au signal vidéo ;
• un adressage numérique en modulation temporelle dit PWM, pour "Pulse Width Modulation", qui consiste à commuter une tension dite "on" pendant une durée plus ou moins grande du temps de sélection ligne T_L, en fonction du niveau de gris à afficher, comme décrit dans la demande de brevet français FR-A-88 08756 du 29 juin 1988.

We find in an article by T. Leroux, A. Ghis, R. Meyer and D. Sarrasin entitled "Microtips Display Adressing" (SID 91 Digest, pages 437 to 439) a description of the operating principle of these screens as well as different ways to address them. We distinguish in this article two types of addressing:

• an analog addressing which consists in sampling, after amplification, an analog source signal and in transferring on the column considered a voltage directly proportional to the video signal;
• digital addressing in time modulation called PWM, for "Pulse Width Modulation", which consists in switching a voltage called "on" for a greater or lesser duration of the line selection time T _L , as a function of the gray level to be displayed, as described in French patent application FR-A-88 08756 of June 29, 1988.

• une modulation temporelle de type FRC ("Frame Rate Control"). Cette méthode est notamment décrite dans les demandes de brevets EP-0 384 403 et EP-0 364 307 pour des écrans STN (LCD multiplexés) et consiste à effectuer plusieurs balayages de l'image en affectant successivement des états "on" ou "off" aux mêmes éléments d'images, l'oeil faisant office d'intégrateur ;
• une méthode utilisant des circuits multiniveaux. Cette méthode consiste à utiliser des circuits pouvant commuter N niveaux de tension différents (en pratique, N=8 ou N=16). A chaque tension correspond un niveau de gris déterminé. Cette méthode utilise également des circuits huit niveaux, sur deux trames, ce qui permet d'obtenir, avec les mêmes tensions et des durées identiques, seize niveaux de gris comme décrit dans l'article de H. Mano, T. Furuhashi et T. Tanaka intitulé "Multicolor Display Method for TFT-LCD" (SID 91 Digest, pages 547 à 550).

There are also different variants of digital solutions:

• a time modulation of the FRC ("Frame Rate Control") type. This method is notably described in patent applications EP-0 384 403 and EP-0 364 307 for STN screens (multiplexed LCD) and consists in carrying out several scans of the image by successively assigning "on" or "off" states. "with the same image elements, the eye acting as an integrator;
• a method using multilevel circuits. This method consists in using circuits which can switch N different voltage levels (in practice, N = 8 or N = 16). Each voltage corresponds to a specific gray level. This method also uses eight-level circuits, on two frames, which makes it possible to obtain, with the same voltages and identical durations, sixteen levels of gray as described in the article by H. Mano, T. Furuhashi and T. Tanaka entitled "Multicolor Display Method for TFT-LCD" (SID 91 Digest, pages 547 to 550).

You can also use circuits on eight levels out of two successive frames, but by assigning a different weight to the frames by means of tensions. The first frame providing for example the low weights (0, 1, 2, 3, 4, 5, 6, 7) and the second the most significant (0, 8, 16, 24, 32, 40, 48, 56), which provides sixty four gray levels, as described in the article by K. Takahara, T. Yamaguchi, M. Oda, H. Yamaguchi and M. Okabe entitled "16-Level-Gray-Scale Driver Architecture and Full-Color Driving for TFT-LCD" (IDRC 91 Digest, pages 115 to 118). This method however limits the contrast of the screen.

Today, in the world of flat screens, competition is built around a few key points. One of these is a search for low consumption. However, two variants of addressing among those cited for the grayscale display, are more interesting from the point of view of the capacitive consumption specific to the screen: analog control and method using multilevel circuits (which is limited in practice to sixteen voltage levels).

The practical implementation of analog control with circuits operating in linear regime leads to a difficult compromise. In Indeed, in such an operation, if the screen consumes very little, we must by against supplying a non-negligible current to bias the output stage of the circuits. And the more we want short times to go from one level to another (corresponding to the addressing of two successive lines) the more you have to increase this current and therefore the consumption of the control electronics.

Digital type circuits are precisely of interest to have a very low own consumption since they function as as many switches, without the need for bias current and with very short response times. The method using multilevel circuits is approximates the ideal solution, but if one wishes to display Q = 256 shades of gray, obviously we cannot envisage a circuit having 256 inputs of voltage and comprising as many 256-channel analog multiplexers as there are outputs to control.

Another document of known art, the patent application EP-A-0 478 386, applies to TFT ("Thin Film Transistor") screens. In the proposed control mode, the goal is to get on the control electrode column considered, at the end of the line selection time, a column voltage determined by the data provided by the source. The state of the art being to switch a voltage chosen from N external voltages, this request proposes a means for obtaining a large number of distinct final voltages from a limited number of sources of external tension. The principle is to charge the column with the lower (or equal) but most available external voltage close to the desired final value to apply next, while the first tension is established and at a time dependent on the desired final tension (and gray level to be displayed), the external voltage available immediately superior. The transition to this tension takes place with a certain time constant related to the capacity of the column and the access resistance to this capacity, the voltage memorized on the capacity is that obtained at the end of line time (Rq: in a TFT screen, each pixel is connected to an electrode column through a transistor operating as a switch, this transistor being driven by the line electrode; at the end of line time, we open this switch where the high impedance passage on the pixel capacity and the memorization of the voltage on said capacity). By playing on the moment of the triggering of the second voltage, a whole series of voltages can be obtained at the end of the selection intermediaries.

The object of the invention is to propose a method and a device for controlling a matrix display screen of the fluorescent screen type a microtips to solve the various problems defined above.

Statement of the invention

The invention relates to a method for controlling a fluorescent microtip screen composed of pixels arranged in L lines and M columns of images capable of comprising a discrete number of Q shades of gray, said method comprising each time a line is selected of the screen during a line selection time T _L , the application simultaneously to the columns of the screen of voltages corresponding to the gray levels to be displayed at the image points corresponding to the intersection of said line and said columns, characterized in that that the different column voltage values that can be applied to the columns are chosen from a strictly increasing sequence of N + 1 values such that the line selection time is subdivided into S equal time intervals Δt, each voltage value is applied an integer of times Δt, (NxS) +1 representing the number Q of gray levels, with N≥2 and S≥2, and in that during a selection time line T _L and as a function of the gray level to be displayed at an image point, the corresponding column voltage takes a first value Va during a certain number of time intervals Δt, then if necessary during the remaining time intervals, at plus a second value Vb, this second value being consecutive to the first in the sequence of the N voltages.

In this method, an addressing mode is used which both the possibilities of time and voltage modulation offered by the response electro-optics of fluorescent microtip screens. Beyond the threshold emission, the luminance obtained is indeed proportional to (VxT), V being the applied cathode grid voltage and T the duration of the application of this voltage. Thanks to the present invention, the consumption advantages of digital circuits and analog addressing mode while allowing selection of a large number of gray levels.

• une source de données numériques fournissant des mots K codant l'information à afficher sur k bits ;
• un contrôleur d'écran recevant des signaux de synchronisation de la source de données et gérant les différents signaux propres à piloter des circuits de commande des colonnes de l'écran ;
• un générateur de (N+1) tensions discrètes ;
• les circuits de commande des colonnes de l'écran comprenant un registre à décalage de k entrées et de k x M sorties, chaque sortie étant associée à une bascule de mémorisation et des moyens de multiplexage analogique reliés d'une part aux k x M bascules et au générateur, et d'autre part aux M colonnes, ces moyens permettant de commuter sur chaque colonne une tension choisie parmi N+1 en fonction du mot K mémorisé dans les k bascules associées à ladite colonne.

The invention also relates to a device for controlling the columns of a fluorescent microtip screen enabling gray levels to be displayed, which comprises:

• a digital data source providing words K coding the information to be displayed on k bits;
• a screen controller receiving synchronization signals from the data source and managing the various signals suitable for driving circuits for controlling the columns of the screen;
• a generator of (N + 1) discrete voltages;
• the screen column control circuits comprising a shift register of k inputs and kx M outputs, each output being associated with a storage flip-flop and analog multiplexing means connected on the one hand to the kx M flip-flops and to the generator, and on the other hand to the M columns, these means making it possible to switch on each column a voltage chosen from N + 1 as a function of the word K stored in the k flip-flops associated with said column.

• un circuit décodeur binaire n bits 1 parmi 2ⁿ relié aux h bascules de ladite colonne qui ont en mémoire les h bits de poids fort, ledit circuit produisant N signaux H₀ à H_N-1 qui traduisent le codage de H et qui permettent de sélectionner le couple de tensions colonnes (V_i, V_i+1) adapté au niveau de gris à afficher;
• un comparateur relié aux (k-h) bits de poids faibles et à un séquenceur apte à fournir la séquence d'adressage à l'intérieur d'un temps ligne codé sur (k-h) bits ;
• un circuit de logique combinatoire relié aux sorties du circuit décodeur et au comparateur ;
• N+1 commutateurs analogiques dont les entrées analogiques sont reliées au générateur, les entrées de validation au circuit de logique combinatoire et dont toutes les sorties sont reliées à la colonne correspondante.

Each word K stored in the k flip-flops of a control circuit of a column being subdivided into two words H and B such that the word H consists of the h most significant bits of K with 2 ^h = N + 1 and such that the word B is made up of (kh) least significant bits remaining, the means for multiplexing the control circuit of a column include:

• a binary decoder circuit n bits 1 among 2 ⁿ connected to the h flip-flops of said column which have in memory the h most significant bits, said circuit producing N signals H ₀ to H _N-1 which translate the coding of H and which make it possible to select the pair of column voltages (V _i , V _{i + 1} ) suited to the gray level to be displayed;
• a comparator connected to the least significant bits (kh) and to a sequencer capable of supplying the addressing sequence within a line time coded on (kh) bits;
• a combinational logic circuit connected to the outputs of the decoder circuit and to the comparator;
• N + 1 analog switches whose analog inputs are connected to the generator, the validation inputs to the combinational logic circuit and all of whose outputs are connected to the corresponding column.

The sequencer provides the index P of the addressing sequence within a line time, this index P being coded on (kh) bits. This sequencer is advantageously a counter whose clock includes 2 ^(kh) pulses per line time, this counter being initialized at each line time. The comparator performs the comparison between the signals P and B and delivers a coding bit E such that: P <B ⇒ E = 1 P ≥ B ⇒ E = 0.

The combinational logic circuit between the coding bit E and the signals H ₀ to H _N-1 makes it possible to obtain the signals F ₀ to F _N which control the N + 1 analog switches, such as: F 0 = E .H 0 F 1 = EH o + E .H 1 F i = EH i-1 + E .H i F N-1 = EH N-2 + E .H N-1 F NOT = EH N-1 so as to position the change in voltage Vi to Vi + 1 over time.

The generator of N + 1 discrete voltages can be formed operational amplifiers mounted as follower amplifiers, with input voltages set by a resistive divider bridge (R1, R2, ........, RN). In the in the case of a linear distribution of the voltages, the resistors all have the same value.

The generator of N + 1 discrete voltages can also be built around one or more analog digital converters, themselves piloted by a controller responsible for calculating the values of the N + 1 voltages.

A monochrome or color palette circuit can also allow the discrete voltage generator to be managed according to the request for the user.

Brief description of the drawings

• FIG. 1 represents an example of a signal intended to activate the columns of a matrix screen;
• FIG. 2 represents the luminance / voltage response of a fluorescent microtip screen;
• Figures 3A and 3B show distributions of the luminance as a function of voltage;
• Figures 4 and 5 illustrate the device of the invention;
• Figures 6 and 7 illustrate exemplary embodiments of circuit of the device of the invention.

Detailed description of embodiments

The invention relates to a method for controlling a screen. fluorescent microdots composed of pixels arranged in L lines and M image columns likely to have a discreet number of shades of Grey.

In this process the columns (cathodes) are controlled by signals intended to activate them. These column signals allow the selection of a voltage Vi chosen from N + 1 with N≥2 and 0≤i≤N.

These N + 1 voltages Vi are chosen such that their values form a strictly increasing sequence. Line time is subdivided into S equal time intervals Δt, S being an integer with S≥2. We obtain thus a grid of the time-voltage space of Q = SxN boxes, each box representing a luminance contribution proportional to its weight VxT.

During a line selection time T _L and as a function of the gray level to be displayed, the column signal must take a first voltage value Va during a certain number of time intervals Δt, then if necessary during the intervals of remaining time, at most a second voltage value Vb, this second value being consecutive to the first in the series of N voltages. This second value must therefore be such that: Vb = Va ± ΔV

If the rank 1 gray tint is obtained by applying a voltage V1 for a time Δt, the shade of gray of rank 2 will be obtained by applying the voltage V1 for a time Δt + Δt, and to obtain the shade of gray of rank S it will have to be applied for S times the time Δt. The tint of rank gray (S + 1) will be obtained by applying a voltage V2 during a time Δt and voltage V1 during the (S - 1) other time intervals.

FIG. 1 gives an example of a signal intended to activate the columns of a matrix screen in the case N = 8 and S = 8 which makes it possible to generate N x S = 8 x 8 = 64 gray levels; the signal corresponds to the display of gray No. 42, that is to say the activation of boxes 1 to 42 in the figure. We see that compared to a conventional command operating in multilevel we can obtain a large number of gray levels for example 256 with the couples {N = 16 and S = 16} or {N = 8 and S = 32} while having a single additional transition which takes place between two neighboring levels (ΔV = V _N / N in the particular case of a linear series of voltages), the "cost" in consumption is therefore minimum since the capacitive consumption of a transition is proportional to the square of the voltage difference ΔV.

The N + 1 voltages Vi can for example be such that, for i ranging from 0 to N: Vi = ix (V _N / N), which gives the same weight ΔV x Δt at each difference between consecutive gray levels. However, it is advantageously possible to choose a non-linear distribution by varying the voltages differently, which can make it possible to adjust the electro-optical response of the screen to the wishes of the user. Indeed, the luminance / voltage response (line / column or grid / cathode V _GC ) of a fluorescent microtip screen being of the type of that of FIG. 2, using equal time intervals and judiciously chosen voltages, we can match this response in successive ranges to the desired curve.

To obtain a determined series of luminance values, we can find one and only one sequence of tensions from a curve of luminance / voltage response. We can thus perform a gamma correction for the television application or fulfill the function of a pallet circuit for the computer-type applications.

The process of the invention, contrary to the request for EP-0 478 386 cited above, applies to the specific case of screens with microtips. The electro-optical response of these screens differs from that of active matrix liquid crystal displays (TFT). Indeed for a type screen TFT, a voltage is charged for a line time which is then kept on the pixel during an entire frame (full image scan), this voltage controlling the tilting of molecules, and therefore the modulation of light transmitted throughout the frame. For a microtip screen, the answer electro-optics is done immediately during the line selection time and the pixel considered only emits during this line time.

The voltage applied to a selected line brings the line / column voltage at the limit of the emission threshold (while the voltage row / column for an unselected row is always below this threshold). Also, the voltage applied to a column, during this selection time line, immediately causes a more or less significant emission (depending on the luminance / voltage curve). The emission therefore takes place only during the time of line selection.

The method described in the invention relies on this characteristic to propose a construction of the gray levels by box. Schematically, within a line selection time, the control possibilities of a pixel are represented by the area of a rectangle having one side of dimension V (column voltage = cathode voltage) and one side of dimension T _L. It is proposed to make a grid of this area with S equal time intervals for the side T _L and N voltage intervals (equal or not) for the side V. As for patent application EP-0 478 386, practice limits the discrete number of usable external voltages Vi. We thus obtain a grid of S x N boxes. We can then obtain Q = (SxN) +1 gray levels, (from 0 to Q-1) by the simultaneous selection of 0, 1, 2, or (Q-1) boxes.

The selection of a set of these boxes must be done in a well-determined order on the one hand because the tensions not necessarily being equal the respective weight of each box depends on its level of tension (a random selection of these boxes introduce discontinuities on the response curve) and, on the other hand, because the primary purpose of the addressing system of the invention is to minimize the transitions on the applied column voltages (capacitive consumption aspect). We therefore agree to play by adding boxes along the axis T _L , before moving to boxes of higher rank along the axis V. This translates in practice by the display of a given gray level, by the selection of a first voltage V _i during (Sj) time intervals, then by the selection of a second voltage V _i +1 (or V _i -1) during the j other time intervals of the line considered.

Thus, the method of the invention digitizes the time space of row / column voltage selection by cutting this time into S time intervals predefined equals so that switching between two voltages selected can be done at the start of any interval. In the EP-0 478 386, we find in the order of the columns the switching between two neighboring voltages from a generator. However the purpose of this switching being to store a capacitor on the pixel, from an intermediate voltage to the two selected voltages, this voltage intermediate is obtained by using the charging time of said capacitor at through its control transistor by playing on the start time of the charge. Also, unlike the invention, switching between the two rather, the selected voltages are found at the end of the line selection time.

Figures 3A and 3B are intended to help better understand the possibility of adjusting the differences between the N voltages.

FIG. 3A shows the distribution of the luminances L obtained in the case of deviations of equal voltages V.

FIG. 3B shows a linear distribution of the luminances L obtained by adjusting these voltages V.

• une source de données numériques 10 fournissant des mots K codant l'information à afficher sur k bits (dans le cas d'une source analogique, il faut effectuer une conversion analogique digitale des données) ;
• un contrôleur d'écran 11 recevant des signaux de synchronisation de la source de données et gérant les différents signaux propres à piloter des circuits 13 de commande des colonnes de l'écran 15 ;
• un générateur 14 de N + 1 tensions discrètes ;
• les circuits 13 de commande des colonnes de l'écran 15. Le contrôleur d'écran 11 sert également à piloter les circuits 12 de commande des lignes.

The invention also relates to an electronic device for controlling the columns of the screen. This device comprises, as shown in FIG. 4:

• a digital data source 10 providing words K coding the information to be displayed on k bits (in the case of an analog source, it is necessary to perform a digital analog conversion of the data);
• a screen controller 11 receiving synchronization signals from the data source and managing the various signals suitable for driving circuits 13 for controlling the columns of the screen 15;
• a generator 14 of N + 1 discrete voltages;
• the circuits 13 for controlling the columns of the screen 15. The screen controller 11 is also used to control the circuits 12 for controlling the lines.

The circuits 13 for controlling the columns of the screen are conventionally constituted by a shift register 16 of k inputs and kx M outputs, each output being associated with a storage flip-flop 17. In other words, each control circuit of a column includes a part of the shift register and k flip-flops. Each word K thus memorized in the k flip-flops of a control circuit of a column must be able to validate the control of a voltage chosen from N + 1. The control circuit therefore comprises multiplexing means. The original part of the device concerns these means. FIG. 5 illustrates the constitution of the multiplexing means specific to the invention. These means include a circuit n bit binary decoder 22 (1 among 2 ⁿ ), a comparator 24, a combinational logic circuit 25 and N + 1 analog switches 21 whose outputs are all connected to the column output Sc of the channel considered and the analog inputs are connected to the generator 14. The validation inputs of these switches are determined as described below:

• si on dispose de N + 1 tensions, le mot H est constitué des h bits de poids fort de K, avec 2^h = N + 1 ;
• le mot B est constitué des (k-h) bits de poids faible restant.

The word K provided by the source 10 is subdivided into two words H and B, such as:

• if there are N + 1 voltages, the word H consists of the h most significant bits of K, with 2 ^h = N + 1;
• word B is made up of the remaining least significant bits (kh).

If we consider for example the binary word K: 11001110

For N = 8, we have h = 3 and the word H will be made up of the three first bits either: 110 and word B of the last five, or: 01110.

The word H is used to determine the pair of voltages (Vi, Vi + 1) adapted to the gray level to be displayed and supplies the circuit 22 binary decoder n bits 1 among 2 ⁿ to produce the N signals H ₀ to H _N-1 which translate the coding of H.

We have for example the following truth table of a 3-bit binary decoder (1 among 8). (2 ³ = 8) starters exits h ₂ h ₁ h ₀ H ₀ H ₁ H ₂ H ₃ H ₄ H ₅ H ₆ H ₇ 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1

This example is given for a decoder operating in positive logic (output active at state 1), one can also operate with a decoder working in negative logic, the important thing is that there is only one only one valid output at a time so as to have only one switch closed at at some point.

For this, we have the sequencer which supplies the index P of the addressing sequence within a line time, P being coded on (kh) bits. This sequencer can for example be a counter 23 whose CPG clock comprises 2 ^(kh) pulses per line time, this counter 23 being initialized at each line time ("load" signal). This counter 23 can be an external counter or a counter per circuit. Let E be a coding bit, comparator 24 makes it possible to compare B and P such that: P <B ⇒ E = 1 P ≥ B ⇒ E = 0.

This coding bit E provided by the comparator 24 makes it possible to position the passage from Vi to Vi + 1 over time. The combinational logic circuit 25 between the signal E and the signals H ₀ to H _N-1 makes it possible to obtain the signals F ₀ to F _N which drive the N + 1 analog switches. We have : F 0 = E .H 0 F 1 = EH o + E .H 1 F i = EH i-1 + E .H i F N-1 = EH N-2 + E .H N-1 F NOT = EH N-1

As shown in FIG. 6, the generator 14 of N + 1 discrete voltages can be, for example, made up of N + 1 operational amplifiers 30 mounted as followers, with input voltages fixed by a resistive divider bridge R1, R2, ..., RN. In the particular case of FIG. 6, where the power supply terminals of the divider bridge are themselves voltage sources, the extreme voltages V ₀ and V _N are obtained directly (without adaptation of impedance by an operational amplifier mounted in follower) from said terminals. In the case of a linear distribution of the voltages, the resistors R1-RN will all have the same value, otherwise their ratio will be calculated according to the values V ₀ to V _N desired.

But this generator of N + 1 discrete voltages can also be frame, as shown in Figure 7, around one or more converters analog digital 31, themselves controlled by a controller 32 responsible for calculate the values of the N + 1 voltages, and followed by amplifiers 33.

In cathode ray tube applications, you can usually choose to display a certain number of colors (or levels of gray for a monochrome screen) chosen from a much larger number great, this functionality is usually fulfilled by a specific circuit called "pallet circuit". This operation is possible within the framework of the invention, we then asks the pallet circuit to manage the generator of discrete voltages and therefore the palette according to the user's request.

Compared to patent application EP-0 478 386, it should be noted that in the implementation of the device of the invention the need to have equal time intervals leads to a simplification, since the switching moments are perfectly defined and do not depend on any external parameter. It is thus possible to use a simple line sub-time counter CPG and to operate by comparison between the state of the counter and the set of bits constituting the least significant of the data to be displayed. In patent application EP-0 478 386 the sub-times (TM signals) are supplied externally because the position of triggering the transition from Vi to Vi + 1 depends on the characteristics of the screen to be controlled (the time constant R _s x C _s varies for example with the size of the screen)

Claims (10)

1. Process for the control of a microtip fluorescent display formed from pixels arranged in accordance with L rows and M columns of images which can have a discreet number of Q grey tones, said process comprising, at each selection of a row of the display during a row selection time T, the simultaneous application to the display columns of voltages corresponding to the grey levels to be displayed at the image points corresponding to the intersection of said row and said columns, characterized in that the different column voltage values applicable to the columns are chosen in a strictly increasing sequence of N+1 values such that the row selection time is subdivided into S equal time intervals Δt, each voltage value being applied an integral number of time Δt, (NxS)+1 representing the number Q of grey levels, with N≥2 and S≥2, and in that during the row selection T_L and as a function of the grey level to be displayed at an image point, the corresponding column voltage assumes a first value Va for a certain number of time intervals At, and then, if need be, during the remaining time intervals at the most one second value Vb, said second value following on to the first in the sequence of N voltages.
2. Device for controlling the columns of a microtip fluorescent display making it possible to display grey levels according to the process of claim 1 comprising a digital data source (10) supplying words K encoding the information to be displayed on k bits, a display controller (11) receiving synchronization signals from the data source and controlling the different signals able to drive the control circuits (13) of the display (15) columns, a generator of (N+1) discreet voltages, control circuits (13) for the display columns incorporating a shift register (16) with k inputs and k x M outputs, each output being associated with a storage flip-flop (17) and analog multiplexing means connected on the one hand to the k x M flip-flops and to the generator and on the other to the M columns, said means making it possible to switch to each column a voltage chosen from among N+1 as a function of the word K stored in the k flip-flops associated with said column.
3. Device according to claim 2, characterized in that each word K stored in the k flip-flops of a control circuit of a column is subdivided into two words H and B such that the word H is constituted by the h most significant bits of K with 2^h=N+1 and such that the word B is constituted by the (k-h) remaining least significant bits, the multiplexing means of the control circuit of a column comprising a binary decoding circuit of n bits 1 from among 2ⁿ connected to the h flip-flops of said column having in the memory the h most significant bits, said circuit producing N signals H₀ to H_N-1 translating the coding of H and making it possible to select the pair of column voltages (V_i, V_i+1) adapted to the grey level to be displayed, a comparator connected to the (k-h) least significant bits and with a sequencer able to supply the addressing sequence within a row time coded on (k-h) bits, a combinatorial logic circuit connected to the outputs of the decoding circuit and to the comparator, N+1 analog switches, whose analog inputs are connected to the generator and the validation inputs to the combinatorial logic circuit and whereof all the outputs are connected to the corresponding column.
4. Device according to claim 3, characterized in that the sequencer is a counter (23), whose clock has 2^(k-h) pulses per row time, said counter being initialized for each row time.
5. Device according to claim 3, characterized in that the comparator (24) performs the comparison between the signals P and B and supplies a coding bit E such that: P < B⇒E = 1 P ≥ B⇒E = 0.
6. Device according to claim 3, characterized in that the combinatorial logic circuit (25) between the coding bit E and the signals H₀ to H_N-1 makes it possible to obtain the signals F₀ to F_N, which drive the N+1 analog switches, such that: F0 = E.H0 F1 = E.HO + E.H1 Fi = E.Hi-1 + E.Hi FN-1 = E.HN-2 + E.HN-1 FN = E.HN-1 so as to position in time the change of voltage Vi to Vi+1.
7. Device according to claim 2, characterized in that the generator of N+1 discreet voltages (14) is constituted by operational amplifiers connected as follower amplifiers (30), with input voltages fixed by a resistive divider bridge (R1, R2, ... RN).
8. Device according to claim 7, characterized in that in the case of a linear distribution of the voltages, the resistances (R1, R2, ... RN) of the divider bridge all have the same value.
9. Device according to claim 2, characterized in that the generator of N+1 discreet voltages (14) is constructed on the basis of one or more digital-analog converters (31), themselves driven by a controller (32) responsible for calculating the values of the N+1 voltages.
10. Device according to claim 2, characterized in that it comprises a black and white or colour palette circuit making it possible to control the discreet voltage generator in accordance with the wishes of the user.

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