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EP0428324A2 - Panneau d'affichage adressé en matrice et circuit de commande compatible avec un TRC - Google Patents

Panneau d'affichage adressé en matrice et circuit de commande compatible avec un TRC Download PDF

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Publication number
EP0428324A2
EP0428324A2 EP19900312187 EP90312187A EP0428324A2 EP 0428324 A2 EP0428324 A2 EP 0428324A2 EP 19900312187 EP19900312187 EP 19900312187 EP 90312187 A EP90312187 A EP 90312187A EP 0428324 A2 EP0428324 A2 EP 0428324A2
Authority
EP
European Patent Office
Prior art keywords
pixels
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Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19900312187
Other languages
German (de)
English (en)
Inventor
John Francis King
Mark Robert Vincen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Delco Electronics LLC
Original Assignee
Delco Electronics LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Delco Electronics LLC filed Critical Delco Electronics LLC
Publication of EP0428324A2 publication Critical patent/EP0428324A2/fr
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto

Definitions

  • This invention relates to matrix addressable flat panel display and driver arrangements, and more particularly to a display/driver configuration which may be directly interfaced with a conventional CRT display controller.
  • Matrix addressable flat panel displays have become increasingly popular as an alternative to the cathode ray tube (CRT), both for television and display applications. This is particularly so in applications where the display depth is limited, such as in automotive and aerospace display panels.
  • CTR cathode ray tube
  • a CRT graphics controller supplies the RGB (red, green and blue) colour information in synchronism, colour element by colour element, matrix addressable display drivers typically require sequential access to the colour information.
  • the controller must be customized to generate additional information, or the driver must be customized to accept and store synchronously generated data. Either approach adversely affects both cost and performance of the system.
  • FIG. 1 An example of a conventional active matrix liquid crystal display and driver is shown in Figure 1, where the display panel and driver circuit elements are designated by the reference numerals 10 and 12, respectively.
  • the display panel 10 comprises an N x M array of red (R), blue (B) and green (G) pixels formed at the intersections of the N laterally extending rows and the M vertically extending columns.
  • R red
  • B blue
  • G green
  • M pixels are arranged in a predefined and uniform colour sequence, RBGRBG etc.
  • the pixels are colour shifted in either direction by one column. Consequently, each row and each column contains pixels of all three colours.
  • a row-activated thin-film transistor at the intersection of each row and column applies a column-supplied control voltage to the respective pixel to control its intensity whenever the transistor is activated.
  • the driver 12 includes a row circuit 14 for successively activating the various rows of transistors, and one or more column circuits 16, 18 for storing the appropriate control voltages.
  • the column circuit 16 supplies control voltages to the odd numbered columns and the column circuit 18 supplies control voltages to the even numbered columns.
  • the row circuit 14 comprises a bank 20 of individual driver circuits connected to the various rows of the display panel 10, and a shift register 22 for successively activating the driver circuits of the bank 20 at a shift frequency determined by the horizontal synchronization signal HSYNC on line 42.
  • a vertical synchronization signal VSYNC on line 26 periodically resets the shift register 22 to the first to top row.
  • the column circuits 16, 18 each comprise a driver bank 28, 30 of individual driver circuits connected to the various columns of the display panel 10, and a shift register 32, 34 for receiving and storing parallel formal digital control voltage data via lines 36, 38.
  • the control voltage data is entered into the shift register 32, 34 under control of the SHIFT CLOCK signal on line 40; when a full row of data has been entered, the HSYNC signal on line 42 signals the driver bank 28, 30 to latch the shift register data.
  • the pixels are divided into (M X N)/3 groups of colour elements or triads, each comprising a red pixel, a green pixel and a blue pixel.
  • the pixels may be grouped linearly, as indicated by the outlined pixels in row 1, or staggered as indicated by the outlined pixels in rows 3 and 4.
  • the red, blue and green pixel control voltage data is supplied to the driver 12 via lines 44, triad by triad.
  • a colour select circuit designated generally by the reference numeral 45 comprises a demultiplexer (select one-of-three) 46 and a serial to parallel shift register 48 operating under the control of the DOTCLOCK signal on line 50 for suitably applying the pixel control voltage data from lines 44 to lines 36 and 38.
  • the data on lines 44 is in serial format and is applied to the input channels of the demultiplexer 46, which presents individual colour data in succession to serial to parallel shift register 48 on line 54. Since the display columns contain different colour elements and all three pixel colours, the order of the data supplied to serial to parallel shift register 48 varies with the triad grouping and the overall display size.
  • the triad configuration chosen for a display can also affect the quality of the displayed image and the complexity of the colour select circuit 45.
  • Linear triad configurations, as illustrated in row 1 reduce the complexity of the colour select circuitry, but yield reduced display quality with their 3:1 aspect ratio.
  • Staggered triad configurations, as illustrated in rows 3 and 4 improve the display quality with a 2:1 aspect ratio, but increase the complexity of the colour select circuit 45.
  • a matrix addressable display in accordance with the present invention is characterised by the features specified in the characterising portion of claim 1.
  • the present invention is directed to an improved matrix addressable flat panel display which can be directly interfaced with a conventional CRT graphics controller and which provides both superior display quality and reduced driver complexity.
  • the pixels in each row of the display are formed in every other column, and the pixels in every other row are laterally shifted in both location and colour with respect to adjacent rows such that the pixels in each column are of the same colour.
  • the colour elements are defined by a triad of first and second horizontally adjacent pixels of one row and a third pixel residing in the column intermediate the first and second pixels and in a vertically adjacent row. Since each column contains pixels of only one colour, the colour select circuitry is greatly simplified or eliminated. Moreover, the aspect ratio of the colour element is 1:1 resulting in drive signal compatibility with CRT graphics controllers.
  • the row driver circuits activate two rows at a time, and the colour separation of the control voltage information by the graphics controller is maintained in the display driver.
  • the column driver circuits are split into individual shift register and driver banks dedicated to processing the red, blue and green control voltage data, and a simple toggle circuit controls the flow of the information.
  • the reference numeral 100 generally designates a display panel according to this invention.
  • the display panel 100 comprises a plurality of red (R), blue (B) and green (G) pixels distributed in a row x column matrix array.
  • the pixels of display panel 100 are only formed at alternate row/column intersections.
  • the pixels of every other row are laterally shifted by one column.
  • pixels reside only in the odd numbered columns of rows 1a, 2a, 3a, etc. and in the even numbered columns of rows 1b, 2b, 3b, etc.
  • the conductor traces for pixels in the even numbered columns run between the pixels of the odd numbered columns
  • the conductor traces for pixels in the odd numbered columns run between the pixels of the even numbered columns.
  • the colour sequence of the pixels in rows 1b, 2b, 3b, etc. is shifted so that triangular-shaped triads of red, blue and green pixels are formed in each pair of adjacent rows (1a-1b, 2a-2b, 3a-3b, etc.), as indicated by the outlined pixels in rows 1a-1B.
  • the above-described panel configuration has two important properties: (i) the triads have a 1:1 aspect ratio, and (2) the pixels in each column are all of the same colour.
  • the first property provides the superior image quality of a CRT.
  • the second property permits a reduction in the drive circuit complexity and compatibility with standard CRT graphics controllers, as described below in reference to Figure 3.
  • Figure 3 illustrates the display panel 100 of Figure 2, a row circuit 110, and upper and lower column circuits 112 and 114.
  • the row circuit 110 comprises a bank 116 of individual driver circuits connected to the various rows of the display panel 100, and a shift register 118 for successively activating the driver circuits of the bank 116 at a shift frequency determined by the horizontal sync signal HSYNC on line 120.
  • the vertical sync signal VSYNC on line 122 periodically resets the shift register 118 to row 1.
  • the bank 116 activates two rows at a time -- that is, 1a and 1b, 2a and 2b, etc. Due to the triad configuration described above in reference to Figure 2, each output line of bank 116 activates all the pixels of the triads residing in the respective rows. In other words, no partial triads are activated.
  • the upper and lower column circuits 112, 114 each comprise a driver bank 130, 132, 134; 136, 138, 140 of red, green and blue driver circuits connected to the various columns of the display panel 100.
  • the red driver bank 130 connected to the red pixels residing in odd numbered columns, and the red driver bank 136 is connected to the red pixels residing in even numbered columns.
  • the green driver bank 132 is connected to the green pixels residing in odd numbered columns, and the green driver bank 138 is connected to the green pixels residing in even numbered columns.
  • the blue driver bank 134 is connected to the blue pixels residing in odd numbered columns, and the blue driver bank 140 is connected to the blue pixels residing in even numbered columns.
  • the red, green and blue driver banks 130 -­140 are connected to respective red, green and blue shift registers 142, 144, 146; 148, 150, 152 which receive and store parallel format digital control volta9e data from the red, 9reen and blue serial data lines R, G and B.
  • the data is entered into the shift registers 142, 144, 146; 148, 150, 152 one pixel at a time.
  • the upper red, green and blue shift registers 142, 144 and 146 only receive control voltage data for the odd numbered panel columns
  • the lower red, green and blue shift registers 148, 150 and 152 only receive control voltage data for the even numbered panel columns.
  • the control voltage data is distributed between the upper and lower column circuits 112 and 114 by upper and lower flip-flops 154, 156. Both flip-flops 154 and 156 are clocked by the DOTCLOCK (D) signal on line 158, and oscillate at one-half of the DOTCLOCK frequency.
  • DOTCLOCK DOTCLOCK
  • the event triggering logic level transition (rising or falling edge) of upper flip-flop 154's Q output occurs at the same time as that of lower flip-flop 156's Q-bar output.
  • the event triggering logic level transition (rising or falling edge) of upper flip-flop 154's Q-bar output occurs at the same time as that of lower flip-flop 156's Q output.
  • the Q output of upper flip-flop 154 enables the upper red and blue shift registers 142 and 146 to receive red and blue control voltage data while the Q-bar output enables the upper green shift register 144.
  • the Q-bar output of lower flip-flop 156 enables the lower red and blue shift registers 148 and 152 to receive red and blue control voltage data while the Q output enables the lower green shift register 150.
  • a display-enable (DE) signal on line 160 presets the upper and lower flip-flops 154 and 156 to synchronize their operation with the control voltage data stream on lines R, G and B.
  • the red and blue components are directed to upper red and blue shift registers 142 and 146, respectively, and the green component is directed to the lower green shift register 150.
  • the red and blue components are directed to lower red and blue shift registers 148 and 152, respectively, and the green component is directed to the upper green shift register 144.
  • the red and blue components are directed to upper red and blue shift registers 142 and 146, respectively, and the green component is directed to the lower green shift register 150, repeating the pattern of the first triad.
  • the fourth triad (rows 1a-1b, columns 10-12) of data is generated, the red and flue components are directed to lower red and blue shift registers 148 and 152, respectively, and the green component is directed to the upper green shift register 144, repeating the pattern of the second triad.
  • the above-described data process is continued until the control voltage data for each triad of rows 1a-1b is stored in the shift registers 142-152.
  • the upper red shift register 142 will have stored the R1, R3, R5, R7, etc. data (where the numeral indicates the triad number);
  • the upper green shift register 144 will have stored the G2, G4, G6, G8, etc. data;
  • the upper blue shift register 146 will have stored the B1, B3, B5, B7, etc. data;
  • the lower red shift register 148 will have stored the R2, R4, R6, R8, etc. data;
  • the lower green shift register 150 will have stored the G1, G3, G5, G7, etc. data;
  • the lower blue shift register 152 will have stored the B2, B4, B6, B8, etc. data.
  • the horizontal sync signal HSYNC on line 120 directs the driver banks 130-140 to latch the data from the respective shift registers 142-152, and the vertical sync signal VSYNC signal on line 122 directs the shift register 118 and bank 116 to activate the rows 1a-1b via driver output line 1 to suitably energize the respective pixels of display panel 100. Subsequent horizontal sync pulses HSYNC direct the row shift register 118 to activate successive row pairs as described above.
  • control voltage data for successive row-pairs of pixels is loaded into the shift registers 142-152, latched into the driver banks 130-140 and applied to the respective control panel pixels.
  • the colour select circuitry 45 of the prior art display/driver is substantially eliminated since colour separation of the control voltage date is maintained by the drive circuitry.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
EP19900312187 1989-11-13 1990-11-07 Panneau d'affichage adressé en matrice et circuit de commande compatible avec un TRC Withdrawn EP0428324A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US43591789A 1989-11-13 1989-11-13
US435917 1989-11-13

Publications (1)

Publication Number Publication Date
EP0428324A2 true EP0428324A2 (fr) 1991-05-22

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Application Number Title Priority Date Filing Date
EP19900312187 Withdrawn EP0428324A2 (fr) 1989-11-13 1990-11-07 Panneau d'affichage adressé en matrice et circuit de commande compatible avec un TRC

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EP (1) EP0428324A2 (fr)
JP (1) JPH03174581A (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2742910A1 (fr) * 1995-12-22 1997-06-27 Thomson Multimedia Sa Procede et dispositif d'adressage d'un ecran matriciel
GB2351835A (en) * 1996-12-30 2001-01-10 Hyundai Electronics Ind A method of driving a liquid crystal display
GB2320790B (en) * 1996-12-30 2001-04-04 Hyundai Electronics Ind Pixel arrangement structure, liquid crystal display device using the same and method for driving the device
WO2002052535A2 (fr) * 2000-12-22 2002-07-04 Ifire Technology Inc. Systeme de pilote d'affichage electroluminescent a pixels partages
US6442894B2 (en) 1998-02-10 2002-09-03 Southpac Trust International, Inc. Floral wrapper having printed design with shaded and highlighted areas

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2742910A1 (fr) * 1995-12-22 1997-06-27 Thomson Multimedia Sa Procede et dispositif d'adressage d'un ecran matriciel
WO1997023861A1 (fr) * 1995-12-22 1997-07-03 Thomson Multimedia Dispositif d'adressage d'un ecran matriciel
US6252613B1 (en) 1995-12-22 2001-06-26 Thomson Multimedia, S.A. Matrix display addressing device
GB2351835A (en) * 1996-12-30 2001-01-10 Hyundai Electronics Ind A method of driving a liquid crystal display
GB2320790B (en) * 1996-12-30 2001-04-04 Hyundai Electronics Ind Pixel arrangement structure, liquid crystal display device using the same and method for driving the device
GB2351835B (en) * 1996-12-30 2001-04-25 Hyundai Electronics Ind Method for driving a liquid crystal display device
US6442894B2 (en) 1998-02-10 2002-09-03 Southpac Trust International, Inc. Floral wrapper having printed design with shaded and highlighted areas
US6708447B2 (en) 1998-02-10 2004-03-23 Southpac Trust International, Inc. Floral wrapper having printed design with shaded and highlighted areas
WO2002052535A2 (fr) * 2000-12-22 2002-07-04 Ifire Technology Inc. Systeme de pilote d'affichage electroluminescent a pixels partages
WO2002052535A3 (fr) * 2000-12-22 2003-11-20 Chun-Fai Cheng Systeme de pilote d'affichage electroluminescent a pixels partages
US7027013B2 (en) 2000-12-22 2006-04-11 Ifire Technology, Inc. Shared pixel electroluminescent display driver system

Also Published As

Publication number Publication date
JPH03174581A (ja) 1991-07-29

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