EP0353249A4

EP0353249A4 - Parallel networking architecture

Info

Publication number: EP0353249A4
Application number: EP19880904083
Authority: EP
Inventors: Douglas M. Pihl; Gary D. Connell; John M. Hedin; Blair A. Wilson; John D. Hardy, Jr.
Original assignee: LEE DATA CORP
Current assignee: LEE DATA CORP
Priority date: 1987-04-06
Filing date: 1988-04-01
Publication date: 1992-01-08
Also published as: JPH02503366A; WO1988008167A1; EP0353249A1

Abstract

A new digital data transmission architecture is disclosed utilizing a networking concept which can be used to interconnect in parallel, contemporaneously, the many resources and facilities which are normally interconnected with one or more host computer systems (24, 25). Because the adapter logic (20) and matrix distribution switch (30) disclosed serve solely to interconnect a requesting device (29, 35) with the destination receiving device (29, 35), the invention can be used in any data transmission environment where any one of three or more data transmission devices (29, 35) are configured to transmit to any of the interconnected devices (29, 35). Since the N x N switch (30) is configured to establish a separate path for each device requesting a transmission, independent parallel processing is achieved.

Description

PARALLEL NETWORKING ARCHITECTURE BACKGROUND OF THE INVENTION The field of the invention is an apparatus for interconnecting computing devices. More particularly, the invention relates to a computer system in which the system resources selectively transmit and receive data from other resources through a switched distribution network.

Traditionally communication between a host computer and the various peripherals and resources which make up a computer system has been sequential and serial with substantial contention among resources to access the single data and address bus which is provided. It has long been recognized that this contention has been a serious limitation on the speed of processing and the manipulation of data and commands to and from the various resources that are utilized in a computer system. _$ny and varied attempts have been made to alleviate this problem. Controllers have been provided with separate channels. Various means and apparatus have been provided to establish priority between contending requests for access to the data bus and in some cases the most commonly used resources such as the host computer and the memory devices have been inter¬ connected in a mariner that makes them most accessible to the resources contending for their attention.

As the speed of processing has- been continuously increased and the on-board intelligence of the various connected resource devices has been enhanced, there has become an ever increasingly urgent need to facilitate the transmission and handling of data transmission between the various components or resources of a computer system. The present invention is. directed to and addresses this urgent need.

SUMMARY OF THE INVENTION The present invention is used to interconnect the various resources commonly used in a computer system. Each of the devices used in the system is connected through adapter logic to a distribution matrix switch. The matrix switch is configured to establish separate paths from any device attached to the switch to any other device to which the switch is connected. In this manner simultaneous and parallel processing can occur at the same time between resources which are connected through the switch.

Data transmission is achieved with the data

10 signals and three handshake signals, two which are directed towards the receiving device and one acknowledge signal from the receiving device. The data is transmitted in a packetized format pursuant to which the address of the device to which the data is directed

---*^•' precedes the bytes of substantive data. To assure proper operation an error detection algorithm is used during the transmission and receipt of data and the result of the error check is used to trigger a handshake signal indicating that the data has been correctly ^U received.

To achieve the invention a resource board having adapter logic is utilized for each resource having an interface configured to receive the data for transmission through the distribution matrix. Under

25 microprocessor control the adapter logic stores and transmits data and performs the error detection algorithm. The same logic receives data and handshake signals from the destination resource for transmission back to the requesting device.

³⁰ The resource board having the adapter logic is connected to the switch matrix which includes associated control logic .

The distribution matrix sequentially scans the various devices attached to .the matrix to accept a

³⁵ request for service. Arbitration logic is provided to be sure that two resources do not access the same destination device simultaneously. Upon receipt of a request for service the control logic establishes an interconnection to the destination device which is maintained until all data has been successfully trans- mitted. If, during the transmission, a second request is made to a different device, the same process is followed and a separate independent connection is made between the second requesting device and the second destination device. In this manner all connected devices can be interconnected one with the other until all the resources have been interconnected.

These and other advantages and objectives of the invention will become obvious to those skilled in the art upon a review of the following description of a preferred embodiment, the accompanying drawings and the claims- appended hereto.

DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of the invention

*•_ showing how system resources are connected to and through the distribution matrix to achieve the objectives of the invention;

Figure 2 is a block diagram of a typical resource board which connects through an interface to hard or soft disks, displays and the like and communi- cates with one or more host computers. Each resource board can be configured to connect to the distribution switch with 22 lines, 11 for transmission and 11 for received signals;

Figure 3 is a block diagram of the distribution switch shown in a 16 x 16 matrix configura¬ tion with control logic which sequentially polls the connected devices, establishes the connection between devices and arbitrates between requests for the same device; Figure 4 is a timing diagram of the data transmission, including the address byte, and the three handshake signals, data frame (DFR) , data byte valid (DBV) and the return signal from the distination device, data byte acknowledged (DBA) ;

Figure 5 is a schematic diagram of components of the adapter logic; and

Figure 6 is a schematic diagram of an embodiment of the sequence scanner, the arbitration logic and a switch matrix which is constructed in accordance with the invention. DESCRIPTION OF A PREFERRED EMBODIMENT

The resource board 20 and matrix switch 30 of the invention is well adapted to be created using very large scale integrated (VLSI) circuits. The invention, however, can also be configured with discrete compo- nents. To facilitate a discussion of the principles used to achieve the invention, discrete components are described as a preferred embodiment of the invention. Those skilled i the art, however, will realize that achieving the function and purpose of the invention using VLSI chips is within the intendment and scope of the claims appended hereto.

Figure 1 is an overall block diagram of a typical system which is interconnected through the distribution matrix 30 using resource boards having adapter logic 20 to interface the system components to and through the switch 30.

As shown in block diagram form in Figure 1, the distribution matrix 30 interconnects all _of the resources which are typical in a computer system. These include communication systems 22,23 to async and sync host computers 24,25, local area networks connected through a network interface resource board 26, main frame computers connected through a local channel resource board 28, various types of display terminals or printers 29 which are indicated in Figure 1 as coax "A" for industry standard IBM compatible displays and printers connected through a station controller resource board 32 and other types of displays 35 such as those manufactured by Lee Data Corporation which are indicated to be connected through a station controller resource board 37 for coax "L" displays and printers. In addition, a gateway resource board 38 can be provided to interconnect to one or more other distribution matrixes 30.

To initiate processing a system processing resource board 41 can be utilized which can include diagnostic or self test routines to be run to make sure that the basic operation of the board is satisfactory.

Also provided is a system loader board 43 which can access a program off of any type of storage media such as hard disk storage 44 or floppy disk storage 45. The initial loading routine queries the available addresses to determine which resources are "live" or active. Typically the system loader board 43 routine will also load a block of data and set up a transfer through the switch 30 to the system processing resource board 41 to be verified by the acknowledge or read-back technique to be discussed below.

Referring to Figures 2 and 4, a typical system resource board 20 and the distribution matrix data and handshake signals 50-53, the protocol of data trans¬ mission can be understood.

Referring to Figure 2, the typical system resource board typically consists of four control elements 60-63 and transmitter 65 and receiver 66 circuitry. A conventional microprocessor 60, which can be an Intel 8088, is the controller for the resource board 20. This is a typical microprocessor configura¬ tion.

The read/write memory 61 is typically a RAM storage to store an operating program, a temporary data register, scratch pad stack and any other temporary <_^• storage functions that the microprocessor 60 requires.

The read only memory 62 is typically a ROM which stores the boot program. Included in the boot program is diagnostics, initialization routines when power is supplied to the resource board, configuration informa¬ tion and the like. The "real world" interface 65 is the logic required to interface to the different type of devices and environments such as conventional RS232 interfaces and the like. As indicated in Figures 1 and 2 , typical applications would be a disk 44 interface, a floppy disk 45 interface, a coax interface to allow the resource board 20 to communicate to IBM plug compatible displays 29 or Lee Data displays 35. Typical logic would also allow the resource board 20 to interface to a serial networking environment or to interface directly through a channel interface 28 to a main frame computer. It is also possible to interface to any of a variety of communication devices 22,23, asynchronous, synchronous, high speed, low speed, moden- or direct connections, or any other basic logic required to connect or interface to any type of environment that is external to the switch 30.

Error control is preferably by an error detection technique. One such method shown in Figure 2 is a parallel Cyclic Redundancy Check (CRC) . Such systems are conventionally available from companies such as Intel Corporation or Monolithic Memories, Inc. and can be constructed with a series of latches with feedback of bits exclusively orred with other terms within the latch. In a preferred embodiment of the invention, a 16 bit CRC algorithm and result is utilized, generated by a CRC generator 68, which is transmitted as the last two bytes 71,72 of the data transmission 51 shown in Figure 4. The same CRC circuit is used as the CRC checker 74 for received data by the receiving resource board 20. As will be discussed in more detail below, if the calculated CRC by the CRC checker 74 corresponds to the transmitted CRC generated by the CRC generator 68, which is transmitted as the last two bytes, an acknowledge signal 75 is transmitted as a read-back pulse, shown in Figure 4, indicating the correct receipt of data.

In addition to the CRC generator 68, the transmitter 65 also includes FIFO data storage means 77 and transmit control circuits 79 which will be discussed in more detail below. The receiver circuitry 66 similarly includes FIFO data storage 82 for received data and receiver control circuits 84 which will also be. discussed in conjunction with the detailed schematics of the invention. Referring now to Figure 3, the distribution matrix switch 30 may be constructed in any N x N configuration. As shown in Figure 3, a 16 x 16 matrix 85 is shown with 11 planes or levels. Sixteen connections 88 are made to the switch matrix 85 for transmitted signals, each connection having 11 lines to accommodate the 8 parallel data lines and the 3 handshake signals 50,52,53, XDFR, XDBV and XDBA. Similarly, sixteen receiver connections 91 are made from the attached devices to the switch matrix 85 each having li parallel lines connected to the matrix, the 8 parallel data lines and the 3 handshake signals RDFR, RDBV and RDBA 50,52,53.

Connected to the switch matrix 85 is control circuitry, a scanner or sequence timer 95 which is clocked by a conventional master clock 97.- The sequence timing circuit 95 sequentially polls all transmitter 65 connections 88 to determine whether any device is transmitting a data frame signal 50 indicating a request for service through the switch 85. In the event of a request for service, indicated by a data frame signal 50, sixteen address latches 98 are connected to the data frame sense lines 99 through conventional delay timers

102 to activate one set of the 16 x 16 interconnects

85. The delay timers 102 do not delay on the "attack" or request for service signal. The delay timers 102 delay the disconnection for purposes of the error or no error acknowledge pulse 75.

Arbitration logic 105, which will be discussed in more detail below, is connected to the address latches 98 and the switch 85 to create the connection and to arbitrate between contending requests for the same device. The arbitration logic 105 identifies the row and column addresses for the connection, which includes a reverse connection for the DBA or acknowledge signal 53. The arbitration logic 105 also generates the connect enable signal to make the connection and strobes the data 51 through the switch 85. All components are reset by a conventional reset circuit 108.

Referring now to Figures 2 through 4, the basic protocol of data transmission can be discussed and understood. It should be understood that a typical data transmission, whether microprocessor generated or by Direct Memory Access (DMA), will involve two resource boards 20, one on each side of the switch 30. Thus the discussion relating to Figures 2 and 5 relating to transmitted and received signals and processing are normally directed to a first resource board 20 which transmits to connections 88 through the switch 85 and a second,- separate board 20 of similar design and configuration which receives the signals from connec- tions 91 through the switch 30. It is, however, possible with the invention for a device to transmit to itself for test purposes and the like.

The first byte 55 of any data transfer 51 as shown in Figure 4, is the destination address, where the data is to be sent. That data byte 55 will initiate the CRC generation 68 and will go out on the XMIT data lines 110, which are driven into the distribution matrix 30.

After a short period of time, the XDFR signal 112 will be activated. That signal 112 is a high going signal which is high or active for the entire data 55 trans- mission. When bit 112 is activated, the arbitration logic 105 which is internal to the switch 30 and shown in Figure 3, will decide whether that destination is free or not. If it is free, the arbitration logic 105 will permit the connection. That byte 55 will then appear at the receiver port for the corresponding address 91 of the distribution matrix 85. When it is received the receiver control circuit 84 will determine whether or not the received data 115 is correctly addressed for the - connected device which is connected through the real world interface 63. If the address is correct, the data will be stored in the receive data storage 82. The data will also be cycled through the CRC checker 74 and the RDBV signal will validate the byte of data. The DBV signal 52 will be active at the same time that there is active data 51 on the transmit data lines 110.

When the receiver control circuit 84 at the resource board 20 connected to the destination device has received the data 51 and can process the byte 55 of information, the RDBA signal 53 will be asserted which is returned to the transmitter to enable it to send the second byte of information which is the first substan¬ tive data byte. This process, including the haidshake signals 50,52,53, is repeated throughout the data 55 transmission. The data frame signal, XDFR 112, which is received as the RDFR signal or line 116, will always be active throughout the entire message. The transmitter will sequentially put out another byte of data every time that XDBA 117 has gone active^" and gone away. From then on, XDBV/RDBV 121,122 will be active for every byte of information that goes out and the acknowledge signal , to

RDBA 124 from the receiver 66 and XDBA 117 to the transmitter 65 will indicate that the data 55 was received by the receiver 66.

Typically, the data is put into the transmit storage block 77 on the typical resource board 20. After that data is stored, it will be put onto the bus and taken off of the bus one byte at a time by the receiver 66. The receiver 66 in turn will load it into its receive data storage block 82 and will acknowledge 124 every byte it has received. The whole time that the data 55 is going out on lines 110 the transmitter CRC generator 68 will continually perform a calculation based on the CRC polynomial which is implemented in the CRC generator circuit 68 and it will compute a result based on the data 55 that went out.

That result will, at the end of the message, be used as the last two bytes 71,72 of information appended to the end of the message and sent as data 55 to the receiver 66. On the receive end, the CRC checker 74 takes every byte that comes in on lines 115 and performs the same calculation. At the end of the message when the remainder is sent by the transmitter 65, the receiver 66 assumes that it is normal data 55 being received. When the message is terminated, the CRC checker 74 will have a predetermined value as a remainder. If the remainder that is actually generated by the CRC checker 74 matches the predetermined value, then the message is assumed correct.

The data message 55 is terminated when the XDFR/RDFR signal 112,116 goes inactive. The switch connection remains active for a short period of time, due to the delay timers 102 shown in Figure 3, after the DFR signal 50 in order to respond to the message. The response is in the form of RDBA 75 or acknowledge signal being asserted on the line 124,117. When that is asserted, the message is indicated to be received // without error.

Referring now to Figure 3, operation of the distribution matrix or switch 30 can be understood.

As shown in Figure 4, the address byte 55 is initiated before the data frame signal 50. For a 16 x 16 matrix, the four least significant digits in the address byte 55 contain the address code and are connected from the transmitters 88 through.- the switch matrix 85 to the connect address latches 98. The sequencer 95 controls the polling sequence by constantly scanning the sixteen transmitters on lines 88, designa¬ ted 0-F on the drawing, in a perpetual round-robin. As soon as a DFR signal 50 goes high, it is sensed through the delay timers 102 by one of the connect address latches 98. That information is synchronized by the sequence timer 95 and brought into the connect address latch 98 in sync with the scanner 95. The delay timers 102 do not delay in both directions. They only delay on release of the data frame for purposes of the read-back acknowledge pulse 75. On the initial sense there is no delay to the connect address latches 98.

Once the address is latched then two sequence cycles later the address is processed into the multi¬ plexing matrix 85 by the arbitration logic 105. The arbitration logic 105 makes the connection if the receiving address is available. Once the arbitration logic 105 makes the connection, then the address data from the connect address latch 98, fed through the arbitration logic 105, is then latched into the matrix 85. This establishes a cross-point for the matrix 85. Conceptually the matrix is 16 rows and 16 columns with 11 planes. The same intersection will be made through the top 10 planes going ^"in a forward direction and a complementary connection will be made in the 11th plane for the acknowledge return handshake signal 53. If a previous connection had been made to the device, the arbitration logic _.,105 will prevent a requested connection and no acknowledge signal 53 will be returned to a transmitter 65 when a receiving device is not available. A delay function in the transmitting resource board will determine when the transmitting device times out because a receiving device is unavailable. Software control from the read-only memory 62 will establish the number of retries that a transmitter 65 will make. Referring now to Figures 5 and 6, a preferred embodiment of the invention can be discussed when constructed from discrete components. Figures 4 and 5 are schematic diagrams of a typical resource board 20 and a four by four matrix switch 30. It will be understood by those skilled in the art that any N x N switch 30 can be constructed using either the discrete components of Figure 6 or using VLSI circuitry.

Referring to Figure 5a, microprocessor inter¬ face logic 20, is utilized which includes AND and NAND gates and a PAL (Programmable Array Logic) 150 which is used to decode and combine the signals that come off the microprocessor bus and to select certain data register and the control and status registers on the resource board 20. The PAL 150 decodes the microprocessor signals and interfaces them to the balance of the board 20 components. The PAL 150 takes the address control signals _ from the microprocessor bus and combine-, them logically to decode the reads, writes and similar signals from the microprocessor. Also included is a three state octal transceiver, manufacturer's designa¬ tion 7 LS245, used as a data buffer 152 which separates the internal data bus of the adapter logic or resource board 20 from the data bus that the adapter logic interfaces to. Also shown in Figure 5a, are D-flip-flops 152-156 used as control registers. When a transmit or receive operation is being set-up by the microprocessor, the control registers 152-156 configure the transmitter 65 or the receiver 66. As shown in Figure 5a, internal interrupt transmit signals are established 161,162, transmit is enabled 164 and/or a DMA transmit is enabled 166. An end transmission signal 167 is also established by the control register 152 to terminate a transmission. Similarly, D.-flip-flops 155,156 are used for the receive enable 168 and to enable a received DMA transfer 169 and to establish internal receiver interrupt conditioning 170,171 .

Referring to Figure 5b, the balance of the transmitter circuitry 65 is shown. The transmitter 65, and the receiver 66, is run off a 16 megahertz clock 175. A latch 177 is provided for stabilization of the signals before they are connected to a state machine 200. The state machine 200, manufacturer's designation No. PAL-C22V10, is a PAL consisting of both an AND and an OR gates having a series of registers that are on the output. Consequently, when an input changes the state machine 200 will step through a sequence of states which are conditions of the output. After the series is completed, the state machine 200 will wait for another input condition and then continue and stop again. It provides the control of the switch interface handshake. For example, when the transmit enable signal on line 164 is high and data exists in the data transmit register, the sequence machine 200 will cause the frame signal 50, XDFR on line 112, a handshake signal, to be transmitted and then will validate the data with the XDBV handshake signal on line 121. Since the state machine 200 is driven by the 16 megahertz clock 175, it can change states every 62-1/2 nanoseconds.

Consequently, every time a byte is loaded from the processor into the transmit data register 180, the byte is connected to the output bus when the tri-state latch 180 is enabled by the state machine 200. The data byte is followed by the XDBV signal 52 indicating a valid transmission. When the XDBA signal 53 is received, the acknowledge signal, the XDBV signal 52 goes low and the state machine 200 waits for another byte to be received from the processor. As soon as another byte is received, the process is repeated. Control of the state machine 200 is achieved through the transmit control registers 152-154 discussed in connection with Figure 5a.

Referring to Figure 5a, it can be seen how bits 3-7 are used with the transmit control registers to achieve operation of the transmission. Bit 3, D3, forces the end of transmission. Bit 4, D4, enables the DMA mode which is connected to output 3 of the transmit control register 154 and creates the transmit DMA enable signal. Two interrupt transmit signals are also included, an interrupt on the end of transfer and an interrupt on transmit ready. The transmit enable signal from bit 1 , D7, is the signal that enables the trans¬ mitter 65 to transmit.

The data can be held for transmission in a latch 180 for single bytes, which can be manufacturer's designation 74LS374, or a FIFO memory 77 as discussed in connection with Figure 2. The output of the transmit data storage 77, whether it be a latch 180 or FIFO memory 77 is connected to the CRC chip 183, manu¬ facturer's designation EPLD5C090, and to the data lines 110 to the switch 30. The transmission of data bytes 55 will follow the process described above. Every time a byte is loaded into the transmit data storage 180, whether the data transmission scheme is DMA operation or whether the data is sequentially loaded by the microprocessor. Data transmissions will continue, as well as the handshake 50,52,53 signalling, until the end of transmission signal, END XMT, on line 167 goes active. When the end transmit signal 167 goes active, the CRC generator 183 outputs are enabled in two eight bit halves. As data was being transmitted over the line 110 to the switch, the CRC generator 68 was running its algorithm for each byte and the 16 bit remainder is transmitted by transmitting the most significant byte 71 as the second to last data transmission 51 and then the least signifi¬ cant byte 72 as the last data transmission 51, each being processed with the same handshake signals 50,52,53 as the substantive data 51. When the least significant byte 51 has been transmitted and acknowledged, the state machine 200 will drop the XDFR frame signal 112 and the CRC Checker 190 will evaluate the data transmission including the last two bytes 71,72 to generate the received CRC checker 190 status. If the check is valid indicating the correct receipt of data, then one additional pulse 75 will be transmitted back to the transmitter 65 indicating there is no error. This is detected by the read-back flip-flop 183 shown in Figure 5b.

While the frame signal 50 is active, the read-back flop 183 is held in the on state. When the XDFR signal 112 becomes inactive, the read-back flop 183 waits for the last acknowledge pulse 75 shown in Figure 4.

If the pulse 75 is received, the flip-flop 183 will clear because the D input, on pin 2, is tied to ground. This will normally happen at an arbitrary point in time within 500 nanoseconds depending on cable length, propagation delays and the like. At the same time that the data frame signal 50 on line 112 goes low, a delay counter 186 is enabled on line 187 with an asynchronous clear. The delay counter 186 will count eight 16 megahertz clock 175 transitions and then its output, on QD pin 8, line 188 will go high. That time period is the delay interval established to verify the data 55 transmission.

The correctness of the transmission is checked by the state machine 200. If the delay signal on line 188 is high and the read-back flop 183 output on line 189 is not high, the transmission was correct. If the delay signal on line 188 is high and the read-back flop 183 output continues to be high, then an error was made in the data 51 transmission. The read-back flop 183 is then reset and a status signal on line 190 is generated to indicated that a read-back error was detected from the receiver 66.

The XDBA edge detect flip-flop 192 monitors the falling or trailing edge of the acknowledge signal 53. When that occurs it clears the byte ready flop 194. The byte ready flip-flop 194 is set whenever the processor 60 loads the transmit data register 180. When the data 55 is written into the transmit data register 180, the byte ready flip-flop 194 will set which is connected to the state machine 200 to indicate that there is a byte in the register 180 that needs to be transmitted.

Referring now to Figure 5c, the receiver circuitry 66 is shown. The receiver circuitry 66 is similar to the transmitter circuitry 65, however, no state machine logic is included since the timing in the system is dictated by the transmitter circuitry 65. The- receiver circuits are basically edge triggered devices. The receiver ready flip-flop 202 is a converse to the byte ready flip-flop 194. It indicates when the receive data latch 204 is empty. Transmitted data 55 when received is presented at the receive data latch 204, which can be a FIFO, and to the CRC checker 190 which is an equivalent device to the CRC generator 183. The sequence of operation with the data byte connected from the switch 30 includes the receiver enable signal , the data frame active signal and the dat byte valid si gnal ac tive . Also , the receive read flip-flop 202 must be clear indicating that no dat resides in the register 204 . When these conditions ar met, a data byte acknowledge signal 53 is returned .

When the RDBA signal is returned to the transmitter 65 , the transmitter will drop the data byte valid signa 52 . When that occurs , it will be detected by th receive ready flip-flop 202. When that flip-flop 202 is set the data latch 204 will be loaded and the CR checker 190 will be clocked and the byte is received an processed .

Since the receiver ready flip-flop 202 will be s et and the CRC checker chip 190 will have performed a calculation on the first byte , when the receiver ready f lop 202 sets , the data byte acknowledge signal 53 will drop indicating that the data has been received by the receiver 66 .

The receive ready fl ip-flop 202 will remain set until the microprocessor and attached equipment takes the byte from the latch or the FIFO 82 . The read edge detect flip-flop 212 looks for the trailing edge of the read signal so that the status and data is stabilized and no additional byte is received prior to the read signal . At the trailing edge of the read signal , which is a rising edge , the read edge detect flip-flop 212 will set and force the receive ready flip-flop 202 to clear . Clearing the receiver_^ ready flip-flop 202 clears the receiver 66 and enables the receiver 66 to receive additional data 55 . This action enables the data buffer 82 onto the data bus so that the processor c an proce ss the byte of data .

When the data frame signal 50 drops or goes inactive , it signifies the end of a mes sage trans- mis sion . Since the last two bytes 71 , 72 that are transmitted f rom the transmitter 65 indicate the results /* of the CP.C generator 68, these two bytes 71,72 are fed as normal data to the CRC checker 190. If the data has been correctly received, the output of the CRC checker 190 will be true or a low signal. If the CRC output is low and the data frame signal 50 on line 222 drops, both of which are connected to the CRC error flop 220, the CRC OK output on line 223 will go low. That signal is combined with the data frame signal 50 on line 224 which is low and connected with an NOR gate 227 to generate the data byte acknowledge signal, RDBA on line 230, the return pulse 75, indicating that the data was correctly received. This occurs on the rising edge of the frame signal 50 meaning the data frame signal has ended.

The amount of time that the pulse 75 is on the return line 124 is controlled by the read-back timer 231 and timer control flip-flop 233. The timer control flop

233 sets when the data frame signal 50 on line 222 goes low which enables the read-back timer 231 to start - . counting. This is an active low clear flip-flop, manufacturer's designation 74F74, so it will give a pulse out which is used to set the flip-flop status bit that indicates that the received end of transfer has been detected.

The read-back timer 231 counts four cycles of the 16 megahertz clock 175. When the output goes high, the clear signal is inverted 236 and connected through a NOR gate 237 to clear the timer control flip-flop 233.

If a CRC error occurs, the input to NOR gate 227 is ^" high to prevent a read-back pulse 75 from occurring. This signifies to the transmitter 65 that there is an error. If the read-back pulse 75 is not received within the delay period established by the transmitter 65, the transmitter 65 retransmits the entire data transmission under software control. Each of the signals," the receive end of trans¬ mission, the CP.C OK signal, the received data frame ή signal, and the CRC error signal are connected to the circuitry shown in Figure 5d which are transmit and receive status flip-flops.

Shown on Figure 5d are the transmitter 65 status flip-flops 240-243, latch 245 and buffer 247 and the receiver 66 status flip-flops 250-253, latch 255 and buffer 257. The latches are utilized to synchronize the received events to the processor which -is reading status. The transmit and receive buffers 247,257 are used to buffer the state of the latch 245,255 from the bus. The input signals to the initial transmit and receive status flops 240,241,250,251 correspond to data bit zero of the receive and transmit status registers discussed in connection with Figure 5a. The transmit and receive end of transfer signals are generated by the

PAL 200 on the transmitter side.

The logic gates 270,271 provide interrupt signals. The transmit gates 270 combine the transmit interrupt, end of transfer and interrupt on transmit ready. If any of these conditions exist, bits are enabled to provide an interrupt to the processor. The receiver gates 271 and the DMA interfaces 273,274 operate in the same manner.

Referring now to Figure 6, the N x N distribu- tion matrix and control circuitry can be discussed and understood.

As will be obvious from a review of the schematic, in a preferred embodiment if discrete components are used, the switching matrix 85 is preferably constructed of multiplexers 300. Since a 16 x 16 matrix 85 discussed in conjunction with the block diagram of Figure 3 would geometrically increase the complexity, a 4 x 4 matrix 300 is discussed and disclosed. It will be understood by those skilled in the art, however, that with an appropriate increase in components, any N x N matrix 85 can be constructed and the functions and operation of the switch 30 lend themselves to VLSI circuitry which is a preferred form of the invention but which is not as easily described as discrete components. The majority of the switch matrix 85 is shown in Figure 6a, consisting of twenty dual one of four multiplexers 300 having non-inverting outputs and common select inputs. Each half of the chips is a_-σne of four multiplexer, manufacturer's designation 74LS153, programmed by the control logic so that one of the four inputs is connected to the output. This part of the matrix switches the 10 forward wires to a selected receiver.

The reverse plane or matrix 330 which is the balance of the switch 85 is shown at the top of Figure 6c to provide the reverse acknowledge signal 53.

Referring to Figure 6b, the data frame signal 50 for each of transmitters X0-X3 o _rn lines 334-337 from the four resource boards 20 connected to the transmit side of the switch 30 are connected to the input of the control circuitry.

The switch 30 is controlled by a sequencer 95 operated off a clock 342, 344 which is connected to a timing counter 346 and a demultiplexer 348, manu- facturer's designation 74LS139. This produces a ring counter, a perpetual round-robin to sequentially poll the input transmitters X0-X3. Each of the polling pulses are connected to one of the four input flip-flops 352-355 shown in Figure 6b. The D-flip-flops 352-355 are shut down on reset which only happens on power-up to be sure that everything starts in a known state.

Since a four-by-four switch 40 is disclosed only two bits of address, 00, 01, 10 or 11, are necessary to select a receiver R0-R3. The destination address, which is contained in the first byte of data 55, is latched into the address latch 88 which Zi corresponds to the appropriate receiver R0-R3. The tw bit address 00-11 of the data byte 55 is connected t each of the four latches 352-355. The data frame signal 50 from each transmitter X0-X3 is connected to a dat frame delay line 102 consisting of delay counters 356-359 which is clocked with a two megahertz signal from the oscillator 344. When any counter 356,357,358 or 359 goes active, it sets the connected D-flip-flop 352, 353, 354 or 355 which in turn clocks the connected address latch 362-365. Multiplexers 367,368 are provided to multiplex the address lines in time sync with the sequencer 95.

A buffer 370, manufacturer's designation 74LS367A, is also provided to drive the appropriate multiplexer chips 300. The output of the buffer gives row select signals 393,394 which corresponds to the receiver 66 to receive the data 51 and column select bits 396,397 to identify the transmitter 66.

It should be noted that in the acknowledge chips 330 constituting the reverse plane or the reverse matrix the row select identifies the transmitter and the column select designates the receiver.

The buffer 390 also provides the transmit enable signal and a reset pulse. A strobe signal is also provided from the sequencer 95.

Once the address latches 362-365 capture a destination address, they hold that address until the data frame signal 50 on lines 334-337 rises again for next new data transmission. As will be explained in connection with the arbitration logic 105, no other transmitter 65 can connect to the addressed receiver 66 until the initial data transmission is complete.

Referring now to Figure 6c, the forward latches 402-405 and reverse latches 412-415 and compara- tors 422-425 and -their interconnection with the -multi¬ plexers 300 can be shown and understood. It will be understood that during the connection sequence, the sequencer 95 continuously polls each of the transmitters X0-X3, 65 and makes the appropriate connection of each requesting transmitter X0, XI, X2 and/or X3 to the destination address in the time sequence and window established by the sequencer 95. It should be obvious to those skilled in the art that no two transmitters 65 should contemporaneously talk to a single receiver 66 and, thus, there can be no commonality between rows and columns through the switch 85.

As shown in Figure 6c, a demultiplexer 430, manufacturer's designation 74LS139, is connected to the row select address for the forward plane which is connected to forward latches 402-405 for each of the rows of multiplexers 300. Similarly, a demultiplexer 434 is also connected to the column select for the reverse plane and four reverse latches 412-415 are provided for the reverse plane or matrix to provide the acknowledge handshake signal 53. In other words, if transmitter 1 is connected to receiver 3 in the ten forward planes, receiver 3 will transmit to transmitter 1 in the reverse plane. The demultiplexer 430 in the forward planes will cause a pulse to control the latch 402, 403, 404 or 405 for the destination receiver. For example, if receiver 3 is selected, address select latch 405 will be clocked, as will an associated control multiplexer 451 which is part of the arbitration logic 105. This latch 405 is connected to the receiver 3 multiplexers 301-305 and will connect the output data bus to receiver 3. In addition to the address connection to each latch 402-405 and a demultiplexer 430 input, the receiver enable line 452 is also connected to each latch 402-405.

The flip-flops 352-355 will be active during the period of the connection and when the flip-flops 352-355 go inactive at the end of the transfer, after the delay times 102 times out, the connection will be discontinued and the enable on line 452 will go low. The enable is time shared in the same manner as other components and, consequently, the enable will affect the chosen latch 402, 403, 404 or 405 only during its time slice. The enable line 452 provides the input data to the connection flip-flop, flip-flop four, of the multiplexer control latches 402-405.

Connected to each of the latches 402-405 and to the column select input, is a comparator 422-425 used for arbitration logic 105. The comparator 422-425 output will be true only when the input address is equal to the output address. The comparator 422-425 outputs, which are connected to the control multiplexer 451, are also connected through a NAND gate 460 with the strobe line 462 to indicate its time to latch the switch multiplexers 300 again. If a different transmitter 65 attempts to make a connection with the receiver 66, the multiplexer 451 output will prevent the connection because the comparator output 422-425 will not be true. The comparator 422, 423, 424 or 425, the multiplexer 451 and associated logic 463 will continue to prevent the connection from being made until the original trans¬ mitted data frame signal 50 goes low and the delay timers 102 time out. At this time the connect enable on line 452 will go low thereby setting ^" the enable flip-flop of the latch 402,403,404 or 405 inactive causing the multiplexer enables RO, Rl, R2 or _ R3 on lines 470, 471, 472 or 473 to go high. This turns the multiplexer off and forces the outputs 91 low or inactive, to a quiescent state. It also enables the multiplexers to establish a new connection upon a subsequent request for service. The inputs 88 to the switch 85 are also biased off when inactive by pull down resistors (not shown) so that no errant signals will cause switch connections for channels that have no __^< resource module present.

The construction of a 16 x 16 switch 30 is substantially the same with a four bit input for row and column select and similar timing cycles. Other larger N x N switches can be similarly constructed.

In the manner described a plurality of trans¬ mitting computer system components attached to and through the matrix switch 30 of the instant invention using the above described adapter logics 20 can contemporaneously transmit data to other attached components.

Once a transmitter/receiver connection is established it will remain connected for the duration of the data 51 transmission or until the data frame signal 50 is removed and the delay timer times out and fully accurate data transmissions can occur simultaneously and contemporaneously between different components.

It will be obvious to those skilled in the ar.t upon a review of the foregoing specification and the attached drawings that many and varied modifications and variations both in component design and operation can be achieved using the principals of the invention. All such modifications and variations which come within the scope of the appended claims are within the intendment of the invention. Having described a preferred embodi¬ ment of our invention, we claim:

Claims

1. A distribution matrix switch for interconnecting N computer system signalling devices comprising:

An N x N switch interposed between the N devices; means for connecting each of the devices to the switch for transmission to any of the other devices; means for connecting each of the devices to the switch for receipt of signals from any of the other devices; means for sensing a data transmission from any of the devices; means for determining the address of the receiving device for any transmission from any of the devices; and means for automatically establishing an unique connection between any transmitting devic and the addressed receiving device through the switch for the period of the signal transmission

2. The distribution matrix switch of claim 1 wherei the means for establishing a unique connection through the switch comprises means for contemporaneously establishing a separate, unique connection from any trans¬ mitting device to any receiving device which is not alread receiving a signal transmission from another device.

3. The distribution matrix switch of claim 2 wherei the means for establishing a unique connection comprises means for arbitrating transmission requests for the same receiving device.

4. The distribution matrix switch of claim 1 wherei the switch further comprises means for sequentially pollin each of the devices to determine whether any of the device are attempting to transmit to any of the other devices.

5. The distribution matrix switch of claim 1 wherein the connecting means comprise means for connecting each of the devices for transmission in parallel and for connecting each of the devices for receiving signals in parallel to the switch.

6. The distribution matrix switch of claim 1 wherein the transmitted and received signals comprise data and

-_n handshake signals.

7. The distribution matrix switch of claim 6 wherein the first byte of the data signal comprises the address of the receiving device and wherein the means for establishing a connection comprises means for establishing -^*-5 a unique connection to the receiving device having the address which is contained in the first byte of data.

8. The distribution matrix switch of claim 6 wherei the means for establishing a connection comprises means for establishing a forward connection for data and handshak

20 signals and at least one reverse connection for an acknow¬ ledge handshake signal.

9. The distribution matrix switch of claim 6 wherei the means for establishing a connection comprise means for continuing the connection after the data transmission ²⁵ is complete for receipt of an error detection acknowledge handshake signal.

10. The distribution matrix switch of claim 1 -furthe comprising means for maintaining any of the connection means for transmission off when no data is being trans¬

30 mitted.

11. The distribution switch of claim 1 further comprising means for maintaining any of the connection means for receipt of signals off when no data is being received.

35 12. A resource board having adapter logic for connecting one of a plurality of computing devices through a distribution matrix switch, each device having a unique transmitting address and/or a unique receiving address, for transmission of data to another of the computing devic comprising: means for interfacing the adapter logic to the computing device; means for receiving and storing..data from the transmitting device to be transmitted to any receiving device; means for connecting the data to be trans¬ mitted to the distribution matrix switch; and means for generating at least one handshake signal to be transmitted with the data. 13. The resource board of claim 12 wherein the generating means comprise means for generating a data fram handshake signal to be active for the entire data trans¬ mission.

14. The resource board of claim 12 wherein the generating means comprise means for generating a data byte valid handshake signal for indicating that a data byte is being transmitted .

15. The resource board of claim 12 wherein the resource board further comprises means for receiving at least one handshake signal from the receiving device.

16. The resource board of claim 15 wherein the receiving means comprises means for receiving a data" byte acknowledge handshake signal indicating that the data has been received by a receiving device. 17. The resource board of claim 12 wherein the data being transmitted is processed by an error detection algorithm to assure correctness of the data as transmitted.

18. The resource board of claim 17 wherein the resul of the error detection algorithm is transmitted as the £8 last bytes of data.

19. A resource board having adapter logic for connecting one of a plurality of computing devices to a distribution matrix switch, each device having a unique transmitting address and/or a unique receiving address for the receipt of data from another of the computing devices comprising: means for interfacing the adapter logic to the computing device; means for connecting the adapter board to the distribution matrix switch for the receipt of data from any transmitting device; means for receiving and storing the data received from any transmitting device for the receiving device; and means for receiving at least one handshake signal which is transmitted with the data.

20. The resource board of claim 19 wherein the hand¬ shake receiving means comprise means for receiving a data frame handshake signal which is active for the entire data transmission.

21. The resource board of claim 19 wherein the hand¬ shake receiving means comprise means for receiving data byte valid handshake signal for indicating that a data byte is being received.

22. The resource board of claim 19 wherein the resource board further comprises means for generating at least one handshake signal.

23. The resource board of claim 22 wherein the hand- shake generating comprises means for generating a data byte acknowledge "handshake signal indicating that the data has been received by the receiving device.

24. The resource board of claim 17 wherein the received data is processed with an error correction algorithm to assure the correct receipt of data.

25. The resource board of claim 22 wherein the data being transmitted is first processed through an error correction algorithm and wherein the results of the error correction algorithm are transmitted as data and wherein the resource board further comprises means for evaluating the result of the error detection algorithm as transmitte with the result of the error detection algorithm performe by the means for processing the data to assure that a pro transmission of data occurred.

26. The resource board of claim 21 further comprisi means for generating an additional signal which is trans¬ mitted to the transmitter to indicate the correct receipt of data. 27. A parallel networking system for interconnecting N computer system signalling devices comprising: an N x N matrix switch interposed between the N devices; a plurality of resource boards containing adapter logic, one for each device, each resourc board comprising: a means to interface the adapter logic to the connected device; means for receiving data from the attached device through the interface means means for storing data to be trans¬ mitted; means for connecting the data to be transmitted in parallel to the N x N switch means for generating a data frame sign to be active during data transmission throu the N x N switch; means for generating a data byte valid signal to be active every time a byte of data is transmitted through the N x N switc means for receiving a data byte acknow ledge signal from the resource board connected to the receiving device through the N x N switch; 5 means for connecting each of the data frame signal and the data byte valid signal to the N x N switch; means connected to the resource board from the N x N switch to receive the data 10 byte acknowledge signal; means for processing transmitted data with an error correction algorithm; said data being characterized in that the first byte of data transmitted contains 15 the address of the receiving device and the last bytes of data transmitted containe the result of the error detection algorithm said N x N switch comprising: means for sequentially polling 20 each of the plurality of resource boar to determine whether a data transmissi is to take place; means for decoding the address of the receiver to which the data is 25 directed; means for contemporaneously establishing a separate unique connection between any transmitting device and any receiving device to 30 which data is to be transmitted; means for arbitrating between competing requests for transmission to the same receiving device; the adapter logic of each of said resource 35 boards further comprising: means for receiving data transmitted to it; means for receiving the data frame handshake signal and data byte valid hand¬ shake signal through the switch from the transmitting device; means for generating a data byte ackno ledge signal for each byte of data received means for transmitting the-'data byte acknowledge signal for each byte of data received through the N x N switch to the resource board connected to the transmittin device; means for processing the data received with a error detection algorithm to assure the correct receipt of data; means for comparing the results of the processed error correction algorithm with the last bytes of transmitted data; an means for sending an acknowledge signa through the N x N switch to the transmittin device to indicate the correct receipt of data. 28. A method for transmitting signals from N compute system signalling devices through an N x N matrix switch interposed between the N devices, each of the devices bein connected to the switch for transmission to any of the other devices and each of the devices being connected to the switch for receipt of signals from any of the other devices comprising: sensing a data transmission signal from any of the devices; determining the address of the receiving device for any transmission from any of the devices; and automatically establishing an unique connection between any transmitting device and any receiving device through the switch for the period of the signal transmission.

29. The method of claim 28 wherein the step of establishing a unique connection through the switch comprises contemporaneously establishing a separate unique connection from any transmitting device to any receiving device which is not already receiving a signal--transmission from another device.

30. The method of claim 29 wherein the step of establishing a unique connection comprises arbitrating transmission requests for the same receiving device.

31. The method of claim 28 wherein the method further comprises sequentially polling each of the devices to deter mine whether any of the devices are attempting to transmit to any of the other devices .

32. The method of claim 28 wherein the connecting means comprise means for connecting each of the devices- for transmission in parallel and for connecting each of the devices for receiving signals in parallel to the switch and wherein the method further comprises transmitting all signals in parallel through the switch.

33. The method of claim 28 wherein the transmitted and received signals comprise data and handshake signals and wherein the first byte of the data signal comprises the address of the receiving device and wherein the step of establishing a connection comprises establishing a uniq connection to the receiving device having the address whic is contained in the first byte of data.

34. The method of claim 28 wherein the transmitted and received signals comprise data and handshake signals and wherein the step of establishing a connection comprises establishing a forward connection for data and handshake signals and at least one reverse connection for an acknow- ledge handshake signal .

35. The method of claim 28 wherein the transmitted and received signals comprise data and handshake signals and wherein the step of establishing a connection compris continuing the connection after the data transmission is complete for receipt of an error detection acknowledge handshake signal .

36. The method of claim 28 wherein the method furth comprises the step of turning any of the transmission connecting means off when no data is being transmitted.

37. The method of claim 28 wherein the method furth comprises maintaining any of the receiving connections in an off condition when no data is being received.

38. A method for transmitting signals from a plural of computing devices through a distribution matrix switch, each device having a unique transmitter address and/or a unique receiver address comprising: receiving and storing the data from any computing device to be transmitted for each tra mitter; connecting the data to be transmitted to the distribution matrix switch for transmission to the addressed receiver; and generating at least one handshake signal to be transmitted with the data.

39. The method of claim 38 wherein the step of generating a handshake signal comprises generating" a data frame handshake signal to be active for the entire data transmission . 40. The method of claim 38 wherein the step of generating a handshake signal comprises generating a data byte valid handshake signal for indicating that a data byte is being transmitted.

41. The method of claim 38 wherein the method furthe comprises receiving at least one handshake signal from the receiving device.

42. The method of claim 39 wherein the step of receiving a handshake signal comprises receiving a data byte acknowledge handshake signal indicating that the data has been received by the addressed receiver.

43. The method of claim 38 wherein the method furthe comprises processing the data being transmitted with an error detection algorithm to assure correctness of the data as transmitted.

44. The method of claim 43 wherein the method furthe comprises transmitting the results of the error detection algorithm as the last bytes of data.

45. A method for receiving transmitted signals from one of a plurality of computing devices through a distribu tion matrix switch, each device having a unique transmitte address and/or a unique receiver address comprising: receiving and storing the data received from any transmitter for any receiver; receiving at least one handshake signal which is transmitted with the data; and generating at least one handshake signal indicating that the data has been received by the receiver. 46. The method of claim 45 wherein the step of receiving a handshake signal comprises receiving a data frame handshake signal which is active for the entire data transmission.

47. The method of claim 45 wherein the step of receiving a handshake signal comprises receiving data byte valid handshake signal for indicating that a data byte is being received.

48. The method of claim 45 wherein the step of generating a handshake signal comprises generating a data 2,5 byte acknowledge handshake signal indicating that the data has been received by the receiving device.

49. The method of claim 45 wherein the method further comprises processing the received data with an error - correction algorithm to assure the correct receipt of data.

50. The method of claim 49 wherein the data being transmitted is first processed through an error correction algorithm and wherein the results of the error correction algorithm are transmitted as the last bytes of data and wherein the method further comprises comparing the results of the error detection algorithm as transmitted with the results of the error detection algorithm performed by the means for processing the data to assure that a proper trans¬ mission of data occurred. 51. The method of claim 48 wherein the method further comprises generating an additional signal which is trans¬ mitted to the transmitter to indicate the correct receipt of data.

52. A parallel networking method for interconnecting N computer system signalling devices for data transmission through an N x N matrix switch interposed between the N devices, each of the devices being interfaced with interface means to the switch with a resource board containing adapter logic, said data being characterized in that the first byte of data transmitted contains the address of the receiving device comprising: receiving data from any attached device through the interface means; storing data to be transmitted; connecting the data to be transmitted in parallel to the N x N switch; generating a data frame signal to be active during data transmission through the N x N switch; generating a data byte valid signal to be active every time a byte of data is transmitted through the N x N switch; connecting each of the data frame signal and the data byte valid signal to the N x N switch; 5 processing transmitted data with an error correction algorithm; transmitting the result of the error detection algorithm as the last bytes of data transmitted; 10 sequentially polling each of the plurality of resource boards to determine whether a data transmission is to take place to any receiver; decoding the address of the receiver to which the data is directed; 15 contemporaneously establishing a separate unique connection between any transmitting devic and any receiving device to which data is to be transmitted; arbitrating between competing requests for 20 transmission to the same receiving device; receiving data transmitted from any trans¬ mitter to any receiving device; receiving the data frame handshake signal and data byte valid handshake signal through 25 the switch from the transmitting device; generating a data byte acknowledge signal for each byte of data received; transmitting the data byte acknowledge sign for each byte of data received through the N x N 30 switch to the resource board connected to the transmitting device; processing the data received with an error detection algorithm to assure the correct receip of data; 35 comparing the results of the processed erro correction algorithm with the last bytes of tran mitted data; and sending an acknowledge signal through the N x N switch to the transmitting device to indicate the correct receipt of data.