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EP0296348B1 - Process for etching holes or grooves in n-type silicium - Google Patents

Process for etching holes or grooves in n-type silicium Download PDF

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Publication number
EP0296348B1
EP0296348B1 EP88107530A EP88107530A EP0296348B1 EP 0296348 B1 EP0296348 B1 EP 0296348B1 EP 88107530 A EP88107530 A EP 88107530A EP 88107530 A EP88107530 A EP 88107530A EP 0296348 B1 EP0296348 B1 EP 0296348B1
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EP
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Prior art keywords
etching
manufacture
silicon
adjusted
minutes
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EP88107530A
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German (de)
French (fr)
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EP0296348A1 (en
Inventor
Helmut Dr. Föll
Volker Lehmann
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TDK Electronics AG
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Siemens AG
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/744—Gate-turn-off devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3063—Electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1012—Base regions of thyristors
    • H01L29/102—Cathode base regions of thyristors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures
    • H01L29/7392—Gated diode structures with PN junction gate, e.g. field controlled thyristors (FCTh), static induction thyristors (SITh)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/93—Variable capacitance diodes, e.g. varactors

Definitions

  • the invention relates to a method for producing hole openings or trenches in layers or substrates consisting of n-doped silicon, as are used in the production of semiconductor components, in particular highly integrated semiconductor circuits, by masked etching.
  • Silicon as the most important material in microelectronics requires ever more targeted and special processes for surface structuring.
  • the creation of trenches or holes in the silicon surface is a central technical problem.
  • the object of the invention is to achieve hole geometries and trenches controlled by an etching process in the simplest possible manner, both holes and trenches in silicon for microelectronics (diameter smaller than 1 ⁇ m, 10 ⁇ m deep) and those for the power components. Electronics with any cross sections should be generated. In addition, it should also be possible to produce fine trenches (perforations) for the absorption of dopants in silicon.
  • the object according to the invention is achieved in that an electrolytic etching is carried out in an electrolyte containing hydrofluoric acid with the application of a constant or changing potential according to claim 1.
  • the silicon body can also have an ohmic contact or another Have electrolyte contact (contact for the majority charge carriers).
  • FIG. 4 shows the basic IU characteristic of the hydrofluoric acid-electrolyte-n-silicon contact.
  • the divalent dissolution (I less than I PSL ) of the silicon takes place as an anodic electrode reaction without the formation of an electropolishing surface layer, as occurs in the tetravalent resolution range (I greater than I PSL ), that is to say the entire applied voltage falls over the space charge zone (RLZ).
  • ab P orous S ilicon L ayer; this layer forms in the anodic area in hydrofluoric acid on p and n silicon).
  • an electric current only flows if there are minority charge carriers (holes h+). These can be generated by lighting, so the current is a function of the incident light.
  • n-Si electrode with not too large current densities cause small deviations from the ideally smooth surface to rock, that is to say that a minimal hole or an etching pit bends the electric field of the space charge zone in such a way that all are close h+ are collected from this hole and thus the etching takes place more intensely on the hole bottom.
  • the hole of width D collects charge carriers from the area D + 2d.
  • FIG. 6 Reference number 1 denotes a silicon crystal wafer consisting of n-doped silicon, in whose surface the masking layer is to be used to produce the structures (holes or trenches).
  • This silicon crystal wafer 1 is clamped in a sample holder 2 made of Teflon, which is designed such that it contains the electrolyte 3 consisting of hydrofluoric acid solution in a sealed manner in its interior.
  • the silicon crystal wafer 1 is connected to the positive pole 5 of a voltage source (not shown) via an ohmic contact 4.
  • the silicon crystal wafer 1 is illuminated from the back with light of suitable intensity (see wavy arrow 8). Under these conditions, when the voltage is applied, anodic dissolution takes place on the surface of the silicon crystal wafer 1 which is not covered with the masking layer (not shown). The depth of the etching trenches or holes is predominantly set via the etching time.
  • a mask consisting of silicon nitride, for example, is applied to an n-doped silicon crystal wafer in a first step using conventional technology.
  • the arrangement of the holes predetermined by the mask is now pre-etched with an alkaline etching, for example 10% potassium hydroxide solution for 10 minutes (see FIG. 2).
  • the silicon crystal wafer is clamped in the arrangement shown in FIG. 6 or in an arrangement modified for production purposes.
  • the etching current per hole is 0.1 nA, set by illuminating the back with light, for example 800 nm wavelength (current I constant over time or decreasing depending on the hole shape to be produced).
  • the duration of the etching t is 20 minutes.
  • the n-doped substrate has a doping N n of 1 ohm cm and an orientation in the (100) direction.
  • the etching takes place at room temperature.
  • the pretreatment and aftertreatment in potassium hydroxide solution is carried out as described in the first embodiment; analogous values apply to the concentration of the electrolyte and the lighting.
  • the subsequent doping (see dashed line in Figure 8) is carried out using conventional technology.
  • the doping N n is in the range between 1 and 100 ohm cm.
  • the etching in potassium hydroxide solution is intensified in order to connect the individual holes specified by the mask to form a closed trench. This is done either by a longer etching time and / or by higher concentrations and / or by a higher temperature of the KOH solution.
  • the doping N n is in the range between 1 and 100 ohm cm. Minority carriers present in the p-area are cleared out by the etched and possibly metallized channels.
  • A, K and G denote the anode, cathode and gate of the thyristors.
  • the same parameters apply as described in the exemplary embodiments 1 to 4, with the exception of:
  • the etching current I is increased by a factor of 2 to 10 in the range from 1 to 100 nA, as a result of which the hole expansion is achieved.
  • G denotes the gate connections.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Weting (AREA)

Description

Die Erfindung betrifft ein Verfahren zum Erzeugen von Lochöffnungen oder Gräben in aus n-dotiertem Silizium bestehenden Schichten oder Substraten, wie sie bei der Herstellung von Halbleiterbauelementen, insbesondere hochintegrierten Halbleiterschaltungen, verwendet werden, durch maskiertes Einätzen.The invention relates to a method for producing hole openings or trenches in layers or substrates consisting of n-doped silicon, as are used in the production of semiconductor components, in particular highly integrated semiconductor circuits, by masked etching.

Silizium als wichtigster Werkstoff der Mikroelektronik erfordert immer gezieltere und speziellere Verfahren zur Oberflächenstrukturierung. Das Erzeugen von Gräben bzw. Löchern in der Siliziumoberfläche ist hierbei ein zentrales technisches Problem.Silicon as the most important material in microelectronics requires ever more targeted and special processes for surface structuring. The creation of trenches or holes in the silicon surface is a central technical problem.

Bisher werden chemische Ätzverfahren oder Plasmaätzverfahren zur Erzeugung von loch- oder grabenförmigen Strukturen verwendet. Dabei treten folgende Schwierigkeiten auf:

  • a) Beim isotropen chemischen Ätzen (sauer) treten Unterätzungen (10) auf, die die möglichen Ätzgeometrien sehr beschränken (siehe Figur 1).
  • b) Beim anisotropen chemischen Ätzen (alkalisch) ist durch die Kristallflächen (111) und (100) die Anzahl der realisierbaren Ätzgeometrien stark eingeschränkt (siehe Figur 2).
  • c) Beim Plasmaätzen, wie es beispielsweise zur Realisierung der Grabenzellen von Mbit-Speichern in einem Bericht von Morie et. al. aus dem IEEE Electron Device Letters, Vol.-EDL-4, Nr. 11 (November 1983), auf den Seiten 411 bis 414 zu entnehmen ist, sind Abmessungen unter 1 µm, sowie Tiefe/Breite-Verhältnisse T/B größer 10 bei Löchern nur sehr schwierig erreichbar (siehe Figur 3). Der rechtwinklige Grabenquerschnitt ist bei Morie vom Gasdruck des Reaktionsgases (Trifluorbrommethan) stark abhängig.
So far, chemical etching processes or plasma etching processes have been used to produce perforated or trench-shaped structures. The following difficulties arise:
  • a) In the case of isotropic chemical etching (acidic), there are undercuts (10) which limit the possible etching geometries very much (see FIG. 1).
  • b) In the case of anisotropic chemical etching (alkaline), the number of etching geometries that can be achieved is severely limited by the crystal surfaces (111) and (100) (see FIG. 2).
  • c) In plasma etching, as is the case, for example, for realizing the trench cells of Mbit memories in a report by Morie et. al. From IEEE Electron Device Letters, Vol.-EDL-4, No. 11 (November 1983), on pages 411 to 414, dimensions below 1 µm and depth / width ratios T / B greater than 10 are shown Holes are very difficult to reach (see Figure 3). For Morie, the right-angled trench cross-section is the gas pressure of the reaction gas (trifluorobromomethane) heavily dependent.

Durch die Erfindung soll die Aufgabe gelöst werden, Lochgeometrien und Gräben kontrolliert durch ein Ätzverfahren in möglichst einfacher Weise herzustellen, wobei sowohl Löcher und Gräben im Silizium für die Mikroelektronik (Durchmesser kleiner 1 µm, 10 µm tief), als auch solche für die Leistungsbauelemente-Elektronik mit beliebigen Querschnitten erzeugt werden sollen. Außerdem soll es auch möglich sein, feine Gräben (Perforationen) für die Aufnahme von Dotierstoffen im Silizium zu erzeugen.The object of the invention is to achieve hole geometries and trenches controlled by an etching process in the simplest possible manner, both holes and trenches in silicon for microelectronics (diameter smaller than 1 µm, 10 µm deep) and those for the power components. Electronics with any cross sections should be generated. In addition, it should also be possible to produce fine trenches (perforations) for the absorption of dopants in silicon.

Die Lösung der erfindungsgemäßen Aufgabe erfolgt dadurch, daß eine elektrolytische Ätzung in einem flußsäurehaltigen Elektrolyten unter Anlegung eines konstanten oder sich zeitlich ändernden Potentials durchgeführt wird gemäß Anspruch 1.The object according to the invention is achieved in that an electrolytic etching is carried out in an electrolyte containing hydrofluoric acid with the application of a constant or changing potential according to claim 1.

Es liegt im Rahmen der Erfindung, die Elektrolyse durch Bleuchtung des Siliziumkörpers von der Rückseite her zu injizieren und die Beleuchtung konstant oder zeitlich variiert aufrechtzuerhalten, um den Ätzstrom durch die Bildung von Minoritätsladungsträgern zu steuern.It is within the scope of the invention to inject the electrolysis by illuminating the silicon body from the rear and to maintain the illumination constant or varying in time in order to control the etching current through the formation of minority charge carriers.

Es hat sich außerdem als vorteilhaft erwiesen, zusätzlich vor und/oder nach der elektrolytischen Ätzung eine chemische Ätzung vorzugsweise in Kalilauge durchzuführen, wobei ein Netzmittel zugesetzt werden kann.It has also proven advantageous to additionally carry out chemical etching, preferably in potassium hydroxide solution, before and / or after the electrolytic etching, in which case a wetting agent can be added.

Zusätzlich kann der Siliziumkörper außer dem zu ätzenden Elektrolytkontakt einen ohmschen Kontakt oder einen weiteren Elektrolytkontakt (Kontakt für die Majoritätsladungsträger) aufweisen.In addition to the electrolyte contact to be etched, the silicon body can also have an ohmic contact or another Have electrolyte contact (contact for the majority charge carriers).

Weitere Ausgestaltungen der Erfindung ergeben sich aus den Unteransprüchen.Further refinements of the invention result from the subclaims.

Im folgenden soll auf die Physik des erfindungsgemäßen Verfahrens am Beispiel des elektrolytischen Löcherätzens im n-dotierten Silizium noch näher eingegangen werden.In the following, the physics of the method according to the invention will be discussed in more detail using the example of electrolytic hole etching in n-doped silicon.

Die Figur 4 zeigt die prinzipielle I-U-Kennlinie des Flußsäure-Elektrolyt-n-Silizium-Kontaktes. Im schraffierten Gebiet erfolgt als anodische Elektrodenreaktion die divalente Auflösung (I kleiner IPSL) des Siliziums ohne Bildung einer elektropolierenden Oberflächenschicht, wie sie im tetravalenten Auflösungsbereich (I größer IPSL) auftritt, das heißt die gesamte angelegte Spannung fällt über der Raumladungszone (RLZ) ab (PSL bedeutet Porous Silicon Layer; diese Schicht bildet sich im anodischen Bereich in Flußsäure auf p- und n-Silizium). Ein elektrischer Strom fließt jedoch nur, wenn Minoritätsladungsträger (Löcher h⁺) vorhanden sind. Diese können durch Beleuchtung erzeugt werden, der Strom ist damit eine Funktion des einfallenden Lichtes. Diese speziellen Eigenschaften der n-Si-Elektrode bei nicht zu großen Stromdichten führt dazu, daß kleine Abweichungen von der ideal glatten Oberfläche sich aufschaukeln, das heißt, ein minimales Loch bzw. eine Ätzgrube verbiegt das elektrische Feld der Raumladungszone gerade so, daß alle nahen h⁺ von diesem Loch gesammelt werden und damit die Ätzung verstärkt am Lochboden erfolgt. Wie aus Figur 5 ersichtlich ist, sammelt das Loch der Breite D Ladungsträger aus dem Bereich D + 2d. Nach einiger Zeit bildet sich durch den beschriebenen Prozeß ein System feiner, eng benachbarter Löcher. Diese mikroskopische Wabenoberfläche absorbiert Licht sehr stark, das heißt, ist makroskopisch tief schwarz.FIG. 4 shows the basic IU characteristic of the hydrofluoric acid-electrolyte-n-silicon contact. In the shaded area, the divalent dissolution (I less than I PSL ) of the silicon takes place as an anodic electrode reaction without the formation of an electropolishing surface layer, as occurs in the tetravalent resolution range (I greater than I PSL ), that is to say the entire applied voltage falls over the space charge zone (RLZ). ab (PSL means P orous S ilicon L ayer; this layer forms in the anodic area in hydrofluoric acid on p and n silicon). However, an electric current only flows if there are minority charge carriers (holes h⁺). These can be generated by lighting, so the current is a function of the incident light. These special properties of the n-Si electrode with not too large current densities cause small deviations from the ideally smooth surface to rock, that is to say that a minimal hole or an etching pit bends the electric field of the space charge zone in such a way that all are close h⁺ are collected from this hole and thus the etching takes place more intensely on the hole bottom. As can be seen from FIG. 5, the hole of width D collects charge carriers from the area D + 2d. After some time, the process described creates a system of fine, closely adjacent holes. This microscopic honeycomb surface absorbs light very strongly, that is, it is macroscopically deep black.

Durch eine geeignete Maske und einer Vorätzung mit zum Beispiel Kalilauge können die erwähnten kleinen Abweichungen vorgegeben werden und damit die Löcher lokalisiert werden. Ein einzelnes Loch wird durch die spezielle Form der Raumladungszone sich verzweigen und so eine baumartige Lochstruktur bilden, während ein gleichmäßiges Muster von Löchern durch gegenseitige Beeinflussung zu einer streng vertikalen Wachstumsrichtung führt. Die Form und Abmessung der Löcher ist stark variierbar und von folgenden Parametern abhängig:

  • 1. Die Lochanordnung (Maske) bestimmt über die Wirkung auf die Raumladungszone stark die Geometrie der Löcher (Verzweigung oder Linearität).
  • 2. Die Vorätzung mit Kalilauge verbessert nur die durch die Maske vorgegebenen kleinen Abweichungen von der ideal glatten Oberfläche (Keim) und wirkt sich nur auf die Form des oberen Lochrandes aus.
  • 3. Das angelegte Potential zwischen Silizium und Referenzelektrode (Spannung) bestimmt das elektrische Feld in der Raumladungszone und damit die Wandrauhigkeit der Löcher (bei Spannungen im Bereich der Durchbruchfeldstärke sind die Löcher spitz und schmal und die Lochwand ist stark durch feine Kanäle (Spitzenentladungen) gestört).
  • 4. Der Ätzstrom durch die Probenoberfläche ist eine Funktion des einfallenden Liches; er bestimmt hauptsächlich die Lochbreite, hat aber auch Einfluß auf den Durchbruchmechanismus.
  • 5. Die Lochtiefe ist näherungsweise proportional zur Ätzdauer.
  • 6. Die Dotierung des Substrats bestimmt die Ausdehnung und das Feld in der Raumladungszone. Aus Scaling-Regeln läßt sich ableiten, daß sich bei Vervierfachung der Dotierung die geometrischen Abmessungen der Löcher um den Faktor 2 vergrößern.
  • 7. Die Einflüsse der Flußsäure-Konzentration und der Temperatur sind noch nicht eingehend untersucht, werden jedoch als eher gering eingeschätzt.
  • 8. Eine Nachätzung, zum Beispiel in Kalilauge, dient einmal zur Entfernung der sich prozeßbedingt bildenden porösen Siliziumschicht (= PSL in Figur 4), oder zum anderen, um feinstrukturierte Kanäle zu gröberen Strukturen zum Beispiel zu Gräben zu verbinden.
Using a suitable mask and pre-etching with, for example, potassium hydroxide solution, the small deviations mentioned can be specified and the holes can thus be localized. A single hole will branch out due to the special shape of the space charge zone and thus form a tree-like hole structure, while a uniform pattern of holes through interaction leads to a strictly vertical direction of growth. The shape and dimension of the holes can be varied widely and depends on the following parameters:
  • 1. The hole arrangement (mask) strongly determines the geometry of the holes (branching or linearity) via the effect on the space charge zone.
  • 2. The pre-etching with potassium hydroxide solution only improves the small deviations from the ideally smooth surface (germ) specified by the mask and only affects the shape of the upper edge of the hole.
  • 3. The potential applied between silicon and reference electrode (voltage) determines the electric field in the space charge zone and thus the wall roughness of the holes (at voltages in the range of the breakdown field strength, the holes are pointed and narrow and the hole wall is strongly disturbed by fine channels (peak discharges) ).
  • 4. The etch current through the sample surface is a function of the incident light; it mainly determines the hole width, but also has an influence on the breakthrough mechanism.
  • 5. The depth of the hole is approximately proportional to the etching time.
  • 6. The doping of the substrate determines the extent and the field in the space charge zone. It can be derived from scaling rules that the geometrical dimensions of the holes increase by a factor of 2 when the doping is quadrupled.
  • 7. The influences of the hydrofluoric acid concentration and the temperature have not yet been thoroughly investigated, but are estimated to be rather minor.
  • 8. An etching, for example in potassium hydroxide solution, serves once to remove the porous silicon layer which is formed as a result of the process (= PSL in FIG. 4), or on the other hand, in order to connect finely structured channels to coarser structures, for example to form trenches.

Weitere Einzelheiten der Erfindung insbesondere ihre Anwendung werden anhand von fünf Ausführungsbeispielen und der Figuren 6 bis 11 im folgenden noch näher beschrieben.Further details of the invention, in particular its application, are described in more detail below with reference to five exemplary embodiments and FIGS. 6 to 11.

Dabei zeigt

die Figur 6
schematisch den Ätzprozeß in einer Elektrolysierzelle, wobei im Schnittbild ein Probenhalter zur Durchführung der elektrolytischen Ätzung abgebildet ist.
In den Figuren 7 bis 11
sind Schnittbilder durch die nach dem Ätzen erhaltenen Strukturen dargestellt.
It shows
the figure 6
schematically the etching process in an electrolysis cell, a sample holder for performing the electrolytic etching being shown in the sectional view.
In Figures 7 to 11
are sectional views through the structures obtained after the etching.

Figur 6: Mit dem Bezugszeichen 1 ist eine aus n-dotiertem Silizium bestehende Siliziumkristallscheibe bezeichnet, in deren mit einer Maskierschicht versehenen Oberfläche die Strukturen (Löcher oder Gräben) erzeugt werden sollen. Diese Siliziumkristallscheibe 1 ist in einem aus Teflon bestehenden Probenhalter 2 eingespannt, der so ausgebildet ist, daß er in seinem Inneren den aus Flußsäurelösung bestehenden Elektrolyten 3 dicht verschlossen enthält. Über einen ohmschen Kontakt 4 wird die Siliziumkristallscheibe 1 mit dem positiven Pol 5 einer Spannungsquelle (nicht abgebildet) verbunden. Die Gegenelektrode 6 (negativer Pol 7 = Kathode) besteht aus einem gegenüber Flußsäure resistenten Material, zum Beispiel aus Platin. Um die benötigte Stromdichte zu erreichen, wird die Siliziumkristallscheibe 1 mit Licht geeigneter Intensität (siehe gewellter Pfeil 8) von der Rückseite her beleuchtet. Unter diesen Bedingungen erfolgt bei angelegter Spannung anodische Auflösung an den nicht mit der Maskierschicht (nicht dargestellt) bedeckten Oberfläche der Siliziumkristallscheibe 1. Die Tiefe der Ätzgräben oder -löcher wird vorwiegend über die Ätzzeit eingestellt.FIG. 6: Reference number 1 denotes a silicon crystal wafer consisting of n-doped silicon, in whose surface the masking layer is to be used to produce the structures (holes or trenches). This silicon crystal wafer 1 is clamped in a sample holder 2 made of Teflon, which is designed such that it contains the electrolyte 3 consisting of hydrofluoric acid solution in a sealed manner in its interior. The silicon crystal wafer 1 is connected to the positive pole 5 of a voltage source (not shown) via an ohmic contact 4. The counter electrode 6 (negative pole 7 = cathode) consists of a material which is resistant to hydrofluoric acid, for example of platinum. In order to achieve the required current density, the silicon crystal wafer 1 is illuminated from the back with light of suitable intensity (see wavy arrow 8). Under these conditions, when the voltage is applied, anodic dissolution takes place on the surface of the silicon crystal wafer 1 which is not covered with the masking layer (not shown). The depth of the etching trenches or holes is predominantly set via the etching time.

Erstes Ausführungsbeispiel:First embodiment:

Herstellung von Löchern in Speicherbausteinen wie zum Beispiel Trenchzellen (siehe Figur 7).Production of holes in memory chips such as trench cells (see Figure 7).

Es sollen Löcher in n-Silizium mit 1 µm Durchmesser und 10 µm Tiefe hergestellt werden, die zur Aufnahme des Varaktors oder des Varaktors und Auswahltransistors eines DRAMs (= dynamic random access memory) dienen. Dazu wird in einem ersten Arbeitsschritt in konventioneller Technik eine zum Beispiel aus Siliziumnitrid bestehende Maske auf einer n-dotierten Siliziumkristallscheibe aufgebracht. Die durch die Maske vorgegebene Anordnung der Löcher wird nun mit einer alkalischen Ätze, zum Beispiel 10 %iger Kalilauge 10 Minuten vorgeätzt (siehe Figur 2). Im weiteren Verlauf wird die Siliziumkristallscheibe in der in Figur 6 dargestellten oder einer für Produktionszwecke modifizierten Anordnung eingespannt.Holes are to be made in n-silicon with a diameter of 1 µm and a depth of 10 µm, which are used to hold the varactor or the varactor and selection transistor of a DRAM (= dynamic random access memory). For this purpose, a mask consisting of silicon nitride, for example, is applied to an n-doped silicon crystal wafer in a first step using conventional technology. The arrangement of the holes predetermined by the mask is now pre-etched with an alkaline etching, for example 10% potassium hydroxide solution for 10 minutes (see FIG. 2). In the further course, the silicon crystal wafer is clamped in the arrangement shown in FIG. 6 or in an arrangement modified for production purposes.

Die elektrolytische Ätzung in einer Flußsäurelösung (2,5 Gewichtsprozent), die mit einem Netzmittel auf Formaldehydbasis (MirsaolR, 3 Tropfen pro Liter) versetzt ist, erfolgt nun unter folgenden Parametern (die in den folgenden Ausführungsbeispielen genannten Parameter sind nur grobe Richtwerte, die je nach Anwendung optimiert und zeitlich variiert werden müssen):The electrolytic etching in a hydrofluoric acid solution (2.5 percent by weight), which is mixed with a formaldehyde-based wetting agent (Mirsaol R , 3 drops per liter), is now carried out under the following parameters (the parameters mentioned in the following exemplary embodiments are only rough guide values that must be optimized and varied in time depending on the application):

Das Potential zwischen Referenzelektrode und ohmschem Probenkontakt wird auf U = 1V (positiver Pol an Probe) eingestellt.The potential between the reference electrode and the ohmic sample contact is set to U = 1V (positive pole on sample).

Der Ätzstrom pro Loch beträgt 0,1 nA, eingestellt durch Beleuchtung der Rückseite mit Licht, zum Beispiel 800 nm Wellenlänge, (Strom I zeitlich konstant oder abnehmend je nach zu produzierender Lochform).The etching current per hole is 0.1 nA, set by illuminating the back with light, for example 800 nm wavelength (current I constant over time or decreasing depending on the hole shape to be produced).

Die Dauer der Ätzung t beträgt 20 Minuten. Das n-dotierte Substrat weist eine Dotierung Nn von 1 Ohm cm und eine Orientierung in (100)-Richtung auf.The duration of the etching t is 20 minutes. The n-doped substrate has a doping N n of 1 ohm cm and an orientation in the (100) direction.

Die Ätzung erfolgt bei Raumtemperatur.The etching takes place at room temperature.

Abschließend erfolgt eine Nachätzung von 10 Minuten in 1 %iger Kalilauge zur Entfernung der beim Ätzen sich bildenden porösen Siliziumschicht (in Figur 4 als PSL bezeichnet).Finally, there is an after-etching of 10 minutes in 1% potassium hydroxide solution to remove the porous silicon layer formed during the etching (referred to as PSL in FIG. 4).

Zweites Ausführungsbeispiel:Second embodiment:

Herstellung von tiefen, vertikalen Dotierungen (eventuell durch die ganze Siliziumkristallscheibendicke) bei geringer horizontaler Dotiertiefe (siehe Figur 8), sowie Herstellung großflächiger Kondensatoren oder pn-Übergänge (zum Beispiel für steuerbare Kondensatoren (Varicaps) großer Kapazität) in kleinem Volumen.Production of deep, vertical doping (possibly through the entire silicon crystal wafer thickness) with a low horizontal doping depth (see FIG. 8), as well as production of large-area capacitors or pn junctions (for example for controllable capacitors (varicaps) of large capacitance) in a small volume.

Die Vor- und Nachbehandlung in Kalilauge erfolgt wie im ersten Ausführungsbeispiel beschrieben; für die Konzentration des Elektrolyten und die Beleuchtung gelten analoge Werte.The pretreatment and aftertreatment in potassium hydroxide solution is carried out as described in the first embodiment; analogous values apply to the concentration of the electrolyte and the lighting.

Das Potential zwischen Referenzelektrode und ohmschem Probenkontakt wird auf U = 2V, der Ätzstrom I auf 1 nA, die Ätzzeit t auf 100 Minuten und die Dotierung auf Nn auf einen Bereich von 0,1 bis 1 Ohm cm eingestellt.The potential between the reference electrode and the ohmic sample contact is set to U = 2V, the etching current I to 1 nA, the etching time t to 100 minutes and the doping to N n to a range from 0.1 to 1 ohm cm.

Die anschließende Dotierung (siehe strichlierte Linie in Figur 8) erfolgt mit konventioneller Technik.The subsequent doping (see dashed line in Figure 8) is carried out using conventional technology.

Drittes Ausführungsbeispiel:Third embodiment:

Herstellung von tiefen, schmalen Gräben zur elektrischen Isolation von Bereichen A und B (siehe Figur 9) in einem Si-Substrat.Production of deep, narrow trenches for the electrical insulation of areas A and B (see FIG. 9) in a Si substrate.

Es gelten die gleichen Parameter wie bei den Ausführungsbeispielen 1 und 2 beschrieben, mit Ausnahme von:The same parameters apply as described in exemplary embodiments 1 and 2, with the exception of:

Das Potential zwischen Referenzelektrode und ohmschen Probenkontakt wird auf U = 2 bis 20V, der Ätzstrom I auf 1 nA und die Ätzzeit t auf 100 Minuten eingestellt. Die Dotierung Nn liegt im Bereich zwischen 1 bis 100 Ohm cm.The potential between the reference electrode and ohmic sample contact is set to U = 2 to 20V, the etching current I to 1 nA and the etching time t to 100 minutes. The doping N n is in the range between 1 and 100 ohm cm.

Die Nachätzung in Kalilauge wird verstärkt, um die einzelnen durch die Maske vorgegebenen Löcher zu einem geschlossenen Graben zu verbinden. Dies erfolgt entweder durch längere Ätzzeit und/oder durch höhere Konzentrationen und/oder durch höhere Temperatur der KOH-Lösung.The etching in potassium hydroxide solution is intensified in order to connect the individual holes specified by the mask to form a closed trench. This is done either by a longer etching time and / or by higher concentrations and / or by a higher temperature of the KOH solution.

Viertes Ausführungsbeispiel:Fourth embodiment:

Kontaktierung tiefer liegender Schichten, zum Beispiel zum schnellen Ausräumen von Ladungsträgern in abschaltbaren (GTO = gate turn off)-Thyristoren (siehe Figur 10).Contacting of deeper layers, for example for the rapid removal of charge carriers in switchable (GTO = gate turn off) thyristors (see Figure 10).

Es gelten die gleichen Parameter wie bei den Ausführungsbeispielen 1 bis 3 mit Ausnahme von:The same parameters apply as in working examples 1 to 3, with the exception of:

Das Potential zwischen Referenzelektrode und ohmschem Probenkontakt wird auf U = 2V, der Ätzstrom I auf 1 bis 100 nA und die Ätzzeit t auf 100 Minuten eingestellt. Die Dotierung Nn liegt im Bereich zwischen 1 bis 100 Ohm cm. Im p-Gebiet vorhandene Minoritätsladungsträger werden durch die geätzten und eventuell metallisierten Kanäle ausgeräumt.The potential between the reference electrode and the ohmic sample contact is set to U = 2V, the etching current I to 1 to 100 nA and the etching time t to 100 minutes. The doping N n is in the range between 1 and 100 ohm cm. Minority carriers present in the p-area are cleared out by the etched and possibly metallized channels.

Mit den Buchstaben A, K und G sind die Anode, Kathode und das Gate der Thyristoren bezeichnet.The letters A, K and G denote the anode, cathode and gate of the thyristors.

Fünftes Ausführungsbeispiel:Fifth embodiment:

Herstellung spannungsgesteuerter Thyristoren (siehe Figur 11).Production of voltage controlled thyristors (see Figure 11).

Es gelten die gleichen Parameter wie bei den Ausführungsbeispielen 1 bis 4 beschrieben mit Ausnahme von: Das Potential zwischen Referenzelektrode und ohmschen Kontakt wird auf U = 2V, die Ätzzeit auf 100 Minuten und die Dotierung Nn auf einen Bereich zwischen 10 bis 100 Ohm cm eingestellt. Nach zwei Drittel der Ätzzeit erfolgt eine Erhöhung des Ätzstromes I im Bereich von 1 bis 100 nA um den Faktor 2 bis 10, wodurch die Lochaufweitung erreicht wird.The same parameters apply as described in the exemplary embodiments 1 to 4, with the exception of: The potential between the reference electrode and the ohmic contact is set to U = 2V, the etching time to 100 minutes and the doping N n to a range between 10 to 100 Ohm cm . After two thirds of the etching time, the etching current I is increased by a factor of 2 to 10 in the range from 1 to 100 nA, as a result of which the hole expansion is achieved.

Durch die spannungsabhängige Vergrößerung der Raumladungszone um die Löcher wird der Strom zwischen der Anode A und Kathode K des Bauelements gesteuert. Mit G sind die Gateanschlüsse bezeichnet.Due to the voltage-dependent enlargement of the space charge zone the current between the anode A and cathode K of the component is controlled around the holes. G denotes the gate connections.

Claims (22)

  1. Method of producing hole apertures or trenches in layers or substrates which comprise n-doped silicon and are used to manufacture semiconductor components, in particular LSI semiconductor circuits, by preferably masked etching, in which an electrolytic etching is carried out in an electrolyte (3) containing hydrofluoric acid by applying a constant potential or a potential which varies with time, the layer comprising silicon or the substrate (1) being connected as positively polarised electrode (5) of an electrolysis cell, and in which minority charge carriers necessary for the injection of the electrolysis are produced in the silicon and the etching is first carried out at small deviations from the ideally flat surface of the silicon at not unduly high current densities in the divalent dissolution region of silicon and is intensified at those points, and a system of fine holes is formed.
  2. Method according to Claim 1, characterised in that the small deviations are provided by an etching mask.
  3. Method according to Claim 2, characterised in that a patterned silicon nitride layer is used as etching mask.
  4. Method according to one of Claims 1 to 3, characterised in that a chemical etching, preferably in alkali hydroxide solution, is additionally carried out before and/or after the electrolytic etching.
  5. Method according to one of Claims 1 to 4, characterised in that a wetting agent is added to the electrolyte (3).
  6. Method according to Claim 5, characterised in that a wetting agent based on formaldehyde is used.
  7. Method according to one of Claims 1 to 6, characterised in that the electrolysis is injected by illuminating (8) the silicon body (1) from the back.
  8. Method according to Claim 7, characterised in that the illumination (8) is maintained as constant or varying with time in order to control the etching current.
  9. Method according to one of Claims 1 to 8, characterised in that the hydrofluoric acid concentration in the electrolyte (3) is adjusted to approximately 2.5% by weight.
  10. Method according to one of Claims 1 to 9, characterised in that during the etching, a further contact (4) in addition to the electrolyte contact (5) is used for the majority charge carriers.
  11. Method according to Claim 10, characterised in that an ohmic contact is used as contact (4).
  12. Method according to one of Claims 1 to 11, characterised in that to manufacture holes having a diameter of approximately 1 µm and a depth of approximately 10 µm in an n-doped silicon substrate in the region of 1 ohm · cm, the etching current is adjusted for each hole to 0.1 nA, the voltage to 1 V and the etching time to 20 minutes.
  13. Method according to one of Claims 1 to 11, characterised in that, to manufacture fine-pored trenches which receive dopant and to manufacture large-area capacitors or p-n junctions in a small volume in the n-doped silicon substrate in the range from 0.1 to 1.0 ohm · cm, the etching current is adjusted to 1 nA, the voltage to 2 V and the etching time to 100 minutes.
  14. Method according to one of Claims 1 to 11, characterised in that, to manufacture trenches in the n-doped silicon substrate in the range from 1 to 100 ohm · cm having a trench diameter in the region of 5 µm and a depth of approximately 20 µm for the reception of insulating material, the etching current is adjusted to 1 nA, the voltage is adjusted in the range from 2 to 20 V and the etching time is adjusted to 100 minutes.
  15. Method according to one of Claims 4 to 14, characterised in that the afteretching is carried out in 1 to 10%-strength by weight potassium hydroxide solution with an etching time of 10 minutes.
  16. Method according to one of Claims 4 to 15, characterised in that the preliminary etching is carried out in 10%-strength by weight potassium hydroxide solution with an etching time of 10 minutes.
  17. Application of the method according to at least one of Claims 1 to 16 for the manufacture of trenches for the reception of trench-cell capacitors (trench cells) for memory modules in the sub-µm region.
  18. Application of the method according to at least one of Claims 1 to 16 for the manufacture of insulating trenches for LSI semiconductor circuits.
  19. Application of the method according to at least one of Claims 1 to 16 for the manufacture of controllable capacitors (varicaps) having high capacitance.
  20. Application of the method according to at least one of Claims 1 to 16 for the manufacture of vias in deeply situated layers in silicon semiconductor substrates such as those used, in particular, in turn-off thyristors, the etching current being adjusted to a range from 1 to 100 nA, the voltage to 2 V and the etching time to 100 minutes.
  21. Application of the method according to Claim 20 for the manufacture of voltage-controlled thyristors, the etching current being increased by a factor of 2 to 10 after two thirds of the etching time for the purpose of hole enlargement.
  22. Application of the method according to at least one of Claims 1 to 16 for the manufacture of large-area capacitors in a small volume.
EP88107530A 1987-05-27 1988-05-10 Process for etching holes or grooves in n-type silicium Expired - Lifetime EP0296348B1 (en)

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DE10117363A1 (en) * 2001-04-06 2002-10-17 Infineon Technologies Ag Production of a porous silicon dioxide disk comprises oxidizing a porous silicon disk having a number of macroscopic pores extending between the upper and lower sides of the plate and having a macroscopic pore diameter
DE102005046711B4 (en) * 2005-09-29 2007-12-27 Infineon Technologies Austria Ag Method of fabricating a vertical thin-film MOS semiconductor device with deep vertical sections
DE102008012479B3 (en) * 2008-03-04 2009-05-07 Christian-Albrechts-Universität Zu Kiel Electrochemical etching of macropores in n-type silicon wafers under illumination of backside of the wafer using an aqueous electrolyte, where the electrolyte is an aqueous acetic acid solution of a composition with hydrogen fluoride

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JPS63310122A (en) 1988-12-19
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EP0296348A1 (en) 1988-12-28
US4874484A (en) 1989-10-17

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