EP0131479B1 - Method and device for controlling an a.c. plasma panel - Google Patents

Description

The present invention relates to a method for controlling an alternative type plasma panel as well as a device for its implementation.

A plasma panel is a device making it possible to visualize characters, figures, curves, that is to say two-dimensional images obtained by combination of zones or "points" of a surface, made luminous by commands appropriate. Such devices are well known to those skilled in the art and are described in particular in an article which appeared in the "THOMSON-CSF Technical Review June 1978, volume 10, n ° 2 pages 249 to 275.

More specifically, a plasma panel is presented as the juxtaposition of a large number of cells arranged in matrix form, each cell being constituted by the gas space located at the intersection of two electrodes belonging to two networks of electrodes orthogonal and being subjected to control signals constituted by the difference of the voltages applied to the two electrodes between which it is located.

Three types of control signals are generally used in plasma panels, namely the registration signals which cause the cells to light up, the erasure signals which extinguish the cells and the maintenance signals which preserve the cells. in their initial state, either the off state or the on state.

However, unlike the maintenance signals which are applied to all the electrodes of the panel to ensure the visualization of the information entered, the recording and erasing signals are selective signals which must not cause the recording and erasing only for the selected cells. Thus, any cell xy is registered or erased only if its two electrodes x and y receive adequate voltages Vx and Vy which make it possible to obtain at the terminals of this cell and of it alone the signal of registration or erasure.

Consequently, the control electronics must include circuits making it possible to selectively apply to the electrodes the voltages necessary for the operation of the panel.

Various circuits for controlling plasma panels of the alternative type have been described in the prior art. We know in particular by the article published by Texas Instruments, in November 1980, Bulletin SCA-204 and entitled "AC Plasma Display as well as by French patent application n ° 81.19941 in the name of THOMSON-CSF of the integrated circuits which make it possible to control plasma panels of the alternative type.

• - une partie logique basse tension définissant le signal à exécuter, sa durée et les électrodes du panneau sur lesquelles le signal est appliqué;
• - une interface basse tension - haute tension qui est commandée par la partie logique, cette interface permettant d'appliquer aux électrodes du panneau des signaux d'amplitude et de durée variables selon l'ordre à exécuter.

These integrated circuits mainly include:

• - a low voltage logic part defining the signal to be executed, its duration and the panel electrodes on which the signal is applied;
• - a low voltage - high voltage interface which is controlled by the logic part, this interface making it possible to apply signals to the panel electrodes of amplitude and duration varying according to the order to be executed.

The logic part essentially consists of serial / parallel shift registers and a decoding and validation system. Therefore, the data or logical addresses designating the active and non-active electrodes are entered in series in the shift registers and are found in parallel on the outputs of the registers which respectively correspond to the electrodes of the plasma panel. An order defining the recording or erasing signal to be applied to the active electrodes then validates the parallel outputs of the registers towards the low voltage - high voltage interface.

• - un mode surimpression qui permet l'inscription ou l'effacement d'un ou plusieurs points sans modification des autres points ;
• - un mode remplacement qui permet le remplacement de l'information affichée sur un segment ou une partie de segment vertical ou horizontal par une nouvelle information.

On the other hand, the most elaborate plasma panel control circuits must allow, in order to easily display text or graphics, operation in two modes, namely:

• - an overprint mode which allows the entry or deletion of one or more points without modifying the other points;
• - a replacement mode which allows the replacement of the information displayed on a vertical or horizontal segment or part of a segment with new information.

However, to replace information, the solution usually used consists of sending an erase order to all the points in the segment or part of the segment to be modified, then entering the points to be switched on. This control method has a number of drawbacks. It is long, because you must first enter the address of all the electrodes of a segment to be deleted and then the address of the only electrodes to be entered. On the other hand, the writing of a point immediately after its erasure poses problems of stabilization of the charges at the terminals of the cell.

The present invention therefore relates to a new control method overcoming these drawbacks and in particular allowing an appreciable saving of time in replacement mode.

This control method is preferably used with plasma panels comprising a control circuit of the type described above. However, it can be applied to any control circuit in which the addresses of the active electrodes can be validated before the application of the voltages corresponding to the orders to be executed.

On the other hand, this control method can be used on plasma panels operating only in replacement mode or operating both in replacement and overprinting mode.

• - à adresser sur l'un des réseaux au moins un groupe d'électrodes avec au moins une électrode à activer ;
• - à sélectionner les électrodes adressées en fonction du mode de fonctionnement et d'un ordre d'effacement ou d'inscription de sorte que dans le mode surimpression les électrodes à activer soient sélectionnées quel que soit l'ordre et dans le mode remplacement, les électrodes à activer soient sélectionnées lors d'un ordre d'inscription et les électrodes complémentaires des électrodes à activer soient sélectionnées lors d'un ordre d'effacement ;
• - à sélectionner une électrode sur l'autre réseau ;
• - à appliquer sur les électrodes des tensions telles qu'une inscription ou un effacement selon l'ordre donné soit réalisé sur les cellules se trouvant à l'intersection de deux électrodes sélectionnées, les autres cellules étant entretenues dans leur état initial.

The present invention therefore relates to a method for controlling a panel with alternating type plasma operating in overprint and / or replacement mode, said method allowing the application of specific control signals between two electrodes belonging to two networks of orthogonal electrodes and the gas space located at the intersection of two electrodes belonging to different networks constituting a cell of the panel characterized in that it consists:

• - to address on one of the networks at least one group of electrodes with at least one electrode to be activated;
• - to select the electrodes addressed as a function of the operating mode and of an erasing or writing order so that in the overprinting mode the electrodes to be activated are selected regardless of the order and in the replacement mode, the electrodes to be activated are selected during an enrollment order and the electrodes complementary to the electrodes to be activated are selected during an erase order;
• - to select an electrode on the other network;
• to apply voltages to the electrodes such that an inscription or an erasure according to the given order is carried out on the cells located at the intersection of two selected electrodes, the other cells being maintained in their initial state.

With this method, to perform an image replacement, the points to be registered are addressed, then the complementary points of the points to be registered are deleted and immediately after the points to be lit are registered. This procedure has the advantage of not re-writing points which have just been deleted, which increases the operating range of the plasma panel.

On the other hand, the address of the points to be registered is loaded from the start, which avoids an address loading operation between the erasing of the previous information and the recording of the new information and results in a reduction in time. necessary to perform an image replacement.

The present invention also relates to a device for implementing the above method. In the case of an integrated control circuit comprising a low voltage logic circuit defining the signal to be executed, its duration and the electrodes of the panel to be activated and a low voltage - high voltage interface circuit, this device is constituted by a circuit validation positioned between the addressing part of the logic circuit and the interface circuit which validates at the output either the electrodes to be activated or the complementary electrodes of the electrodes to be activated according to the order of registration. and the operating mode chosen.

• - la figure 1 est un schéma sous forme de blocs d'un panneau à plasma et de ses circuits de commande ;
• - la figure 2 est un schéma sous forme de blocs du dispositif permettant la mise en oeuvre du procédé de la présente invention ;
• - la figure 3 est une représentation schématique de quelques cellules d'un panneau à plasma ;
• - les figures 4(a) à (c) et 5(a) à (c) sont une représentation des tensions élaborées par le circuit de commande selon l'invention et des signaux de commande reçus par les cellules de la figure 3 dans le cas d'un effacement et d'une inscription ;
• - la figure 6 est une représentation des tensions élaborées par le circuit de commande selon l'invention et des signaux de commande reçus par les cellules pendant une séquence de remplacement d'information.

Other characteristics and advantages of the present invention will appear on reading the description of an embodiment made with reference to the attached drawings in which:

• - Figure 1 is a block diagram of a plasma panel and its control circuits;
• - Figure 2 is a block diagram of the device for implementing the method of the present invention;
• - Figure 3 is a schematic representation of some cells of a plasma panel;
• FIGS. 4 (a) to (c) and 5 (a) to (c) are a representation of the voltages produced by the control circuit according to the invention and of the control signals received by the cells of FIG. 3 in the case of erasure and registration;
• - Figure 6 is a representation of the voltages developed by the control circuit according to the invention and the control signals received by the cells during an information replacement sequence.

In the figures, the same elements are designated by the same references.

FIG. 1 is a diagram showing the organization of a control circuit which can be used in the case of the present invention.

In this figure, the reference 1 designates the plasma panel itself. This plasma panel comprises two arrays of orthogonal electrodes, the electrodes of which have the references x, to x _n and y, to Y ".

In the embodiment shown, the control circuits consist of integrated circuits and amplifiers. The integrated circuits mainly comprise a logic circuit and a high voltage - low voltage interface which is in this embodiment, produced by the control circuits described in French patent application No. 8,119,941. However, other types of interface can be considered.

Thus the electrodes x, at x _n are controlled by integrated circuits which bear the reference X. Each integrated circuit consists of a logic circuit which will be described in more detail with reference to FIG. 2 and by a low voltage - high interface LV / HV voltage. The logic circuit is supplied with 12 Volts and receives commands and data in low voltage logic which define the signal to be executed, its duration and the electrodes of the panel to be addressed. The LV / HV interface is supplied by continuous voltages of values 0 Volt and 100 Volts and by a low-voltage sloping signal which generally increases from 0 to 12 Volts. It applies to the different electrodes to which it is connected, depending on the addressing and the order, either a voltage of 0 Volt or a sloping signal from 0 to 100 Volts as will be explained in detail below.

As regards the electrodes y ₁ to y _n , they are controlled by integrated circuits which bear the reference Y.

Two amplifiers 3 and 4 are associated with these integrated circuits. Integrated circuits Y are supplied by continuous voltages of values 0 Volt, 12 Volts, + 100 Volts and -100 Volts. They receive orders in low voltage logic which determine the address of the electrodes and the operation to be executed, namely erasure or registration and they send on the electrodes y of the panel to which they are connected either a voltage of 0 Volts, or a voltage of substantially + 100 volts, or a voltage of substantially -100 volts as will be explained in detail below.

Each integrated circuit X and Y generally makes it possible to control 32 electrodes.

A plasma panel comprising 256 X electrodes and 256 Y electrodes will therefore have a control circuit consisting of 8 integrated circuits X and a single amplifier for controlling the network of X electrodes and 8 integrated circuits Y and two amplifiers for controlling the array of y-shaped electrodes.

FIG. 2 is a diagram showing the structure of the logic circuit of the integrated circuits X allowing the implementation of the method of the present invention.

The logic circuit CL is mainly constituted by a serial / parallel shift register 10 comprising 32 outputs 10 ₁ , 10 ₂ ... 10 ₃₂ and a circuit for enabling outputs 12.

More specifically, the shift register consists of four shift registers with 8 binary positions each which can be cascaded, which makes it possible to work on groups of 8 electrodes as will be explained below.

The register receives in series logical data D defining the electrodes to be activated, namely the electrodes which must be registered in replacement mode or else the electrodes which must be registered or erased in overprinting mode. These data are shifted under the action of a clock pulse H which is validated for each circuit X by a validation circuit 11 as a function of a circuit validation pulse V '. On the other hand, byte validation pulses V ₀ to V ₃ make it possible to perform a replacement or overprint operation only on groups of 8 electrodes.

The validation circuit 12 of the outputs provided between the shift register 10 and the BT / HT interface 13 is constituted by 32 AND circuits 121 ₁ to 121 ₃₂ which receive as input the signal coming from the corresponding output of the shift register and a validation signal V ₀ to V ₃ depending on its position, AND circuits 121 ₁ to 121 ₈ receiving the signal V _o , AND circuits 121 ₉ to 121 ₁₆ receiving the signal V ₁ , etc. These AND circuits 121, to 121 ₃₂ therefore validate at least one group of 8 outputs of the shift register 10.

Each output of the AND circuits 121 ₁ to 121 ₃₂ is sent to one of the inputs of an inverted exclusive OR circuit 122, to 122 ₃₂ , the other input of which is validated by the output S ¹ of a validation circuit 123, to 123 ₄ . The validation circuits 123 ₁ to 123 ₄ make it possible to validate the output of an OR circuit _i24 as a function of the validation signals of bytes V _o to V ₃ so that, in replacement mode and with an erase order, the cells of the validated single or bytes are deleted. Each validation circuit 123, at 123 ₄ responds to the following truth table

On the other hand, an OR circuit ₁₂₄ is provided upstream of the validation circuit to indicate the operating mode chosen and thus allow adequate selection of the electrodes.

The OR circuit ₁₂₄ receives as input a logic signal O corresponding to the order to be executed, namely recording or erasing and a logic signal P corresponding to the operating mode in overprinting or in replacement. The signal O is chosen so as to be at logic level 1 for an entry order and at logic level 0 for an erasing order. Likewise, the signal P is at logic level 1 for operation in overprint mode and at logic level 0 for operation in replacement mode.

With the circuit described above for the byte (s) selected, in overprinting mode, the electrodes addressed by a logic level 1 are validated regardless of the order, but in replacement mode, the electrodes addressed by a logic level 1 are validated when the order is a registration order and the electrodes addressed by a logic level 0 are validated when the order is an erase order.

Will now be described with reference to Figures 3 to 6, the method of developing control signals and the sequence to be performed in replacement mode.

FIG. 3 schematically represents six cells C ₁₁ , C ₂₁ , C ₃₁ , C ₁₂ , C ₂₂ , C ₃₂ of a plasma panel which are located at the intersections of two horizontal electrodes y ₁ , and y ₂ and three vertical electrodes x ₁ , x ₂ and x ₃ .

It is assumed that one wants to register, using the method of the present invention, in a replacement mode, cells C ₁₁ and C ₃₁ of the line y ,. For this, the line y ₁ and the columns x, and x ₃ are selected simultaneously or not. We therefore enter the registers of integrated circuits corresponding to y ₁ and y ₂ a logic level 1 for y, and a logic level O for y ₂ and the other electrodes. Similarly, we enter into the registers of integrated circuits X corresponding to x ₁ , x ₂ and x ₃ a logic level 1 for x, and x ₃ and a logic level 0 for x ₂ .

After having loaded the addresses of the electrodes to be activated, the cells which do not have to be written on the line y ₁ selected, namely the deletion of cell C _{21, are} erased in accordance with the present invention.

• - les tensions V_x1 et V_x3 sont des tensions constamment nulles ;
• - la tension V_x2 varie à partir de l'instant t₃ sensiblement linéairement en fonction du temps de O à V₁ choisi égal à 100 Volts dans le mode de réalisation représenté puis se stabilise à V₁ et redescend à O au temps t₄. L'utilisation d'une telle tension pour effacer une cellule a été décrite dans la demande de brevet français 2 417 848 au nom de THOMSON-CSF ;
• - la tension V_y1 a une partie positive d'amplitude + 100 Volts de t₁ à t₂ ; une partie nulle de t₃ à t₄ et une partie négative d'amplitude -100 Volts de t₅ à t_s ;
• ― la tension V_y2 a une partie positive d'amplitude + 100 Volts de t, à t₂ et t₃ à t₄ et une partie négative d'amplitude -100 Volts de t₅ à t_s.

Figures 4 (a) and (b) represent the voltages V _x1 , V _x2 , V _x3 , V _y1 , Vy ₂ which are applied to the electrodes x ₁ , x ₂ , x ₃ , y ₁ , y ₂ so that only cell C ₂₁ is deleted. These tensions will be described with reference to the instants t ₁ to t ₆ which follow one another on the time axis.

• - the voltages V _x1 and V _x3 are constantly zero voltages;
• the voltage V _x2 varies from instant t ₃ substantially linearly as a function of the time from O to V ₁ chosen equal to 100 Volts in the embodiment shown, then stabilizes at V ₁ and drops back to O at time t ₄ . The use of such a voltage to erase a cell has been described in French patent application 2,417,848 in the name of THOMSON-CSF;
• - the voltage V _y1 has a positive part of amplitude + 100 Volts from t ₁ to t ₂ ; a zero part from t ₃ to t ₄ and a negative part of amplitude -100 Volts from t ₅ to t _s ;
• - the voltage V _y2 has a positive part of amplitude + 100 Volts of t, at t ₂ and t ₃ at t ₄ and a negative part of amplitude -100 Volts of t ₅ at t _s .

FIG. 4 (c) represents the control signals applied to cells C ₁₁ , C ₂₁ , C ₃₁ , C ₁₂ , C ₂₂ , C ₃₂ which correspond to V _x -V _y . Only the signal applied to cell C ₂₁ allows erasure thanks to the part of the voltage increasing linearly from 0 to V, from time t ₃ to t ₄ . For the other signals applied to the cells, there is a falling edge of amplitude -V, at time t, and a rising edge of amplitude + V ₁ at time t ₅ which corresponds to the characteristics of the maintenance signals and allows viewing of information already entered.

After having erased the cell addressed by a column at logic level 0, the cells C ₁₁ and C ₃₁ whose columns are addressed by logic levels 1 are then entered.

Figures 5 (a) and (b) show the voltages V _x1 , V _x2 , V _x3 , V _y1 , V _y2 which are applied to the electrodes x ₁ , x ₂ , x ₃ , y ₁ , y ₂ so that only cells C ₁₁ and C ₃₁ are entered.

• - les tensions V_x1 et V_x3 varient à partir de l'instant t'₃ sensiblement linéairement en fonction du temps de 0 à + 100 Volts puis se stabilisent à 100 Volts et redescendent à O au temps t'₄ ;
• - la tension V_X3 est constamment nulle ;
• - la tension V_y1 a une partie négative d'amplitude -100 Volts de t'₁ à t'₂ et t'₃ à t'₄ et une partie positive d'amplitude + 100 Volts de t'_s à t'_s ;
• - la tension V_y2 a une partie négative d'amplitude-100 Volts de t', à t'₂, une partie nulle de t'₃ à t'₄ et une partie positive d'amplitude + 100 Volts de t'₅ à t'_s.

In that case :

• - the voltages V _x1 and V _x3 vary from time t ' ₃ substantially linearly as a function of time from 0 to + 100 Volts then stabilize at 100 Volts and go back down to O at time t'₄;
• - the voltage V _X3 is constantly zero;
• - the voltage V _y1 has a negative part of amplitude -100 Volts from t ' ₁ to t' ₂ and t ' ₃ to t' ₄ and a positive part of amplitude + 100 Volts from t ' _s to t'_s;
• - the voltage V _y2 has a negative part of amplitude-100 Volts from t ', to t' ₂ , a zero part from t ' ₃ to t' ₄ and a positive part of amplitude + 100 Volts from t ' ₅ to _t's.

Figure 5 (c) shows the control signals applied to the different cells. As can be seen in these drawings, only the signals applied to C ₁₁ and C ₃₁ allow the inscription of these cells thanks to the part increasing up to 200 Volts between t ' ₃ and t'₄; the other cells being only maintained.

The sequence described above is summarized in FIG. 6 in which the amplitude of the voltages when the line is at logic level 1 as well as the signal to be applied to the column to be modified is shown in dotted lines.

On the other hand with regard to the overprinting mode, the signals to be applied to carry out an erasure or an inscription are the same as those described with reference to FIGS. 4 and 5, but in this case, these signals are applied only to the electrodes selected, namely on the electrodes at logic level 1.

Thus in the embodiment described above, on the columns x a selection or non-selection voltage is applied as a function of the validation of the column according to the order to be executed while on the rows y there is applied a voltage function of the order to be executed, namely interview or registration.

On the other hand, it is obvious to those skilled in the art that many modifications can be made to the present invention, in particular as regards the validation circuit used and the form of the signals applied to the electrodes. In addition, the columns and the rows can be reversed without departing from the scope of the present invention.

Claims (7)

1. A method of controlling an AC plasma panel which operates in the overwrite and/or replacement mode, said method allowing the application of specific control signals between two electrodes belonging to two perpendicular sets of electrodes, the gas space situated at the intersection of two electrodes belonging to different sets constituting a cell of the panel, characterized in that it consists in :

- selecting one electrode out of one of the sets,

- addressing out of the other set at least one group of electrodes including at least one electrode to be activated,

- selecting the addressed electrodes in accordance with the operating mode and of an erase or inscription instruction such that in the overwrite mode, the electrodes to be activated are selected irrespective of the instruction, and that in the replacement mode, the electrodes to be activated are selected, if a write instruction is present, whereas the complementary electrodes with respect to the electrodes to be activated are selected in the presence of an erase instruction,

- applying such voltages to the electrodes that in accordance with the given instruction, writing or erasing takes place in the cells located at the intersection of two selective electrodes, whereas the other cells are conserved in their initial state.

2. A method according to claim 1, characterized in that during the replacement mode :

- one electrode is selected out of one of the sets,

- at least a group of electrodes including at least one electrode to be activated is addressed in the other set,

- the complementary electrodes with respect to the electrodes to be activated are selected out of the second set,

- such voltages are applied to the electrodes that erasing takes place only in the selected electrodes,

- the electrodes to be activated are selected out of the second set,

- such voltages are applied to the electrodes that writing takes place only in the selected electrodes.

3. A method according to any one of claims 1 and 2, characterized ion that the addressing of the two sets of electrodes is made simultaneously.

4. A method according to any one of claims 1 and 2, characterized in that :

- in accordance with the instruction, a write or erase voltage is ap'plied to the selected electrode of the first set and a hold voltage is applied to the other electrodes of this set,

- simultaneously, a selection voltage is applied to the selected electrodes of the second set and a non-selection voltage is applied to the other electrodes of this set,

the shape, amplitude and duration of these different voltages being such, that only the cells receiving via one electrode the selection voltage and via the other electrode the write or erase voltage are inscribed or erased, whereas the other cells are held in their initial state.

5. A method according to claim, 4, characterized in that :

- the selection voltage increases linearily with time from O to V₁, then it is stabilized at V, prior to returning to zero,

- the non-selection voltage is zero,

- the write voltage is negative, its amplitude being V_i,

- the erase voltage is zero,

- the hold voltage is p6sitive, its amplitude being V, or zero in accordance with the write or erase instruction.

6. A device for implementing the method according to claim 1, characterized in that it comprises an addressing circuit-for addressing the electrodes of one set (10) defining at the output the electrodes to be activated, a low voltage/high voltage interface (13) and between the addressing circuit (10) and the interface (13) a validation circuit which validates at the output either the electrodes to be activated or the complementary electrodes to the electrodes to be activated in accordance with the write or erase instruction to be executed and with the chosen operation mode.

7. A device according to claim 6, characterized in that it further comprises means (121, to 121₃₂ and 123, to 123₄) allowing the addressing of one or several groups of electrodes out of the electrodes of one set.

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