EP0058724B1

EP0058724B1 - Power amplifier

Info

Publication number: EP0058724B1
Application number: EP81902371A
Authority: EP
Inventors: Akio Koizumi; Kiroshi Yamagishi
Original assignee: Sony Corp
Current assignee: Sony Corp
Priority date: 1980-08-27
Filing date: 1981-08-25
Publication date: 1985-07-03
Also published as: JPS6337964B2; AU7533081A; US4476436A; WO1982000739A1; EP0058724A1; EP0058724A4; JPS5742214A; AU550792B2

Description

This invention relates to power amplifiers for generating a pulse width modulated (PWM) signal proportional to the amplitude of an input signal.
A known type of power amplifier for this purpose is a so-called class D amplifier. Since such a class D amplifier generally has a transistor in its output stage operating in a switching mode, the output transistor produces relatively little heat and hence the power amplifier can be made small while still producing a large output. Because the efficiency increases as the switching frequency becomes higher, the switching transistor is usually a field effect transistor, which can operate at high speed; unlike a bipolar transistor, the switching speed of which is limited by carrier concentration effect. However, a field effect transistor for use in a power amplifier is more expensive than a bipolar transistor.
Swiss patent specification CH-A-482 353 discloses additional amplitude modulation of a PWM signal in a pulse width modulation low-frequency amplifier in a high-frequency transmitter.
One object of the present invention is to provide a power amplifier in which these defects can be alleviated.
Another object of the present invention is to provide a power amplifier utilizing bipolar transistors in its power amplifying stage.
According to the present invention there is provided a power amplifier for generating a pulse width modulated signal proportional to the amplitude of an input signal, characterised by:

a pair of level-shifting means, each supplied with said input signal;
a pair of switching means controlled by a pulse width modulated signal derived from said input signal for switching output signals from said pair of level-shifting means;
an adding means for combining respective outputs of said pair of switching means to produce a pulse width modulated signal amplitude-modulated in accordance with the level of said input signal; and
a power amplifier stage which is supplied with said output signal of said adding means, said power amplifier stage comprising a pair of bipolar transistors connected in complementary push-pull configuration.

The invention will now be described by way of example with reference to the accompanying drawings, throughout which like parts are referred to by like references, and in which:

Figure 1 is a circuit diagram of an example of a known power amplifier of pulse width modulation type;
Figures 2 to 4 are characteristic graphs used to explain the operation of the amplifier of Figure 1;
Figure 5 is a circuit diagram of an embodiment of power amplifier according to the present invention;
Figure 6 shows signal waveforms used to explain the operation of the amplifier of Figures 1 and 5; and
Figures 7 and 8 are characteristic graphs used to explain the operation of the amplifier of Figure 5.

Before describing the embodiment, a known power amplifier of similar type but having a transistor of emitter-grounded saturation type in the output stage will be described with reference to Figure 1. An input signal source 1 generates an input signal S_Z, the waveform of which is nearly a sine wave as shown in Figure 6B, a reference signal source 2 generates a clock signal S₁, the waveform of which is shown in Figure 6A, an integrator 3 integrates the input'signal S₂ on the basis of the clock signal S₁ so as to produce a saw-tooth wave signal S₃, the waveform of which is illustrated in Figure 6C, and a comparator 4 compares the saw-tooth wave signal S₃ with a reference level (zero level) so as to produce a PWM signal S₄ shown in Figure 6D.
Bipolar transistors 5 to 8 form a voltage amplifying section in which diodes 9 and 10 for use in absorbing charges are respectively connected in parllel with the emitter-collector paths of the transistors 7 and 8 in the output stage. If the transistors 7 and 8 are non-saturation type transistors, the diodes 9 and 10 are each connected to their base-collector paths. The output signals of the transistors 7 and 8 are supplied through a filter 15, which comprises coils 11 and 12 and capacitors 13 and 14, to a loudspeaker 16. DC voltage supply sources 17 and 18 are also provided.
In the case of a power amplifier in which the transistors in the output stage are each of the emitter-grounded saturation type, V_cE(_oN) is low and hence high efficiency can be expected. Nevertheless, since an operating point P at that time is in the saturated region as illustrated in Figure 2, even if the current which will be supplied to the bases of the transistors 7 and 8 ceases, charges still remain in the transistors 7 and 8. As a result, the collector currents do not cease immediately, and the current flows from the emitter-collector path of the transistor 7 to the collector-emitter path of the transistor 8, which causes the power amplifying efficiency to be deteriorated. Figures 3A to 3C show that when the transistors 7 and 8 are supplied with base currents l_B7 and I_B8 as shown in Figures 3A and 3B, respectively, collector currents I_C7 and l_c8 respectively flow as shown in Figure 3C. Generally, when the base currents I_B7 and l_B8 do not flow, it would be expected that the collector currents I_C7 and l_c8 would also not flow nearly simultaneously. But, when the charges remain as described above, then as indicated by hatching in Figure 3C, intervals exist during which the collector currents I_C7 and l_c8 flow such that they are superimposed on each other, and these currents flow from the transistor 7 to the transistor 8, which is why the power amplifying efficiency is deteriorated.
The main reason for this is that when an optimum bias is set to widen the effective dynamic range, the base current is selected in consideration of the collector current l_c (max) for a large output, so that in the case of a moderate output, there is too much base current and hence it takes a long time to absorb the charges accumulated therein. For example, as shown in Figure 2, although the operating point in the case of a moderate output stays at the position denoted by P', which is immediately before the beginning of the saturated region, in the case of a large output, the operating point stays at the position denoted by P, which is far into the saturated region. In this case, since the base current I_B1 at the operating point P is selected as the optimum bias setting and then held fixed, in the case of a moderate output, instead of the original base current 1₈₂ being sufficient, excessive base currents corresponding to the difference between the base currents l_B1 and I_B2 flow, so that it takes some time to absorb the accumulated charges.
Figure 4 is a graph showing an output-loss characteristic of the known power amplifier operating as described above. In Figure 4, curve a is a characteristic which expresses a loss caused by V_CE(_ON), curve b is a characteristic showing a loss caused by the switching speed, and curve c is a characteristic showing a summation of the above two losses.
As described above, in the case of the known power amplifier, since the base current is fixed and the position of V_CE(ON) is within the saturated region, it takes some time to absorb the accumulated charges and then, as described with reference to Figure 3, the current flows from the transistor 7 to the transistor 8, so that the efficiency is deteriorated and, as will be understood from Figure 4, the loss at that time becomes extremely large.
The embodiment of power amplifier according to the present invention will now be described with reference to Figures 5 to 8.
In this embodiment, there are provided a positive level-shifting circuit 21 and a negative level-shifting circuit 22, each serving for level-shifting the input signal S₂, which is supplied from the input signal source 1, towards the positive and negative sides. At the output sides thereof are produced signals S₅ and S₆, which are respectively shown by broken lines in Figure 6E. The signals S₅ and S₆ thus derived are supplied through switching circuits 23 and 24 whose opening and closing operations are controlled by a PWM signal S₄ supplied from a comparator 4, to an adder 25 which produces at its output a signal S₇ shown by a solid line in Figure 6E. In other words, at the output side of the adder 25 is produced the PWM signal S₄ which is amplitude-modulated by the signals S₅ and S_s, each being level-shifted to the positive and negative sides. The PWM signal S₇ thus amplitude-modulated is supplied through a buffer circuit 26 to the bases of the transistors 5 and 6. Otherwise the arrangement is the same as in Figure 1.
The operation of the embodiment will now be described. When the input signal source 1 produces the input signal S₂ as shown in Figure 6B, the input signal S₂ is integrated by an integrator 3 on the basis of the clock signal S₁ which is supplied from the reference signal source 2 and is shown in Figure 6A, and is then converted to the saw-tooth wave signal S₃ shown in Figure 6C. This saw-tooth wave signal S₃ is supplied to the comparator 4 in which it is compared with the reference level. Thus, the comparator 4 produces at its output side the PWM signal S₄ shown in Figure 6D.
On the other hand, the input signal S₂ from the input signal source 1 is also supplied to the level-shifting circuits 21 and 22 in which it is level-shifted respectively to the positive and negative sides. Accordingly, the level shifting circuits 21 and 22 produce at their outputs the signals S₅ and S₆, respectively, shown by the broken lines in Figure 6E, which are then supplied to the corresponding switching circuits 23 and 24. The switching circuits 23 and 24 are controlled to open and close by the PWM signal S₄ obtained at the output side of the comparator 4, so that they selectively produce the signal S₅ or S₆ applied thereto. More specifically, when the PWM signal S₄ is positive, the switching circuit 23 is closed to produce the signal S₅ shifted in level to the positive side, while when the PWM signal S₄ is negative, the switching circuit 24 is closed to produce the signal S₆ shifted in level to the negative side. The signals so derived are supplied in turn to the adder 25, and the adder 25 produces at its output the signal S₇ shown by the full line in Figure 6E, that is, the amplitude-modulated PWM signal 5₇.
The PWM signal S₇ controls the transistors 5 and 6, by which the corresponding base currents are supplied to the transistors 7 and 8 at the final stage. The base current 1₈ with which the transistors 7 and 8 operate in the saturated state is set as in the following equation, where the collector current and the current amplification factor of the transistors 7 and 8 are respectively taken as l_c and h_FE. l_B is approximately equal to (1.5 to 3)
That is, the base current of the transistors 7 and 8 is varied by the signal S₇, which is provided by amplitude-modulating the PWM signal S₄ with the input signal S₂, so as always to satisfy equation (1).
At this time, the operating points P₁ to P₃ of the transistors 7 and 8 are always immediately before the beginning of the saturation region, in accordance with the increase or decrease of the collector current I_c as shown in Figure 7. In other words, since only the required minimum base currents in response to the respective outputs are supplied to the transistors 7 and 8, when the supply of the base currents ceases, the collector currents no longer flow therethrough, so the phenomenon in the amplifier of Figure 1, that the charges are accumulated in the transistors 7 and 8 and even although the base current ceases, the collector current continues to flow, does not occur.
Figure 8 is a graph showing an output-loss characteristic in the embodiment. Curve a represents a characteristic to express a loss caused by V_cE(_ON)_' curve b represents a characteristic to express a loss caused by a switching speed, and curve c represents a characteristic to express a summation characteristic of both of the above losses. Comparing the loss characteristics of Figure 8 with those of the known circuit shown in Figure 4, it is apparent that the output-loss characteristic of the embodiment is substantially improved. In addition, as will be understood from Figure 8, in the embodiment, since the output-loss characteristics change is substantially linear, the distortion factor is improved over the whole range of the output. Thus a power amplifier can be provided which has less losses caused by V_CE(ON) or high switching speed, and which is low in distortion and high in efficiency.

Claims

1. A power amplifier for generating a pulse width modulated signal proportional to the amplitude of an input signal (S₂), characterised by: a pair of level-shifting means (21, 22), each supplied with said input signal (S₂); a pair of switching means (23, 24) controlled by a pulse width modulated signal (S₄) derived from said input signal (S₂) for switching output signals (S₅, S₆) from said pair of level-shifting means (21, 22);

an adding means (25) for combining respective outputs (S₅, S₆) of said pair of switching means (23, 24) to produce a pulse width modulated signal (S₇) amplitude-modulated in accordance with the level of said input signal (S_z); and

a power amplifier stage (5 to 10) which is supplied with said output signal (S₇) of said adding means (25), said power amplifier stage (5 to 10) comprising a pair of bipolar transistors (7, 8) connected in complementary push-pull configuration.

2. A power amplifier according to claim 1 wherein said pair of level-shifting means (21, 22) level-shift the level of said input signal (S_z) by predetermined amounts in positive and negative directions, respectively.

3. A power amplifier according to claim 1 further comprising pulse width modulating means (2 to 4) comprising an integrating circuit (3) for integrating said input signal (S_z) in dependence on a clock signal (S₁) supplied by a clock signal source (2) to produce a saw-tooth signal (S₃), and a comparator (4) for comparing the saw-tooth signal (S₃) with a reference voltage, whereby said pulse width modulated signal (S₄) is produced at the output of said comparator (4).

4. A power amplifier according to claim 1, claim 2 or claim 3 wherein a further pair of transistors (5, 6) in said power amplifier stage (5 to 10) are respectively connected in emitter-grounded configuration.