DE69116012T2 - Pallet devices with selection of multiple pixel depths containing the entire bus width - Google Patents

Description

BACKGROUND OF THE INVENTION

Without limiting the general scope of the invention, its background is described by way of example only in the context of computer graphics.

In computer graphics systems, the low cost of dynamic random access memory (DRAM) has made it economical to provide a bit-oriented or pixel-oriented memory for the system. In such a bit or pixel memory, a color code is stored in a memory location corresponding to each pixel to be displayed. A video system is provided which retrieves the color codes for each pixel and generates a raster scan video signal corresponding to the retrieved color codes. Thus, the data value stored in the memory determines the display by determining the color that is generated for each pixel (picture element) of the display.

The need for natural looking rendering and the need to minimize required memory are in conflict. In order to obtain a natural looking rendering, it is necessary to have a large number of colors available. This requires a large number of bits for each pixel to specify the particular color among a large number of possibilities. However, providing a large number of bits per pixel requires a large amount of memory for storage. Since a number of bits must be provided for each pixel in the rendering, even a moderately large rendering would require a large amount of memory. Thus, it is advantageous to provide a method for reducing the amount of memory required to store the rendering while maintaining the Possibility to choose from a large number of colors.

The provision of a circuit called a color palette allows a compromise between these conflicting requirements. The color palette stores color data words that are longer in bit length than color codes stored in the pixel map memory, rather than the actual color data words themselves. The color data words can specify colors to be displayed in a form that is ready for digital-to-analog conversion directly from the color palette. The color codes stored in the memory for each pixel have a limited number of bits, thereby reducing storage requirements. The color codes are used to select one of a number of color registers or palette locations. Thus, the color codes themselves do not define colors, but instead identify a selected palette location. These color registers or palette locations each store color data words that are longer than the color codes in the pixel map memory. The number of such color registers or palette locations provided in the color palette is equal to the number of selections provided by the color codes. For example, a 4-bit color code can be used to select 2n or 16 palette locations. The color data words can be redefined in the palette from frame to frame to provide many more colors in a continuous sequence of frames than those present in any single frame.

Because of the advantages of color palette devices, systems and methods, any improvements in their implementation in computer color graphics technology are beneficial.

WO-A-89 00744 describes a technique for selecting the colors for a pixel from more than 2n colors using only n bits for the pixel, with the color selection data expanded from 4 bits to, say, 8 bits. In normal operation, four bits of these eight bits are fixed and the other four bits are derived from the pixel data so that a palette of 16 colors can be used. In a special mode, entered when a flag code occurs in the pixel data, two blocks of four bits are taken in sequence and placed in an 8-bit register for selecting from a palette of more than 16 colors.

The display system described in WO-A-89 01218 provides both control information and colour information at each pixel. The two types of information from a pixel are combined in a processing module to produce colour display signals.

EP-A-0 358 918 describes a colour display system for a display device, such as one using LCD elements, which is capable of displaying only a limited range, for example 16 colour values at each pixel. The computer controlling the display system provides more bits, for example 18, for the colour values at each pixel and these colour values are applied as input colour values to a converter for providing four-bit output colour values for display, the converter being arranged to select the output colour value having the closest colour match to that represented by the input colour value.

An apparatus for reproducing color images with a reduced size image data memory is described in EP-A-0 319 684. The reduction in memory size is achieved by transforming a three-component color image signal into a two-component one by a quantization process using a look-up table. An example of the Reducing from 15 bits per pixel down to 8 bits per pixel is described. SUMMARY OF THE INVENTION

According to the present invention, a picture display device is provided with a video memory storing a plurality of multi-bit colour codes each representing a picture-forming pixel, a display means, a palette device with a look-up table memory for supplying colour data words for supply to the display means dependent on the colour codes, and a multi-bit bus having a predetermined number of bits connected to the video memory for transferring colour codes stored in the video memory in bus cycles,

characterized in that the multi-bit bus is designed in such a way that in each bus cycle several color codes are transmitted covering the entire width of the multi-bit bus; and that the palette device further contains:

an input buffer connected to the multi-bit bus for simultaneously receiving the plurality of color codes therefrom and for latching the plurality of color codes in each bus cycle;

a color code transfer circuit having an externally loadable control register storing a representation of the number of bits associated with each color code and a representation of the number of color codes transferred in each bus cycle;

and a multiplexer controlled by the control register and connected between the input memory and the look-up table memory, the multiplexer providing the look-up table memory with a sequence of bit blocks of data stored in the input memory, each of the bit blocks being equal in number to the number of bits associated with each color code stored in the control register, so that individual ones of the plurality of color codes are transferred from the input memory, the sequence continuing for a number of bit blocks equal to the number of color codes transferred from the multi-bit bus in each bus cycle for each loading of the input memory.

In general, one form of the invention is a palette device controllable by a digital computer having a frame buffer with a bus for supplying multiple color codes to the palette device in each bus cycle. The palette device includes a multi-bit input for inputting the color codes from the bus and a look-up table memory for supplying color data words in response to the color codes from the input. Color code transfer circuitry is connected between the input and the look-up table memory for supplying the look-up table memory from the input in a sequential manner with color codes of selectable widths, covering the entire width of the bus.

A technical advantage of the invention is a wider range of applications of the same palette device in systems with different bus widths and pixel widths.

These and other features of the present invention will be readily understood from the following description taken in conjunction with the drawings, in which

Figure 1 is a block diagram of a computer graphics system;

Figure 2 is a block diagram of a graphics coprocessor;

Figure 3 (shown on Sheet 2) shows an expanded stylized view of a video memory operating in conjunction with a partial serial register;

Figure 4 shows a graphic display for illustrative purposes;

Figure 5 shows a memory array for illustration purposes.

Figures 6, 7 and 8 show bits in the serial register at different times;

Figures 9 and 10 (shown on Sheet 1) show two row and column address arrangements for memories of different sizes;

Figures 11, 12 and 13 show masking bits for controlling the tapping point of the serial register in accordance with various physical configurations of addresses;

Figure 14 shows a block diagram of control registers in the graphics coprocessor of Figure 2 for controlling the serial registers; and

Figures 15 to 21 show bits in the control registers of Figure 14 ;

Figure 22 is a block diagram of an improved circuit for inserting a pulse during a blanking signal for a partial shift register transfer;

Figure 23 is a waveform diagram of signals in a form of transfer of the shift register;

Figure 24 is a waveform diagram of signals in which a pulse is inserted during a blanking signal in a partial shift register transfer;

Figure 25 is a pictorial outline of a circuit board for a computer graphics system of Figure 1;

Figure 26 is a block diagram of a computer graphics system with VGA and with an additional circuit board of Figure 25 with VGA pass-through;

Figure 27 is a block diagram of synchronous multiplexing for a pallet device;

Figure 28 is a block diagram of a computer graphics system using two image RAMs in a nibble mode;

Figure 29 is a block diagram of a combined facsimile and photocopier printer system;

Figure 30 is a block diagram of a computer graphics and image recognition system with a printer and an image display;

Figure 31 is a block diagram of a pallet device highlighting clock and video control and other features;

Figure 31A is an enlarged image of two scan lines in a raster scan display for illustrating a timing of blanking and sync signals;

Figure 32 is a block diagram of the palette device of Figure 31, highlighting a packed bus, a possibility of selectable pixel width, real color and overlay features, a VGA pass-through; ones accumulation and analog test features; and other features;

Figure 33 is a waveform diagram of a dot clock (pixel clock), a frame clock VCLK and a shift clock SCLK waveform in an operating mode of the palette device of Figures 31 and 32;

Figure 34 is a pallet device waveform diagram for the pallet device of Figures 31 and 32 when SSRT pulse insertion is disabled and the SCLK frequency is equal to the VCLK frequency;

Figure 35 is a waveform diagram for the pallet device of Figures 31 and 32 when SSRT pulse onset is enabled and the SCLK frequency is equal to the VCLK frequency;

Figure 36 is a waveform diagram for the pallet device of Figures 31 and 32 when SSRT pulse insertion is disabled and the SCLK frequency is four times the VCLK frequency;

Figure 37 is a waveform diagram for the pallet device of Figures 31 and 32 when SSRT pulse insertion is enabled and SCLK frequency is four times the VCLK frequency;

Figure 38 is a schematic diagram of a digital-to-analog converter for an analog color signal with added circuits for synchronization and blanking;

Figures 39 and 40 are two waveform diagrams of a composite video signal including analog video signal and blanking signal with front and back porches on either side of a synchronizing signal;

Figure 41 is a waveform diagram of a pulse insertion for a partial shift register transfer for showing timing relationships in Figure 22;

Figure 42 is a waveform diagram for the pallet device of Figures 31 and 32 for showing a timing in a special nibble mode;

Figure 43 is a state transition diagram for a test circuit of Figure 32;

Figure 44 is a schematic diagram for an analog test circuit in the test circuitry of Figure 32;

Figure 45 is a diagram of terminals of a semiconductor chip package containing a chip carrying the circuitry of the pallet device of Figures 31 and 32;

Figure 46 is a waveform diagram of a timing of register select bits R50-R53 and read, write and data signals in the palette device of Figures 31 and 32 ;

Figure 47 is a waveform diagram of a timing of clock and video control signals in the palette device of Figures 31 and 32;

Figure 48 is a waveform diagram of a timing of the blanking signal, an SSRT input signal and the shift clock SCLK when SSRT pulse insertion is enabled;

Figure 49 is a waveform diagram of a timing sequence in a process of sampling the blanking signal with clock signals of increasingly higher time resolution to establish a sampled blanking signal (Q output of X24) for blanking digital-to-analog converters such as that in Figure 38;

Figure 50 is a schematic diagram of flip-flops clocked with increasing time resolution for performing the process of sampling the blanking signals of Figure 49;

Figure 51 is a schematic diagram of a clock control circuitry in the pallet device of Figures 31 and 32;

Figure 52 is a schematic diagram of circuitry for sampling the blanking signal and producing a selectable variable delay in the pallet device of Figures 31 and 32;

Figure 53 is a detailed schematic diagram of circuit parts of Figure 52;

Figure 54 is a schematic diagram of an accumulator circuit for the test circuit of Figures 31 and 32;

Figure 55 is a block diagram of an accumulator multiplexer circuit arrangement for the test circuit of Figures 31 and 32;

Figure 56 is a block diagram of an alternative circuit for overlay, wherein detection of a particular value in majority bits selects an overlay, alternatively to detection of minority bits in the palette device of Figure 32;

Figure 57 is a block diagram of an alternative circuit for reducing decoding time in a palette device using partial modes and parallel decoders and LUTs (look-up table memories);

Figures 58A, 58B and 58C are three thirds of a flow diagram of a process or method for operating pallet devices and systems;

Figure 59 is a block diagram of circuitry for internal dynamic control of VGA passthrough and cursor generation;

Figure 60 is a pictorial outline of a graphics screen provided with a second graphic image as an insert;

Figures 61A, 61B and 61C are diagrams of pixels in two lines of an image for describing right and left shifting, respectively;

Figure 62 is a block diagram of a first embodiment of a circuit arrangement for enabling shifting;

Figure 63 is a diagram showing process loops of right and left shifting in systems with different bus widths;

Figure 64 is a waveform diagram of a timing of SCLK in two embodiments of a shift circuit arrangement of Figures 62 and 65; and

Figure 65 is a block diagram of a second embodiment of a shift circuit. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Before proceeding to a detailed discussion of the invention, it may be helpful to briefly review the basic operation of a graphics processor operating in conjunction with a host system with reference to Figures 1 and 2.

For convenience and ease of understanding of the inventive concepts taught herein, there is no attempt to show every single operation and data movement, since the actual embodiment of the invention in a system will depend to a large extent on the actual system operation in which the inventive concept is incorporated.

Figure 1 encloses a block diagram of a graphics computer system 100 constructed in accordance with the principles of the present invention. The graphics computer system 100 includes a graphics board 105 connected to a host processing system 110. Disposed on the board 105 are a graphics processor 120, a memory 130, a shift register 140, a video palette 150, and a digital-to-video converter 160. A video display 170 is driven by the video output of the board 105.

The host processing system 110 provides the main computing capacity for the graphics computer system 100. The host processing system 110 preferably includes at least one microprocessor, a read-only memory, a random access memory, and associated peripheral devices to form a complete computer system. The host processing system 110 preferably includes some type of input device, such as a keyboard or a mouse, and some type of long-term storage device, such as a Floppy disk drive. The details of the construction of the host processing system 110 are conventional in nature and known in the art, and therefore the present application will not detail this element further. The essential feature of the host processing system 110 as far as the present invention is concerned is that the host processing system 110 determines the content of the visual display to be presented to the user.

Graphics processor 120 provides the main data manipulation in accordance with the present invention to produce the particular image display presented to the user. Graphics processor 120 is bidirectionally connected to host processing system 110 via host bus 115. In accordance with the present invention, graphics processor 120 operates as a data processor independent of host processing system 110; however, graphics processor is expected to respond to requests from host processing system 110 via host bus 115. The graphics processor 120 further communicates with the memory 130 and the video palette 150 via a video memory bus 122. The graphics processor 120 controls the data stored within the image RAM 132 via the image memory bus 122. In addition, the graphics processor 120 can be controlled by programs stored in either the image RAM 132 or the read-only memory 134. The read-only memory 134 can additionally contain various types of graphics image data, such as alphanumeric characters in one or more font styles and frequently used icons. In addition, the graphics processor 120 controls the data stored within the video palette 150. Finally, the graphics processor controls the digital-to-video converter 160 via the image control bus 124. The graphics processor 120 can control the line length and the number of lines per frame of the video image presented to the user by controlling the Digital/video converter 160 via the video control bus 124.

Video memory 130 includes image RAM 132 which is bidirectionally connected to graphics processor 120 via image memory bus 125. As previously mentioned, image RAM 130 contains the bit map graphics data that controls the video image presented to the user. This image data can be manipulated by graphics processor 120 via image memory bus 122. In addition, image data corresponding to the current display screen is output from image RAM 132 via image output bus 136. The data from image output bus 136 corresponds to the picture element to be presented to the user. In a preferred embodiment, image RAM is formed from a plurality of TMS44251 256Kx4 dynamic read/write integrated circuits available from Texas Instruments Incorporated, the assignee of the present invention. The TMS44251 integrated circuit contains dual ports, which allows refresh and replay to occur without interference.

In accordance with the typical arrangement of an image random access memory 132, this memory consists of a bank of several integrated, separate random access memory circuits. The output signal from each of these integrated circuits is typically one or four bits wide and is output to an image output bus 136.

The video palette 150 receives the high speed image data from the image random access memory 132 via the bus 136. The video palette 150 also receives data from the graphics processor 120 via the image memory bus 122. The video palette 150 converts the data received on the parallel bus 136 into an image level that is output via the bus 155. This conversion is accomplished by means of a lookup table provided by the graphics processor via the image memory bus 122. The output of the video palette 150 may include color value and color saturation for each picture element or may include red, green and blue primary color levels for each pixel. The lookup table for converting the code stored within the frame buffer 132 and the digital levels output via bus 155 is controlled by the graphics processor 120 via the frame buffer bus 122.

The digital-to-video converter 160 receives the digital image information from the video palette 150 via the bus 155. The digital-to-video converter 160 is controlled by the graphics processor 120 via the image control bus 124. The digital-to-video converter 160 serves to convert the digital output signal of the video palette 150 into the desired analog levels which are applied to the image display 170 via the image output 165.

The video palette 150 and the digital-to-video converter 160 are integrated together and their circuitry is significantly improved to form a new device 4000, referred to herein as a "programmable palette" or simply a "palette." Associated with the palette 4000 is a clock circuit 4100 for multiple clock oscillators and programmable clock selection. These enhance the graphics computer system and its operations in general and will be described in more detail starting with Figure 22.

Finally, the image display 170 receives the video output signal from the digital-to-video converter 160 via the image output line 165. The image display 170 produces the specified video image for viewing by the operator of the graphics computer system 100.

It should be noted that the video palette 150, the digital-to-video converter 160 and the image display 170 may operate in accordance with two main image techniques. In the first, the image data is specified in terms of color values and color saturation for each individual pixel. In the other technique, the individual primary color levels Red, blue and green are specified for each individual pixel. In determining the design choice of which of these major techniques to use, video palette 150, digital-to-video converter 160 and image display 170 must be designed to be compatible with that technique. However, the principles of the present invention are unchanged in view of the operation of graphics processor 120 regardless of the particular design choice of image technique. All of the signals that contribute to the reproduction of color in any way are considered color signals, although they may not be from the red, blue, green technique.

Figure 2 shows the graphics processor 120 in more detail. The graphics processor 120 includes a central processing unit 200, dedicated graphics hardware 210, register files 220, an instruction cache 230, a host interface 240, a memory interface 250, input/output registers 260, and a display controller 270.

The heart of the graphics processor 120 is the central processing unit 200. The central processing unit 200 has the capability to perform general purpose data processing including a number of arithmetic and logical operations normally included in a general purpose central processing unit. In addition, the central processing unit 200 controls a number of special purpose graphics instructions, either alone or in conjunction with special purpose graphics hardware 210.

The graphics processor 120 includes a main bus 205 that is connected to most parts of the graphics processor 120 including the central processing unit 200. The central processing unit 200 is bidirectionally connected to a set of register files including a number of data registers via the bidirectional register bus 202. The register files 220 serve as storage for the immediately accessible Data used by central processing unit 200. As will be further discussed below, register files 220 contain, in addition to general purpose registers that may be used by central processing unit 200, a number of data registers used to store complex operands in graphics instructions.

The central processing unit 200 is connected to the instruction cache 230 via the instruction cache bus 204. The instruction cache 230 is also connected to the bus 205 and can be loaded with instruction words from the frame buffer 132 (Figure 1) via the frame buffer bus 122 and the memory interface 250. The purpose of the instruction cache 230 is to speed up the execution of certain functions of the central processing unit 200. A repeat function, or a function that is used frequently within a particular section of the program being executed by the central processing unit 200, can be stored within the instruction cache 230. Access to the instruction cache 230 via the instruction cache bus 240 is much faster than access to the frame buffer 130. Thus, the program executed by the central processing unit can be sped up by pre-loading the repeated or frequently used sequences of instructions within the instruction cache 230. Then, these instructions can be executed more quickly because they can be fetched more quickly. The instruction cache 230 need not always contain the same sets of instructions, but can be loaded with a particular set of instructions that are often used within a particular section of the program executed by the central processing unit 200.

The host interface 240 is connected to the central processing unit 200 via the host interface bus 206. The host interface is further connected to the host processing system 210 (Figure 1) via the host system bus 115. The host interface 240 serves to control the communication between the host processing system 110 and the graphics processor 220. The host interface 240 controls the timing of data transfer between the host processing system and the graphics processor 120. In this regard, the host interface 240 enables either the host processing system 110 to interrupt the graphics processor 120, or, conversely, the graphics processor 120 to interrupt the host processing system 110. In addition, the host interface 240 is connected to the main bus 205 to allow the host processing system 110 to directly control the data stored in the memory 130. Typically, the host interface 240 would forward graphics requests from the host processing system 110 to the graphics processor 120 to allow the host system to specify the type of display to be produced by the image display 170 and cause the graphics processor 120 to perform a desired graphics function.

The central processing unit 200 is connected to a special graphics hardware 210 via a graphics hardware bus 208. Special graphics hardware 210 is further connected to the main bus 205. Special graphics hardware 210 operates in conjunction with the central processing unit 200 to perform special graphics processing operations. The central processing unit 200, in addition to its general purpose data processing function, controls the use of the special graphics hardware 210 to perform special graphics instructions. These special graphics instructions relate to the manipulation of data within the bit map portion of the image RAM 132. Special graphics hardware 210 operates under the control of the central

Processing unit 200 for enabling special, advantageous data manipulations with respect to the data in the image RAM 132.

The memory interface 250 is connected to the bus 205 and further to the frame buffer bus 122. The memory interface 250 serves to control the communication of data and commands between the graphics processor 120 and the memory 130. The memory 130 contains both bit map data to be displayed via the frame display 170 and commands and data necessary to control the operation of the graphics processor 120. These functions include controlling the timing of memory access and controlling data and memory multiplexing. In the preferred embodiment, the frame buffer bus 122 contains multiplexed address and data information. The memory interface 250 enables the graphics processor 120 to provide the appropriate output signal on the frame buffer bus 122 at the appropriate time to access the memory 130.

The graphics processor ultimately includes input/output registers 260 and a display controller 270. The input/output registers 260 are bidirectionally coupled to the bus 205 to enable reading and writing within these registers. The input/output registers 260 are preferably located within the common memory space of the central processing unit 200. The input/output registers 260 contain data specifying the control parameters of the display controller 270. The display controller 270 is clocked by a display clock signal VCLK from the palette 4000. In accordance with the data stored within the input/output registers 260, the display controller 270 generates the signals on the display control bus 124 for the desired control of the palette 4000. Data within the input/output registers 260 Registers 260 contain data for specifying the number of pixels per horizontal line, the horizontal sync and blanking intervals, the number of horizontal lines per frame, and the vertical sync and blanking intervals. The input/output registers 260 may also contain data specifying the type of frame interlacing and specifying other types of frame control functions. Finally, the input/output registers 260 are a repository for other specific types of input and output parameters, which are described in more detail below.

The graphics processor 120 operates in two different address modes for addressing the memory 130. These two address modes are x-y addressing and linear addressing. Since the graphics processor 120 operates on both bit mapped graphics data and conventional data and instructions, different portions of the memory 130 can be accessed very conveniently through different address modes. Regardless of the particular address mode selected, the memory interface 250 generates the appropriate physical address for the appropriate data to be accessed. In linear addressing, the starting address of an array is formed from a single linear multi-bit address. The array size is determined by data within a status register within the central processing unit 200. In x-y addressing, the starting address is a pair of x and y coordinate values. The field size is equal to the size of a pixel, i.e. the number of bits required to specify the particular data at a particular pixel.

Referring to Figure 3, a brief discussion of the memory structure of a typical graphics memory system is now in order, before moving on to the actual detailed description of the operation of the embodiment of the present invention. Background information on a video RAM (VRAM) is found in commonly assigned U.S. Patents 4,330,852; 4,639,890; 4,683,555. Although there are many memory structures and systems that can be used, typically a structure such as that shown in Figure 3 is used which uses eight VRAM memories 130 in an array. Each VRAM memory or VRAM unit has four sections or levels 0, 1, 2 and 3. The design of each level is such that a single data line is used to write information to that level. In a system using a 32-bit data bus such as data bus 122, there would be eight VRAM memories (two of which are shown in Figure 3), with each VRAM memory having four data lines connected to the input data bus.

Thus, for a 32-bit data bus, VRAM 132 would have its four data lines connected to data bus lines 0, 1, 2, 3, respectively. Accordingly, the next VRAM would have its four lines 0, 1, 2, 3 connected to data bus lines 4, 5, 6, 7, respectively. This continues for the remaining six VRAMs, so that the last VRAM has its lines connected to lines 28, 29, 30, 31, respectively, of bus 122.

The memories are arranged so that the pixel information for graphics display is stored serially across the planes in the same row. Assuming a four bit per pixel system, the bits for each pixel are stored in a separate VRAM memory. In such a situation, pixel 0 would be in the first VRAM, and pixel 1 would be in the second VRAM. The pixel memories for pixels 2 through 7 are not shown. The pixel information for pixel 8 would then be stored in the first VRAM, still in row 0, but in column two of it. The reason for this arrangement of pixel information will be more fully understood from an understanding of how information is retrieved from memory.

Continuing with Figure 3, each VRAM has a serial register 139 for shifting out information from a row of memory. The shifting occurs at a rate determined by the shift clock signal SCLK from pallet 4000. The outputs from these registers are connected to bus 136 in the same way that the data input lines are connected to the input bus. Thus, data from a row of memory, say row 0, would be moved into register 139 and appear serially from each register 139 and in parallel on bus 136. This would occur for each level of the 8 memory array.

Looking at the data output bus 136, at an instant in time the first bit in each shift register would be on the bus. Thus, assuming that row 0 is currently being output to the bus, the bus would have on its line 0 from row 0 bit A0 (level 0) of memory 130. Line 1 of bus 136 would have bit A0 (level 1) from row 0, while line 2 from row 0 would have bit A0 (level 2) and line 3 from row 0 would have bit A0 (level 3). These bits would be followed by the bits from the next VRAM. Thus, at a first instant in time, the data bus 136 would have on it the four bits forming pixel 0, in addition to the four bits forming pixel 1, in addition to the four bits forming pixel 2. This would continue until the 32 bits forming 8 pixels 0 through 7 were on the parallel lines of data bus 136. These bits would be supplied to the graphics display and the shift registers would all shift one position to supply the buses with pixel information for the next eight pixels, namely pixels 8 through 15. This shifting would then continue until the entire row in the VRAMs was shifted out and then a new row would be sent for loading into the output serial registers. selected. Up to this point it has been assumed that the bit information per pixel is 4 bits. For example, if the pixel information was 8 bits then two VRAMs per pixel would need to be used. This would change the bit patterns somewhat. Also it should be noted that memory sizes and memory structures are constantly changing and the size and structure shown are for illustration purposes only and the invention can be used with many different memory configurations and with different pixel sizes.

As previously discussed, the serial register 139 for each memory would be 512 bits long, thereby transferring 16384 bits to the display for each memory/serial register read cycle. These 16384 bits represent data for 2048 display pixels, assuming that each pixel contains 8 bits. However, assume that each scan line requires only 1280 pixels. Thus, on each line of memory, 768 pixels from each row of memory cannot be displayed. It is difficult to use this memory for other purposes, and thus it is effectively wasted.

To solve the problem, the serial output register 139 was split in half and each half used to output data from the VRAM. Although it is understood that 32 shift registers 139 are used, the discussion will focus on only one level of memory with the understanding that all levels operate in the same way. The two halves of register 139 are known as half A and half B. Advantageously, the serial register 139 takes from memory an entire row of screen memory and delivers that row to the screen pixel by pixel in a smooth, consistent flow.

As described above, if this had to be done with a single, undivided serial register, then the Information for an entire scan line of the display must be moved from memory 132 into serial register 139, and then shifted to the screen at the screen clock rate. This would then require that each row of memory contain only one line (or whole multiples thereof) of the screen information. This is not the case, as will be seen, with a partitioned serial register, where bits can be shifted from the A section while other bits are loaded into the B section, and shifted to the screen from the B section while other bits are loaded into the A section.

Referring now to Figure 4, a graphics screen 401 is shown having 40 pixels across its surface and several rows of pixels down. It is to be understood that the numbers used here are for illustrative purposes only and bear no resemblance to the number of pixels, say 1280, across the surface of an exemplary graphics screen. The actual numbers are so high that the operation of the invention would be cumbersome if the example given used numbers approaching those actually found. The same applies to the discussion of memory 501, Figure 5, which will follow, and system arrangements using real numbers would only serve to obscure the discussion. In fact, as will be seen, the memory 501 used for discussion purposes has less column capacity (16) in terms of pixels than does the screen 401. In practice, this would typically be the other way around.

Currently, a system with 1280 pixels per line and 1024 lines would be refreshed at a rate of 60 times per second, and thus the pixels must be rendered at a rate of one every 12.7 ns. Using an 8-bit pixel, where two 4-bit VRAMs provide data for one pixel, four sets of VRAMs would be connected to the 32-bit bus This would require clocking the VRAMs once every 50.8 ns, which corresponds to a frequency of 19.6 MHz. When data is moved at such high speeds, any small pause (such as reloading the serial register) is noticeable. Furthermore, this problem can extend to clock rates in any of the clocks in the clock unit 4100.

Referring to Figure 5, a memory 501 is shown in which each pixel has four bits. For purposes here, it is also assumed that only two such memory units are used, one containing even pixels and one containing odd pixels (not shown). This would result in the use of only eight bits or lines of the bus, 4 bits from each memory unit. It is also assumed that the memory has only 16 columns, labeled 0 through 15. Thus, row 0 is labeled A0 through A15, while row 1 is labeled B0 through B15. If the discussion is further restricted to the memory unit with only the even pixels, then it can be thought of that bit A0 represents data for pixel 0 and bit A1 represents data for pixel 2. This follows because the A0 bit in the unseen second VRAM would contain information from pixel 1.

According to this perhaps impractical but illustrative embodiment, this would then result in the information for the (even) pixels 0-30 being in row A, the information for the (odd) pixels 32-62 being in row B, and so on, as shown in Figure 5.

Now assume that it is desired to transfer to the screen the pixel information for screen pixels 40-79 (Figure 4), which form the pixels necessary for the second row of the screen.

To accomplish this task, the system sends to the memory the command bits that address the memory below row B, since the information for pixels 40-79, as described above, is located in rows B and C of the memory (Figure 5).

This operation would result in the serial register being loaded with the pixel information for pixels 32-62 of row B. This is shown in Figure 6. However, if the entire register were to be shifted onto the screen, bits B0 through B3 would also be shifted, and this would cause difficulties since these bits correspond to pixels 32-38 which (as seen in Figure 4) are on the row of the screen. To avoid this problem, the processor, not shown, which controls the memory transfer keeps track of the correct bit position from which to begin a shift and supplies this information to memory as part of the previously mentioned instruction. This position is known as the tap point.

To control the operation of the partial register, it is necessary to know when to reload the first part of the register, that is, when data is being removed from the second part and data from the first part has already been removed, or when the data in the first part extends to an earlier screen row, as may occur immediately after the return interval. It is of course also necessary to know when to reload the second part of the register, that is, when data is being read from the first part after data has been read from the second part. To accomplish this function, a counter is used to keep track of the position of the serial register that is active at a given time. For the counter to work properly, it must know the starting point (tap point) in the register of the first data shift. This is necessary because, as discussed above, the starting point is not necessarily at the beginning of the memory row. Several steps must be taken to calibrate the counter on a row-by-row basis to control the loading and reloading of the two halves of the serial register.

One control of the serial register is such that when the first half of the register has finished sending data, it can be cleared and reloaded so that while the bits are being sent from the second half of the register, new data can be loaded into the first half. If, in fact, the bits to be sent first were in the second half of the register, the B half, then the A half would have to be reloaded immediately. This fact must also be determined. These determinations are made from the address information provided for the memory and are dependent on the bit positions and the number of bits necessary to specify an address.

As an example of the problem, some typical address bit configurations are shown in Figures 9 and 10. Figure 9 shows a 10-bit row and column address preceded by 3 bank select bits and 5 miscellaneous address bits. Figure 10 shows an 8-bit row and column address preceded only by the miscellaneous address bits.

Masks are provided for tracking system configuration by the user. Figure 11 shows a mask for use with the address configuration of Figure 9, while Figure 12 shows a mask for use with the configuration of Figure 10. Figure 13 shows the mask used by the system, with 3 tap point bits (16 possible columns, 8 in each half shift register) preceded by two bank select bits. These bits have been added for discussion purposes.

Figure 14 provides a diagram to explain how to use these masks. Figures 15 to 20 show an example.

Figure 15 shows the row and column address bits for row 1, column 4 of memory, which, as will be recalled, is where the first pixel 40 for the selected screen row is located. The bit word shown in Figure 15 also has additional address bits 0-4 and bank bits 5-6. The tap point bits are loaded into the tap point register 91. The tap point is defined as the bit position in the register that will be read onto the bus first. This tap point is calculated from the address information of Figure 15. In this example, the first 5 bits of the address (0-4) can be ignored, as they would be constant for all configurations for design reasons. The next 13 bits of the address are transferred to the tap register 91, Figure 16.

As shown in Figures 17 and 18, and as controlled by Figure 14, the mask 93 created for our example system (Figure 13) is copied into the mask shift register 92. This mask serves to set the tap point for the possible variation of the bank select bits. In this example, there were two such bits, and thus the first two bits of the mask are 0. A clock then shifts registers 92 and 91 to the right until a 1 occurs in the rightmost position of the shift register 92 (Figure 19). This operation serves to remove the bank bits from the tap point, which then becomes 100 as seen from register 91, Figure 20.

This is then loaded into the tap point counter 94 (Figure 21). The shifted mask 92 (Figure 19) determines how many bits of the counter 94 are significant. This tap point, which is defined as the position in the serial registers that is to be read first onto the data bus, can be Figure 6 and corresponds to pixel 40, which is controlled by bit B4 in half-register A.

Register A is selected as opposed to register B because the leftmost column bit in Figure 15 is 0. If the leftmost position of the column address had contained a 1, the B half of the serial register would have been selected.

Once the shifted tap point is selected, clock 2001, working in conjunction with the memory shift clock SCLK, is used to increment the tap point shift register in conjunction with data read from the serial registers. Thus, if the tap point register only contains 111, it means that the data from position 111 of half register A, Figure 6, is being read onto the bus. This corresponds to pixel 46, memory image B7. The tap point counter overflows to 000 when a shift from half register B begins, where memory positions B8 - B15 are again sent to the graphics display. Note that the register operation just described does not control the actual shifting out of the data, but rather the reloading of the data into the serial register.

At this point, as shown in Figure 7, half register A is cleared and information from memory locations C0 through C7, the next memory row, is loaded into half register A. This alternating operation will continue until the screen reaches the end of the row, i.e. pixel 79 is sent to the screen. Reloading the half row requires an address pointing to the first bit in the half row being reloaded. This address comes from an "incrementable copy of the row address", 95. Register 95 is loaded from register 90 when register 91 is loaded from register 90. It is then incremented to the leftmost bit of the column address to point to the next half row. Register 93 becomes the to determine the bit position for the increment (the bit to the left of the leftmost 1). When the address is output, register 93 is also used to ensure that all bits to the right of this point are 0 (denoting a zero tap address pointing to the first bit in the shift register). Each time the counter overflows, the address in this register is output and then incremented.

Thus, when the tap point SCLK clock 2001 again reaches 111 and pixel 62 at memory location B15 is less than pixel 79, the tap point counter goes back to 000 and, as shown in Figure 8, C0-C7 as memory bits are transferred from the half register A to the bus. As this happens, the half register B is loaded with memory bits C8-C15. However, when the clock again reaches 111, the return interval is also reached and the registers are reset with the next full line to be read on the screen as determined by the processor. The cycle repeats and a new tap point is calculated.

If the new tap point indicates that the first bit to be read is in the B half of the register, which would be the case if pixel array 80-119 were next, then the A half of the register would occur as shown in Figure 8 with the tap point at position C8. This would mean that the A half register must be immediately cleared and loaded with storage bits D0-D7 in preparation for the tap point counter to reach 111 again and jump around to follow the reading of data from the first A half register.

The partial shift register VRAMs use a SCLK signal between a full shift register transfer cycle and the partial transfer cycle. The present work recognizes that these two transfers occur sequentially during the blanking period should be when the SCLK signal is deactivated. The present embodiment advantageously identifies the interval between the two transfers and passes a signal to the SSRT terminal of the palette in the SSRT mode and not in the nibble mode so that the circuit generates an SCLK pulse at that time. This improvement provides a palette and clock generator with additional external control of the shift clock signal SCLK.

In a partial shift register application, all reloading is done during the blanking signal, as shown in Figure 23. Then, after SCLK is started again, the split reload is initiated. However, this only works if the split reload occurs before there have been enough SCLK pulses to move the serial data stream out of the first half and into the second half of the shift register 140. Often this is the case, but to implement a system that can have totally arbitrary boundaries (e.g., one that can have a horizontal shift) it is advantageous to avoid the real-time limitations that could be imposed if the first (or another early) SCLK pulse after the blanking signal moved the pointer out of the reloaded half.

Figure 22 shows logic for identifying a period in which the extra SCLK pulse is advantageously to be used. In the partial serial register VRAM mode, indicated by setting an SSV mode bit for the active VRAM, the TMS34020-GSG generates 120 partial serial register transfer cycles for the VRAM. During horizontal blanking, a regular serial register transfer cycle is generated to initialize the next VRAM row. This is immediately followed by a partial serial register transfer cycle, as shown in the memcy- waveform of Figure 24, to configure the VRAM into partial mode and ensure that the inactive serial registers contain undisplayed data, and not the data that was previously displayed.

In order for operations to occur in the correct order, the SCLK input to the VRAM is clocked between the rise of TR-/QE- at the end of the normal transfer and the falling edge of RAS- at the beginning of the partial transfer to ensure that the tap point provided during the transfer cycle of the ordinary serial register is not overwritten. A decoder logic circuit 2201 of Figure 22 provides a signal to inform the video special logic of the palette 4000 when to insert this pulse. The circuit 2101 is suitably physically contained in the GSP 120 or in the VRAM 130 or in the palette 4000, as an enhancement of any of them or as separate logic on a circuit board 105.

Decoder logic 2201 receives the status code output at the beginning of each memory cycle of the GSP 120 on the TMS34020 LAD bus 205 as an input. If 0100 is detected and the SF pin of the TMS34020 is low (indicating a normal VRAM serial register transfer), the SSRT signal is set high on the falling edge of LCLK1 while CRS2- is low. This coincides with the rising edge of TR-/QE-. SSRT remains unasserted until a partial serial register transfer cycle occurs. If the logic detects the 0100 status code and the SF pin is high (indicating a partial VRAM serial register transfer), the SSRT signal is set low on the falling edge of CAS2-. The video special logic in Palette 4000 uses the rising edge of SSRT to insert a single SCLK pulse.

In Figure 22, a TMS34020-GSP 120 is connected to the VRAM 130 via bus 125, and the shift register 139 is connected to the pallet 4000 via bus 136. The VRAM 130 and the shift register 139 are advantageously implemented as a sub- Shift register VRAM is implemented as discussed in Figures 1-21 to minimize wasted memory space in the graphics system 100. Palette 4000 is connected to GSP 120 via buses 122 and 124. The SSRT input from palette 4000 is input by the output of a decoder 2201 which detects a predetermined code on LAD lines 0-3 from LAD 205 of Figure 2. This decoder is enabled only when the blanking signal from GSP 120 is low. Decoder 2201 is clocked by the falling transition of the RAS (row address strobe) signal. The output of the decoder is activated by the rising transition of the RAS signal to drive the SSRT terminal of pallet 4000 and cause an onset of an SCLK pulse, as discussed using the waveform diagrams of Figures 23 and 24.

In the pictorial representation of Figure 25, a programmable palette 4000 is provided on a graphics system board 105. The board 105 is also equipped with a 1 megabit VRAM 130, a TMS34020 GSP 120, a DRAM 121, and a set of clock oscillators 4100. The system board 105 is advantageously provided with opposing bus connectors, one for the bus 115 and an auxiliary connector 6521 for the VGA pass-through. Optional interface logic 123 provides logic functionality that may be desired outside of the main chips. The board 105 is inserted into the main board of its host computer via the connector to the bus 115.

Further in the system board, a connector 165 supplies a standard composition NTSC video output signal to a color display device 170 of Figure 1. Synchronization generation is established on one of the color output channels, for example green.

The VGA pass-through mode provides VGA and non-VGA displays with only one monitor. In Figure 26, the computer has a motherboard 6501 with a microcomputer chip 6502 and memory chips 6504 mounted thereon. The motherboard 6501 is connected to a bus 6503. A VGA compatible graphics board 6505 is connected to the motherboard 6501 through the bus 6503. If only VGA were to be used, a monitor 6511 would be connected to a DB-15 video connector 6512 on the board 6505. The board 6505 has graphics circuitry mounted thereon and generates color code signals according to the VGA standard. This circuitry is controlled by the microcomputer chip on the motherboard 6501.

To produce advanced non-VGA displays, a board 105 of Figure 1 is connected to bus 6503. Board 105 has a graphics processor 120 and is responsive to control by microprocessor 6502, such as an 80386 on motherboard 6501. A video memory 130 is mounted on board 105 and is connected to graphics processor 120 for producing color code signals on another bus 136 in accordance with a second graphics standard, such as Texas Instruments Graphics Architecture (TIGA), for palette 4000, which is connected to VRAM 130 by a printed circuit board on board 105. An auxiliary connector 6521 on board 105 is connected by a VGA bus 6523 to an auxiliary connector 6525 on the graphics board 6505. The auxiliary connector 6525 supplies color code signals according to the VGA standard. The auxiliary connector 6521 on board 105 inputs the VGA color code signals.

The VGA pass-through allows the 6511 monitor to be omitted, and the 6513 monitor is connected to the DB-15 video connector 6527 for displaying both VGA graphics and TIGA graphics, depending on user selection.

Palette 4000 has an input register 4011 of Figure 31 having a first portion connected to video memory 130 of Figure 26 for inputting a first set of color code bits in accordance with the TIGA architecture. Input register 4011 has a second portion connected to auxiliary connector 6521 for inputting a second set of color code bits in accordance with the VGA standard. Lookup table memory 4021 of Figure 31 provides color data words in response to color codes from input register 4011. Selector circuit 4051 is connected between input register 4011 and lookup table memory 4021. The selector circuit 4051 is connected via a control register 4371 to the graphics processor 120 via the bus 122 and is thereby controllable to transfer selected color codes on the selected bus 136 or 6523 to the look-up table memory 4021 in accordance with the selected first or second graphics standard.

Because of the way the hardware and software of a typical 80386 computer, such as an IBM-compatible PC (Personal Computer), work, boot operations, shortly after the PC is powered up, look for the VGA graphics board 6505 of Figure 26, which is provided as a standard board in an IBM-compatible PC. If the VGA board 6505 is connected to an IBM monitor 6511, a separate monitor 6513 is required, which must be connected to board 105. During booting, the PC CPU would find the VGA hardware 6505 and execute the boot sequence that would output text to the monitor 6511. Then, if high resolution graphics are required, the system would turn off or not use the VGA monitor 6511 and then enable the monitor 6513. Since each of the 6511 and 6513 monitors can be the same type of device, in many cases it is desirable to use a single monitor. If both the 6505 and 105 boards are to be used with only one monitor, the VGA pass-through mode allows a Viewing VGA data, such as the prompt initially displayed. The VGA pass-through advantageously avoids any need for implementation of VGA itself on the palette 4000 or anywhere else on the board 105. The VGA board 6505 responds to the CPU on the motherboard 6501 during start-up, provides the initial text and port directly to the monitor 6513 through the VGA pass-through mode provided in the palette 4000, after which a switch can be toggled to the high resolution mode provided by the board 105. Thus, there is no need for separate monitors and for the VGA board 6505 and for the high resolution board 105. The board 105 does not need VGA power-up initialization software or further duplication of the VGA.

In addition, the VGA pass-through mode allows VGA compatible application software to be executed by the CPU 6502 and the VGA graphics to be generated by the board 6505 or on the motherboard itself, whereupon the VGA graphics are passed through board 105 in the VGA pass-through mode. When a high resolution mode is invoked, the graphics are controlled by the CPU on the board 6501, but are set up by the graphics processor 120 (such as the TMS 34010 or 34020 GSP from Texas Instruments Incorporated using the TIGA-TI architecture), passed through the VRAM 130 and the palette 4000 to the monitor 6513.

The throughput improvement does not depend on the specific characteristics of VGA or TIGA. Accordingly, any two or more graphics architectures, standards or techniques can be applied.

Both an 8/6 DAC width selection feature and the VGA pass-through feature work together advantageously. VGA has a basic 6-bit graphics width and a wider 8-bit feature. In VGA, the 6 bits at the low end of each bytes. When the palette RAM 4021 is loaded with color data words (as opposed to accessing the RAM 4021 with VRAM color codes, which in VGA must be in the least significant 6 bits of each byte when the basic 6 bits are used), the data value for each color data word on the palette goes into the least significant 6 bits. However, the output signal should be designed as if the least significant 6 bits were loaded into the most significant 6 bit positions of the 3 bytes in each color data word. The 8-bit/6-bit selection forces the 6 least significant bits of the RAM 4021 to drive the most significant inputs of the DACs. For its part, unlike the 8/6 select for initially loading the locations in RAM 4021, the VGA pass-through mode advantageously bypasses internal multiplexing to allow the 6 VGA color code VRAM bits to go straight to the RAM 4021 address input decoders to access the color data words. One set of features avoids interference with VGA bits by VGA pass-through for palette access and also causes the DACs to produce their highest output signals possible for a VGA signal (8/6 select feature) for best signal-to-noise ratio.

At start-up, the palette 4000 defaults to the CLK0 clock input which is connected to the VGA mating connector 6525 via cable 6523 so that the palette 4000 derives its dot clock from the VGR board 6505 and is also synchronized with the VGA pixels. The cable 6523 not only sends pixels on lines VGA0-7, but also sends VGA horizontal and vertical synchronization signals which are selected by a multiplexer 6611 of Figure 27 and input to HSYNC and VSYNC inputs of the palette 4000. The VGA blanking signal is also provided by cable 6523. Advantageously, the function of the multiplexer 6611 is implicitly implemented by tri-state buffers on the VGA board 6505 and in the graphics processor 120, whereas both the BLANK- and VGABLANK- blanking signals are selected on-chip in the palette device 4000 according to the preferred embodiment because of their far more critical timing.

The palette device 4000 has a nibble mode that includes the enhanced computer graphics system of Figure 28. In Figure 28, the host computer 110 provides data to the GSP 120 over the host bus 115. The GSP 120 controls two VRAMs 130A and 130B. The VRAM 130A has four VRAM sections with 4-bit, nibble-wide shift registers 139A (not shown) that operate in parallel to provide 16 bits of output coupled to the 4 high nibbles of each byte of a 4-byte wide input memory 4011 in the palette 4000 that provides the monitor 170. VRAM 1308 also has four VRAM sections, each with a nibble-wide output and has its 16 bits of output connected to each of the 4 low nibbles from the 4 bytes of input memory 4011. In nibble mode, palette 4000 can switch between VRAM 130A and VRAM 1308, for example, to switch between two images. The nibble flag NF input signal controls the switch, since an H state of NF selects the 4 high nibbles as the input signal and a L state of NF selects the 4 low nibbles as the input signal. Advantageously, the same pair of VRAMs 130A and 1308 in the same system, but loaded with different nibbles, can be used to generate 8-bit color codes for one image instead of 4-bit color codes for two images. To accomplish this latter two-image operation, control register 4371 is loaded with mode bits that instruct memory 4011 to provide color codes in four 8-bit bytes, and the nibble mode bit is set to zero in another control register 4398, as described further in connection with Table 6.

In an alternative nibble design, the high and low nibbles are placed in opposite halves of the input memory 4011. A selector circuit is designed to have modes which select either the high or low nibble, or which combine nibbles from the high and low halves if necessary. In either the preferred HLHLHLHL embodiment or the alternative HHHHLLLL embodiment, or in any other embodiment having a mixture of nibbles, palette 4000 advantageously provides a nibble circuit responsive to an HL state of a nibble input signal and connected between input memory 4011 and lookup table memory 4021 for passing a high nibble from a plurality of bytes in input memory to lookup table memory, or a low nibble from a plurality of bytes in memory to lookup table memory, depending on the H or L state of the nibble input signal.

In the preferred embodiment of the pallet 4000, the H/L nibble NF input signal of Figure 28 is functionally combined with the SSRT input signal of Figure 22. Figure 31 shows these inputs combined as a programmable nibble select port SSRT/NF, the function of which is established by a control register 4398, see Table 6. A variety of functionality for a port means that an extra port does not have to be provided, thus increasing the functionality of the pallet 4000, while specifying a maximum number of ports possible for application purposes for the package.

These SSRT and nibble mode functions in the present embodiment can be considered mutually exclusive, since SSRT is useful at resolutions such as 1280 x 1024 pixels and the nibble flag is useful at resolutions such as 1K x 768. The first time SSRT pulse insertion is useful is at higher resolutions than those at which a nibble flag is used. These occur at different resolutions because 1280 is the line resolution, which is not a power of 2. This means that if a VRAM designed to store a scan line 2048 pixels wide is used, then the VRAM space could not be used efficiently unless the partial shift register transfer is used as in Figures 1 - 24. The end of the line coincides with the beginning of line 1, and the entire image is compressed in the VRAM. So of 2048, the first 1250 are line 1, the next 768 complete that 2048, and the rest are on the next line, and the tap point is different from line to line.

Nibble mode is not limited to low resolutions, but is particularly useful for low-end systems with four bits per pixel spread over a wider (e.g. 32 bit) data path. As an option in such a low-end system, the user would find it desirable to add a module which adds another additional 4 bits per pixel over this 32 bit data path. The nibble flag allows an additional module from a low-end system, such as in Figure 28, to be plugged in to provide either or both of a switchable 2-image nibble pixel or 8-bit pixel capability by adding the VRAM 130B and without changing connections from the VRAM 130A already present to the palette. Thus, there is a practical and technological dividing line that allows a combination of the two functions as if they were mutually exclusive.

Figures 29 and 30 show various implementations of an image system processor with different applications. For example, Figure 29 shows a personal desktop image computer which has a variety of input and output devices. The system acts as a personal computer or workstation, facsimile system, printer system, and OCR (Optical Character Recognition) system and general image recognition system all in one. As shown, an object or document 4908 for copying is imaged or captured with optics 4907 and image sensor CCD 4906 which is a charge coupled device. CCD 4906 acts as an example of a light detecting device which is arranged to generate an electrical input signal in response to an image provided to the light detecting device. This captured information is then converted from analog to digital information with A/D data acquisition unit 4904 which provides captured digital information to the ISP/Memory 4900 image system processor of European Patent Application No. 0429733 published June 5, 1991. The ISP/memory 4900 is one of many possible examples of processing circuitry coupled to the light sensing device to generate a display control signal and color codes for representing color information in response to the image.

The controller device 4905 provides the necessary timing signals for both the CD unit 4906 and the printing device 4909. This printing device provides documents 4910. Another input or output possibility is a telephone line, shown by the modem 4901, for establishing communication with other units. The modem 4901 is connected to the ISP/memory 4900 for transmitting color information in color data words to a communication path such as the telephone line or a radio link or another computer or electronic device. The control console 4902 suitably consists of a keyboard, mouse or other visual devices previously described. The LCD or CRT display 4903 is used to provide information to the user. The LCD liquid crystal display 4903, like the ISP/memory 4900 and the printing assembly 4909 are connected by an image information bus containing processed image data. The palette device 4000 is fed by the ISP/memory 4900 and in turn provides a display output to a color display device 4921, such as a raster scanned CRT monitor.

Figure 30 describes an application of an ISP/storage 5200 in a network configuration with a host 5205 which image information is collected off-line either remotely or at a central office and then distributed to buffer 5201 and then used by the image PC configuration to provide information to the image system processor 5200. An alternative method of obtaining information is via a selectable camera 5211 or scanner 5207 operating in conjunction with the preprocessor 5206. This version of an image system advantageously allows for sharing of resources by network image collection devices. A printer port is also provided via a printer interface 5203 and its connection to the printer mechanism 5204 which allows the user to print compound documents containing textual and graphic information in addition to images or enlarged images via the image system processor 5200. The memory 5202 supplements the memory in the ISP 5200. The palette device 4000 is connected to a system bus 5213 and in turn provides analog color signals to a color display device 5221. Although this device 5221 is shown as a CRT monitor, it may also be any color display device, such as a color printer enhanced by looking up color data words in response to color codes.

In operation, the camera 5211 captures an image of a hand H showing two fingers raised upward to communicate the number 2 or a V for victory. The preprocessor 5206 and the ISP 5200 execute image sharpening algorithms and Image recognition routines are run on the sharpened image. The system displays a color image 5231 of the upraised hand H with an attractive multi-color graphic background 5233 and an alphabetic overlay of the number TWO 5235 recognized by the system.

The compact structure of the image processing system, where parallel processing and memory interaction are all available on a single chip, coupled with a wide flexibility of processor memory configurations and operating modes, all of which are chip controlled, contributes to the ability of the image processing system to accept image data input as well as ASCII input, allowing the two data types to be used simultaneously. The Palette 4000 further increases the flexibility and functionality of the image processing system.

The user can use spreadsheets and other information-receiving means to obtain information from a keyboard, or in the traditional manner, in ASCII code, as well as from a visual or video source, such as a 5211 camera or video recorder device, or any other type of video input using a picture code input. The video input signal can be recorded and stored on tape, disk, or any other medium in the same manner as information is currently stored for delivery to a computer.

Some of the features that an imaging system can have are 1) acquiring images from cameras, a scanner, and other sensors; 2) understanding the information or objects in a document; 3) extracting important information from a document or an image; 4) navigating a database to combine images and text documents; 5) providing advanced imaging interfaces such as gesture recognition.

The system is useful for providing instant databases because the information brought into the system can be read and the information content can be immediately abstracted without further processing by other systems. This provides a database that can be easily accessed by a match of certain words, none of which have been identified prior to storage. This can be extended beyond words to geometric shapes, images and can be useful in many applications. For example, a system can be designed to scan a catalog or newspaper to find a certain object, such as all the trees or all the red cars or all the trucks over a certain size on a highway. Conceptually, a database is then formed by words, objects and shapes which the image processor abstracts and makes useful to the user.

One use of such a system with imaging capability is that both still and moving images and videos can be integrated into a system or into any document simply by scanning the image through the system. The information is then abstracted and the output made available to the imaging system for further processing under the control of the user.

One of the reasons why so much imaging capability is available under the system shown is that the single chip contains 5200 different processors operating in parallel together with different memories, all accessible under a crossover switch which allows essentially instantaneous rearrangement of the system. This gives a level of power and flexibility not previously known. This then enables an immense increase in the level of image processing capability which can be used in conjunction with other processing capability to provide a type of service not previously possible. An example of this would be the restoration of photographs or other images, or the cleaning of fax documents so that extraneous material in the background is removed to produce a received image as clear as or clearer than the transmitted image. The entire system can be packed into a relatively small package, primarily because of the processing capability combined in one operating unit. Bandwidth limitations and other physical limitations such as wiring connections are eliminated.

An extension of the concept would have the image system built into a small unit that can be placed on a hand and that has replaced the large video display with a small flat panel display so that the user can slide a finger across the surface of the display for input, as shown in Figure 30. The image system discussed previously detects the various movements and translates the movements into an input signal. This effectively removes the problems of keyboards and other mechanical input devices and replaces them with a visual image as an input signal. The input signal in this case could also be a display that serves a dual purpose. This then makes optical character recognition an even more important tool than has been used to date.

In the current improved end chip 4000, the architecture is free of horizontal frequency clock distribution. Applications in CAD/CAM workstations, image and video processing are suitable for this architecture.

In Figure 31, a programmable color palette chip 4000 has an input memory 4011 connected to a 32-bit wide set of input terminals P0 through P31 and to low-active inputs HSYNC-, VSYNC- and BLANK- from bus 124. A register map 4013 has inputs for read and write strobes (RD-, WR-), four register selection inputs RS0 to RS3 to a decoding and control circuit 4015 and data connections D0-7 to bus 122 for loading or programming the palette chip 4000.

A circuit 4015 configures the palette 4000 on startup and return from RESET and also has an 8/6 select pin. The 8/6 pin is used to select an 8- or 6-bit wide data path to a 256x24 color palette RAM 4021. When the 8/6 input is held low, data on the lowest 6 bits of the data bus is internally shifted up 2 bits to occupy the upper 6 bits, and the lower 2 bits are then set to 0. This operation uses the maximum range of the DACs (digital-to-analog converters) 4031, 4033 and 4035.

A clock selector circuit 4040 has 5 clock inputs CLK0-3 and CLK3- from dot clocks 4100 of Figure 25 and is programmed by the input clock selection register ICS4361. The clock selector circuit 4040 supplies clock pulses to programmable frequency divider, also called clock control block 4041, which is programmed by decoding from an output clock selection register OCS 4363. Two buffered outputs 4341 and 4343 for the shift clock SCLK and video clock VCLK are provided by the clock selector circuit 4041.

The clock source used at power-up is specified by input connectors and can also be overridden by later software selection. A dot clock frequency is the pixel rate for the monitor 170.

Above about 100 MHz, ECL oscillators are currently more readily available than TTL oscillators. Thus, the Palette 4000 can preferably accept either a single-ended TTL input signal or a differential input signal, which is the standard mode of input for ICL oscillators, which provide two signals that are inversely to each other to achieve common mode rejection. This requires two terminals CLK3 and CLK3-. Thus there are two terminals that are driven to receive, for example, a 135 MHz dot clock rate. By programming the ICS 4361, the CLK3 and CLK3- terminals can also be configured to single ended TTL for improved clock input flexibility.

Since different screen resolutions require dot clock rates that are not multiples of each other, the present selection circuitry offers an advantage over an alternative embodiment of a frequency divider circuitry alone for generating different dot clock frequencies. It is believed that the use of multiple oscillators and a selector circuit 4040 provides a more stable clock than the alternative embodiment of a phase-locked loop which takes an input oscillator frequency and multiplies it to a higher frequency level. However, now in the future, PLL technology may offer more stability for video purposes at the higher frequency level thus obtained and thus is an alternative embodiment.

In the embodiment of Figures 25 and 31, a plurality of desired frequencies are selected. Each frequency corresponds to a desired resolution of the monitor as a type of video display 170. Thus, a 640x480 resolution requires a 25 MHz oscillator. A 1024x768 resolution is obtained with a 64 MHz oscillator. In other words, the monitor is supplied with a dot clock rate of 64 MHz to obtain the latter resolution.

Today's resolutions from 320x200 up to 1600x1200 and future improvements are effectively supported by the Palette 4000. The Palette 4000's clock selection feature allows programming for use in improving a wide variety of systems of different resolutions while improving their application range.

For example, medical imaging technology requires high resolution, and processor speed is of lesser importance. A trade-off is involved in that higher resolution implies many pixels and requires a large amount of processor power to produce them. On the other hand, CAD/CAM (computer-aided design and manufacturing) applications require fast draw rates, and lower resolutions are acceptable. To support a variety of hardware and software applications, the Palette 4000 desirably supports a variety of resolutions. Each of these resolutions implies a specific dot clock input frequency.

The multiplexer circuitry MUX 4051 advantageously configures the palette 4000 to the amount of RAM available. For example, if only 512K of memory were available, a 1024x768 mode with 4 bit planes could be implemented using a 16-bit wide pixel bus connected to inputs P0-P15. If at a later time an additional 512K of memory were added, the additional 16 bits P16-31 would be used and 1024x768 mode with 8 bit planes would be implemented without any increase in pixel bus speed.

The shift clock SCLK and video clock VCLK are programmably divided from the dot clock by ratios as shown in Figure 3b. The division ratio of the dot clock to the shift clock is equal to the number of pixels per bus load, since the shift clock-related pulse LOAD inputs several pixels simultaneously into the input memory 4011, while the dot clock allows the faster multiplexed transfer of color codes pixel by pixel. Pixels to the palette RAM 4021 through the circuit 4021.

The register map 4013 contains an input clock select register 4361, an output clock select register 4363, a MUX control register 4371, a read mask register 4353, a page register 4399, a RAM address register 4351 for read and write mode, a color palette data holding register 4391 for inputting R, G, B bytes into the RAM 4021, a general control register 4398 which, among other things, configures the logic 4393 for synchronous output, and test register 4395 for accumulation values and analog comparisons.

Figure 31 also shows a blanking sampling circuit 4384. A selector circuit 4386 selects a VGABLANK- or BLANK-. The blanking signal for VGA has a fixed switch-selected delay in circuit 4321. The blanking signal BLANK- passes through a variable delay circuit of 0-32 dot clocks, which depends on the period mode, and then through the delay in circuit 4321. The synchronization signals VSYNC- and HSYNC- are delayed by a similar mode-dependent delay, and then by a fixed switch-selected delay in circuit 4322, 4321, which the synchronization logic 4393 provides to the HSYNCOUT and VSYNCOUT outputs.

The TLC34075 graphics interface chip is designed to provide low system cost with a higher level of integration by incorporating all of the high-speed timing, synchronization and multiplexing logic normally associated with graphics systems into one device, thus greatly reducing chip count. Since all high-speed signals (excluding timing source) are contained on-chip, RF noise considerations are simplified. Maximum flexibility is provided by the pixel multiplexing scheme, which allows allows 32-, 16-, 8- and 4-bit pixel buses to be attached without any circuit modification, and this allows the system to be easily reconfigured for different amounts of available video pixels. The data can be split into 1-, 2-, 4- or 8-bit planes. The device is software compatible with the IMSG176/8 and Bt4/6/8 color palettes. See Figure 32.

The device has a separate VGA bus which allows data from the auxiliary connector of most VGA-supported personal computers to be input directly into the palette without the need for external data multiplexing. This allows a replacement graphics board to remain "downwards compatible" by using the existing graphics circuitry often located on the motherboard.

A real color mode is also provided, in which 24 (3x8) bits of color information are transferred directly from the pixel port to the DACs. In this operating mode, an overlay function is provided using the eight remaining bits of the pixel bus.

The TLC34075 has a 256x24 color lookup table with three 8-bit video DACs capable of directly driving a double terminated 75Ω line. Synchronization generation is included on the green output channel. Hsync and Vsync are input by the device and optionally inverted to indicate the screen resolution for the monitor. A palette page register is used to supply the additional bits of the palette address when 1-, 2-, or 4-bit planes are used. This allows the screen colors to be changed with only one MPU write cycle.

Clocking is provided via one of four inputs (three TTL and one ECL/TTL compatible) and is controlled by software selectable The video and shift clock outputs provide a software-selected division ratio of the selected clock input signal.

The TLC34075 can be connected directly to the serial port of VRAM devices to eliminate the need for any discrete logic. Support for partial shift register transfers is also provided. Circuit Description MPU Interface

The processor interface is controlled via read and write strobes

four register select pins (RS0-RS3) and the 8/6 select pin. The 8/6 pin is used to select between an 8- or 6-bit wide data path to the color palette RAM. With the 8/6 pin held low, data on the lowest 6 bits of the data bus is internally shifted up 2 bits to occupy the upper 6 bits at the MUX output, and the lower 2 bits are then set to zero. This operation is performed to utilize the maximum range of the DACs.

The internal register map is shown in Table 1. The MPU interface operates asynchronously, with data transfers synchronized by internal logic. All register locations support read and write operations. Table 1: internal register planColor palette

The color palette is addressed by an 8-bit incremental register for reading/writing data to/from RAM. These registers are automatically incremented after a RAM transfer to allow the entire palette to be read/written with only one access to the address register. When the address register increments above the last location in RAM, it is reset to the first location (address 0). All read and write accesses to RAM are asynchronous to SCLK, VCLK or the dot clock, but are performed within a dot clock and thus cause no noticeable disturbance on the display.

The color RAM is 24-bits wide for each location and 8-bits wide for each color. Since all MPU access is 8-bits wide, the data stored in the color palette will be 8 bits even if a 6-bit mode is selected (8/6- = 0). If a 6-bit mode is selected, the two MSBs in the color palette will have the values written in. However, if read back in 6-bit mode, the 2 MSBs will be zeros. The output NUN after the color palette will shift the 6 LSB bits to the 6 MSB positions and fill the 2 LSBs with zeros and then input them to the DAC. The test register and the 1s accumulation register will both take data before the output MUX, giving the user maximum flexibility.

Color palette access is described in the following two sections. Writing to the color palette RAM

To load the color palette, the MPU must first write the address where modification is to start into the address register (write mode). This is followed by three successive writes to the palette holding register with 8 bits of red, green and blue data. After the blue write cycle, the three color bytes are truncated into a 24-bit word and are written to the RAM location specified by the address register. The address register then increments to the next location, which the MPU can modify by simply writing another sequence of red, green and blue data. A block of color values in consecutive locations can be written by writing the starting address and performing continuous red, green and blue write cycles until the entire block has been written. Reading from color palette RAM

Reading from the palette is accomplished by writing the location to be read to the address register (read mode). This then initiates a transfer from the palette RAM to the holding register and then an implementation of the address register. Three consecutive MPU reads from the holding register will then generate red, green and blue color data (6 or 8 bits depending on the 8/6 mode) for the specified location. After the blue read cycle, the contents of the color palette RAM are copied to the holding register at the address specified by the address register and the address register is incremented again. As with writing to the palette, a block of color values can be read at consecutive locations by writing the starting address and performing continuous red, green and blue read cycles until the entire block has been read. Palette Page Register

The palette page register appears as an 8-bit register on the register map (see Table 1). Its purpose is to provide high speed color changing by eliminating the need for palette reloading. When using 1-, 2-, or 4-bit planes, the additional planes are provided by the page register, e.g. when using 4-bit planes, the pixel inputs would specify the lower 4 bits of the palette address, with the upper four bits being specified by the page register. This gives the user the ability to select 16 "palette pages" with only one chip access, thus allowing all screen colors to be changed at the line rate. Bit/bit correspondence is therefore used in the above configuration, and page register bits 7-4 would on palette address bits 7-4. This is shown below.

Note that the additional bits from the page register are inserted before the read mask and are therefore subject to masking. Table 2: Palette page register bit arrangementInput/output clock selection and generation

The TLC 34075 provides a maximum of 5 clock inputs. Three of these are assigned to TTL inputs. The other two can be selected as either an ECL input or two extra TTL inputs. The TTL inputs can be used for video rates up to 80 MHz, above which an ECL clock source can be used, although the ECL clock can also be used at lower frequencies. The dual mode clock input (ECL/TTL) is primarily an ECL input, but can be used as a TTL compatible input if the input clock select register is so programmed. The clock source used at power up is CLK0, an alternative source can be selected by software during normal operation. This selected clock input signal is used unmodified as the dot clock (representing a pixel rate for the monitor). However, the device allows the user performs programming of SCLK and VCLK outputs (shift and video clocks) using the output clock selection register. The input/output clock selection registers are shown in Tables 3a and 3b.

SCLK is intended to drive the VRAMs directly, and VCLK is intended to work with the video control signals such as BLANK and SYNCs. Although SCLK and VCLK are intended to be a general purpose shift clock and video clock, they can also be considered to work directly with the TMS340x0 GSP family. Thus, although SCLK and VCLK can be chosen independently, there is still a relationship between the two, as discussed in the following description. This system consideration has been covered in the design, allowing users a maximum degree of freedom.

Internally, both SCLK and VCLK are generated from a common clock counter that counts on the rising edge of DOTCLK. When VCLK is asserted, it is in phase with SCLK, as shown in Figure 33 as an example. Table 3a: Input Clock Select Register FormatNote 1:

Register bits 4, 5, 6 and 7 have "no meaning" states Note 2:

When selecting the clocks from one mode to another, a minimum of 30 ns is required before the new clocks are stabilized and running. Table 3b: Output Clock Output Register FormatNote 1: Register bits 6 and 7 have "no meaning" states. Note 2:

When the clocks are selected from one mode to another, a minimum of 30 ns is required before the new clocks are stabilized and running. SCLK

Data is stored within the device at the rise of "LOAD" (which is essentially the same as SCLK, but is not disabled during a BLANK active period) Therefore, SCLK is set as a function of the pixel bus width and the number of bit planes. SCLK can be selected as a divider of 1, 2, 4, 8, 16, or 32 of the dot clock. If SCLK is not used, the output is turned off and held low to protect against "locking" the VRAM due to invalid SCLK frequencies. SCLK is also held low during the BLANK active period. The timing is designed so that the first pixel data is brought out of the VRAM when BLANK is disabled and ready for display. When partial shift register operation is used, SCLK is also taken into account when working with the SSRT input signal.

The default setting, as used in mode 0, is 1:1.

Reference is made to Figure 34 for the following explanation of the timing.

The falling edge of VCLK is used internally by TLC34075 to sample and hold the BLANK- input signal. When BLANK- becomes active, SCLK is deactivated as soon as possible. In other words, if the last SCLK is high while BLANK- is low, that SCLK will be allowed to finish its cycle low, and then the SCLK signal will be held low until the sampled BLANK- goes back high to activate it again. The VRAM's shift register will be refreshed during BLANK- active periods, and the first SCLK will be used to clock the first pixel data from the VRAM. The internal pipeline delay of the BLANK- input signal is designed to align with data from the DAC output to the monitors. The logic described above works with the situations where the SCLK period is shorter than, equal to and longer than the VCLK period.

Figure 37 shows the case when the SSRT (Partial Shift Register Transfer Function) is enabled. A SCLK with a minimum 15 ns pulse is generated from the rising edge of the SFLAG input signal with specified delay. This is designed to meet the VRAM timing requirement and this SCLK will replace the first SCLK in the case of regular shift register transfer as described above. For the detailed explanation of the SSRT function, refer to the following. VCLK

VCLK can be selected as a divider of 2, 4, 8 or 16 of the dot clock and can also be held at logic "1". The default is to hold VCLK at logic "1" since it is not used in VGA pass-through mode. VCLK is mainly used to generate the control signals (BLANK, HSYNC, AND VSYNC) by the GSP or certain customer designed control logic. As can be seen from Figures 34-37, VCLK must be enabled because the control signals are sampled by VCLK.

Figure 34 shows: SCLK/VCLK control timings (if SSRT is disabled, SCLK frequency = VCLK frequency)

Either the SSRT function is disabled (general control register bit 2 = 0) or the SFLAG input is low if the SSRT function is disabled (general control register bit 2 = 1). (SCLK frequency = VCLK frequency) SCLK/VCLK and TMS340x0

Although the SCLK and VCLK of the TLC34075 are designed for all graphics systems, they are also tightly coupled with TMS340x0 graphics system processors. All timings that work on the TMS340x0 have been taken into account. There are a few points that need to be explained for the convenience of user applications. VCLK

All control signals (BLANK-, HSYNC- and VSYNC-) in TNS340x0 are triggered and generated from the falling edge of VCLK. The fact that TLC34075 uses the falling edge to sample and hold the input signal BLANK- will give users maximum freedom in selecting the frequency of VCLK and connecting TLC34075 to 340x0GSP without any connection logic. The minimum VCLK frequency is selected to be longer than the maximum VCLK period required by TNS340x0.

On the TMS340x0, the same falling edge of the VCLK that generates BLANK- also creates a request for a screen refresh at the same time. If the VCLK period has been selected to be longer than 16TQ's (TQ is the period of TMS340xCLKIN), it is possible that the last SCLK could be mistakenly used to transfer the VRAM data from memory to the shift register with the last pixel transfer. The first SCLK for the next scan line will then shift the pixel data off the line, and the screen will mistakenly start at the second pixel. SCLK and SFLAG

SCLK works well with the "current-10" and slower VRAMs. In the situation of partial shift register transfer, a SCLK is generated between the regular shift register transfer and the partial shift register transfer to ensure the appropriate operation. SFLAG is provided for this purpose. SFLAG can be generated from a PAL and triggered by the rising edge of the TR-/QE- signal, or the rising edge of the RAS- signal of the first regular shift register transfer cycle TR-/QE- can be used if the minimum delay time of the VRAM, namely TRG- to H until SCLK to H, can be satisfied by the PAL delay, otherwise RAS- can be used. Multiplexing Scheme

The TLC34075 offers a very versatile multiplexing scheme, as shown in Tables 4 and 5. Using on-chip multiplexing allows the system to be reconfigured to the amount of RAM available, for example, if only 256K bytes of memory were available, an 800x600 mode with four bit planes using an 8-bit wide pixel bus. If at a later date 256K bytes were added to an additional 8 bits of the pixel bus, the user could have the option of using 8-bit planes at the same resolution or 4-bit planes at a 1024x768 resolution. If an additional 512K bytes were added to the remaining 16 bits of the pixel bus, the user could have the option of 8-bit planes at 1024x768 or 4-bit planes at 1280x1024. All of the above could be achieved without any hardware modification and without any increase in the speed of the pixel bus.

The input MUX can accept data at a frequency of 80 MHz. This applies to all modes including VGA pass-through mode. VGA pass-through mode

Mode 0 is the VGA pass-through mode and is used to emulate the VGA modes of most personal computers. The advantage of this mode is that it can accept data supplied to the device on the auxiliary connector of most VGA compatible PC systems on a separate bus, thus not requiring external multiplexing. This feature is particularly useful in systems where the existing graphics circuitry is on the motherboard; in this case it allows the graphics card to be omitted, maintaining compatibility with all existing software by using the "on-board" VGA circuitry but passing the resulting bit-level data through the TLC34075. This is the default mode at power-up. When this VGA pass-through mode is selected after power-up, the clock select register, general control register and pixel read mask register also how the power-on default states are set automatically.

Since this mode is designed with the extra connector philosophy, all timing is referenced to CLK0, which is used as the default for VGA pass-through mode, while for all other normal modes CLK0-3 are just the OSC sources for generating DOTCLK, VCLK and SCLK, with all data and control timing being referenced to SCLK instead. Multiplexed modes

In addition to the VGA pass-through mode, there are 4 available multiplexing modes, all of which are referred to as NORMAL mode in the description. In each mode, a pixel bus width of 8, 16 or 32 bits can be used. Modes 1, 2 and 3 additionally support a pixel bus width of 4 bits. The data should always be delivered on the most significant bits of the pixel bus. This means that if 16 bits are used, the data is delivered on P31-P16, 8 bits on P31-P24 and 4 bits on P31-P28. All unused PBUS pins must be connected to GND.

Mode 1 uses a single bit plane to address the color palette. The pixel port bit is entered in bit 0 of the palette address, with the 7 bits of high order address defined by the palette page register. This mode has applications in high resolution monochrome applications such as desktop publishing. This mode allows the maximum amount of multiplexing with a 32:1 ratio, thus providing a pixel bus rate of only 4 MHz under a screen resolution of 1280x1024. Although only a single bit is used, changing the palette page register below the line frequency would allow that 256 different colors are displayed simultaneously with two colors per line.

Mode 2 uses 2-bit planes to address the color palette. These two bits are input to the lower order address bits of the palette, with the 6 higher order address bits defined by the palette page register. This mode allows a maximum divider ratio of 16:1 on the pixel bus and is essentially a four-color alternative to Mode 1.

Mode 3 uses 4-bit planes to address the color palette. The four bits are entered into the low-order address bits of the palette, with the 4 high-order address bits defined by the palette page register. This mode provides 16 pages of 16 colors and can be used with SCLK division ratios from /1 to /8.

Mode 4 uses 8-bit planes to address the color palette. Since all 8 bits of the palette address are specified by the pixel port, the page register is not used. This mode allows dot clock to SCLK ratios of 1:1 (8-bit bus), 2:1 (16-bit bus), or 4:1 (32-bit bus). Therefore, in a 32-bit configuration, a 1024x768 pixel screen can be implemented with an external data rate of only 16 MHz. Real color mode

Mode 5 is a real color mode where 24 bits of data from the pixel port are transferred directly to the DACs, but with the same amount of pipeline delay as the overlay data and the control signals (BLANK and SYNCs). In this mode, overlay is possible using the remaining 8 bits of the pixel bus to address the Palette RAM is provided, resulting in a 24-bit RAM output signal which is then used as overlay information for the DACs. If all overlay inputs (P7-P0) are at logic 0, no overlay information is displayed, whereas if a non-zero value is entered, the color palette RAM is addressed and the resulting data is then input via the DACs with priority over the real color data.

The real color mode data input operates in 8-bit mode. In other words, if only 6 bits are used, the two MSB inputs for each color can be tied to GND. However, the palette used by this overlay input signal is still governed by the 8/6 input terminal, and the output MUX will select 8-bit data or 6-bit data accordingly.

For the colors passed, P8-P15 pass RED data, P16-P23 pass GREEN data, and P24-P31 pass BLUE data. Special nibble mode

Mode 6 is a special nibble mode that is enabled when the SNM bit (bit 3) is set and the SSRT bit (bit 2) is reset in the general control register. When the special nibble mode is enabled, the MUX control register setting is ignored and it takes precedence over the other modes. The SFLAG/NFLAG input signals are then used as a nibble flag to indicate which nibble of each byte holds the pixel data. Conceptually, this special nibble mode initiates an additional implementation of the 4-bit pixel mode with a 16-bit bus width (while all 32 inputs P0-P31 are connected as 4 bytes), but in this case the 16-bit data bus is found on the lower/upper nibble of each of the four bytes. This will be described further later. Since this mode uses 4-bit planes for each pixel, they are entered into the low-order address bits of the palette, with the 4 high-order address bits defined by the palette page register. Multiplex Control Register

The multiplexer is controlled by an 8-bit register in the register map (see Table 1). The bit fields of the register are as follows: Table 4: Mode and bus width selectionNote 1: Register bits 6 & 7 have "no meaning" states Note 2:

"Data bits per pixel" is the number of bits of pixel port information used as color data for each pixel displayed, often referred to as the number of bit planes. This can be color palette address data (modes 0 - 4, 6) or DAC data (mode 5). Note 3:

"SCLK division ratio" is the number used for the output clock select register, and it indicates the pixels per bus load, which is the number of pixels generated by each SCLK, for example, with a 32-bit pixel bus and 8-bit planes, 4 pixels are generated at each bus load (or SCLK). Note 4:

An overlay is implemented in real color mode with the remaining 8 bits of the pixel bus. Note 5:

Normally, the "physical connection" of the pixel bus is equal to the "pixel bus width". The only exception is the special nibble mode. Refer to Table 5 and Section 1.9 for further details.

Note 6:

This column is a reference to a column of Table 5 where the actual manipulation of the pixel information is shown. See below.

Table 4 is designed for input MUX control. However, it provides a "SCLK division ratio" that is used for input MUX control and also for user information The SCLK output signal depends on the bits programmed in the output clock selection register, as shown in Table 3b.

The use of pixel and overlay buses in the above modes of operation is shown in Table 5. The table shows what data is extracted from the pixel information at each stage. The operation is tied to a column of the table (see reference of Table 4). On each rising SCLK, data is latched internally from the pixel input port and this also initiates the first row of Table 5. Successive rows are executed on each pixel clock. Once the column is completed, the SCLK will assert another bus load and therefore repeat the column. Table 5: Port data for pixel distribution. (2) Note 1:

In this mode of operation, the ports P0...P7 are used to generate overlay data. This operation can be disabled either by grounding the pixel inputs P0...P7 or by disabling the read mask. For the passed colors, P8...P15 are passed to the RED DAC, P16...P23 to the GREEN DAC and P24...P21 to the BLUE DAC. Note 2:

The lower number is the LSB and the upper number is the MSB. For example, in configuration o (MUX control register = 1D (HEX)), P8 is the LSB and P15 is the MSB in the second channel, and to address palette RAM location 21 (HEX), P8 and P13 must be high. The input data is scanned from the low-numbered channels to the high-numbered channels. For example, if configuration p is programmed (MUX select register = 1E (HEX)), channels P0...P7 are scanned first, followed by P8...P15, P16...P23, and the last channel scanned will be P24...P31. The same rule applies for VGA0-7.

As an example of using Tables 4 and 5, if the user wants to design a system with 8 data bits per pixel and use as low an SCLK rate as possible, the maximum pixel bus width, which is 32, should then be selected and the SCLK division ratio can then be /4 of the DOTCLK. From Table 4 we know that we should write lE (HEX) into the MUX control register. We then find that the configuration p in Table 5 should be used, which tells us that P0...P7 should be connected to the earliest displayed pixel plane, followed by P8...P15, P16...P23 and then P24...P31 as the latest displayed pixel plane. To set SCLK, the output clock selection register must also be programmed. In this case, 12 (HEX) should be used (assuming that SCLK is also programmed as DOTCLK/4). There is one more fact to check, namely an assurance that the special nibble mode is disabled.

When the MUX control register is loaded with 2D(HEX), it is a VGA mode and the TLC34075 goes to its default state, which is the same as when it was powered on. For further details, refer to the reset description. Read Masking

The read mask register is used to enable or disable a bit level from addressing the color palette RAM. Each palette address bit is logically ANDed with the corresponding bit from the read mask register before the palette is addressed.

This function is executed after the page register bits are added, and therefore setting the AND mask to zero

result in a unique palette location and will not be affected by accesses to the palette page register. Reset

There are 3 ways to reset the TLC34075:

A. Power-on reset

B. Hardware reset

C. Software reset Power-on reset

There is a POR (Power-On Reset) logic built into the TLC34075. This POR only operates when the power is turned on. However, it is still recommended to set the hardware reset circuit to ensure the reset condition when the power is turned on, as described below.

Once the voltage is stabilized, the default condition for all registers is VGA mode. Hardware reset

Every time user writes to the "Reset State" register [RS3-0 = 1111 (binary)], the written value is ignored, but the TLC34075 is reset. The TLC34075 is reset by any "WR" rising edge as long as the RS3-0 contains 1111 (binary value). The more "WR" edges, the more reliably the TLC34075 is reset. This scheme provides "WR" strobes until the power supply is stabilized, and is Turning on the power if the hardware reset structure is used is recommended.

The default reset conditions for VGA mode and the values for each register are shown below. Software reset

Every time the MUX control register selects VGA mode after power up, all registers are initialized accordingly. Since VGA mode is the default condition at power up and hardware reset, the VGA mode selection in the MUX control register is naturally considered a software reset. Thus, every time the MUX control register receives 2D (HEX) as an input, the TLC34075 will initiate a software reset. VGA Default Conditions

The condition for each register after reset is shown below:

MUK control register 2D (HEX)

Input clock selection register 00 (HEX)

Output clock selection register 3F (HEX)

Pallet side register 00 (HEX)

General Tax Register 13 (HEX)

Pixel Read Mask Register FF (HEX)

Pallet address register xx (HEX)

Pallet holding register xx (HEX)

Test register (points to the color palette red value) Image buffer interface

The TLC34075 generates two clock signals to control the frame buffer interface: SCLK and VCLK. SCLK can be used to clock data directly from the VRAM shift registers. The partial shift register transfer function is also supported. VCLK is used to clock and synchronize the control signals such as HSYNC, VSYNC and BLANK.

The pixel data supplied to the inputs is latched on the rising edge of SCLK in Normal mode, or on the rising edge of CLK0 in VGA mode. Control signals HSYNC-, VSYNC- and BLANK- are sampled and latched on the falling edge of VCLK in Normal mode, while HSYNC-, VSYNC- and VGABLANK- are latched on the rising edge of CLK0. Both data and control signals are queued at the DAC outputs to the monitors via an internal pipeline delay.

The outputs of the DACs are capable of directly driving a 37.5Ω load as in the case of a double terminated 75Ω cable see Figures 38 and 37. Analog Output Specification

The DAC outputs are controlled by 3 current sources (only two for IOR and IOB) as shown in Figure 38. Normally there is a difference of 7.5 IRE between blanking and black levels, which is shown in Figure 39. If a base value of 0 IRE is desired, it can be selected by resetting bit 4 of the general control register. The video output is shown in Figure 40.

A resistor (RSET) is used when connecting the FSADJ terminal and GND to control the size of the full-scale video signal required. The IRE relationships in Figures 39,40 are maintained independent of the full-scale output current.

The relationship between RSET and the full scale output current IOG is:

RSET (Ohm) = K1 x ( VREF (V) / IOG (mA)

The full scale output current on IOR and IOB for a given RSET is:

IOR, IOB (mA) = K2 x ( VREF (V) / RSET (Ohm)

where K1 and K2 are defined as: HSYNC-, VSYNC-, BLANK-

For normal mode, HSYNC- and VSYNC are passed through the TRUE/complementary gates to the HSYNCOUT and VSYNCOUT outputs. The polarities of HSYNCOUT and VSYNCOUT can then be programmed via the general control register. This allows the connected monitor to sense the current screen resolution. However, for VGA mode, the polarities required for the monitor are already provided on the auxiliary connector from which HSYNC and VSYNC- originate, and so the TLC34075 will only pass them on HSYNCOUT and VSYNCOUT without a polarity change. As above and As described in Figures 35, 36, in the normal mode, the input signal BLANK- is sampled and held at the falling edge of VCLK. The input signals HSYNC- and VSYNC- are sampled and held in the same way. However, for VGA mode, they are held at the rising edge of the CLK0 input signal. For all detailed timings, refer to Figure 8. If the MUX control register is 2D (HEX), it is a VGA mode and the input signals CLK0 and VGABLANK- are selected, otherwise VCLK and BLANK- are used.

Due to the pin count limitation, the input signals HSYNC- and VSYNC- will be used by both the VGA and normal modes. If both modes are used on the TLC34075, an external MUX is required to select the setting between VGA and normal SYNCs. MUXOUT- is provided for this purpose.

HSYNC-, VSYNC- and BLANK- all have internal pipeline delays to align the data at the outputs. Due to the sample and hold time delay, it is possible to have active SCLKs after the input signal BLANK- is active. The relationship between VCLK and SCLK, and the internal VCLK sample and hold delay must be carefully checked and programmed. For further details, refer to 1.3 and Figures 35, 36.

As shown in Figure 38, active HSYNC- and VSYNC- will turn off the synchronization current source after the pipeline delay. They are not qualified by the BLANK- signal. In other words, HSYNC- and VSYNC- should only be intended to be active during an active time of BLANK- to ensure proper operation.

To change the polarity of the output signals HSYNCOUT- and VSYNCOUT- in normal mode, the MPU must set the corresponding bits in the general control register. Again, these two bits will only affect normal mode and not VGA mode. These bits default to 1, which means non-inverted.

VRAMs with partial shift register transfer and special nibble mode VRAMs with partial shift register transfer

The TLC34075 has direct support for partial shift register transfer (SSRT) VRAMs. To enable the VRAMs to perform partial shift register transfer, an extra SCLK cycle must be inserted during the blanking sequence. This is initiated when the SSRT enable bit (bit 2) in the general control register is set, but the SMN bit (bit 3) is reset and a rising edge of the SFLAG/NFLAG input signal is detected. A SCLK pulse is then generated within 20 ns and a minimum logic high duration of 15 ns is provided to satisfy all the requirements of the -15 VRAM. The rising edge of the SFLAG/NFLAG input signal triggers SCLK, but it must remain high until the end of the active period of BLANK-. It is also the user's responsibility to ensure the delay time of the rising edge of this SCLK, which runs up from the TRG- of the VRAM, by controlling the SFLAG rise time. The waveform and relationship of the SCLK/SFLAG input signal and the BLANK- is shown below in Figure 41:

If the SSRT function is enabled but the SFLAG/NFLAG is held low during BLANK-, the SCLK runs just as if the SSRT function is disabled. The SFLAG/NFLAG- input signal must be held low when BLANK- is inactive For further system details, see Figures 34 and 35. Special nibble mode

There is a special nibble mode in the TLC34075. This mode is enabled when the SNM bit (bit 3) of the general control register is set but the SSRT (bit 2) is reset. The SFLAG/NFLAG input is then used as a nibble flag to indicate which nibble holds each byte of pixel data. Conceptually, this special nibble mode initiates an additional modification of the 4-bit pixel mode with a 16-bit bus width (while all 32 inputs P0...P31 are connected as 4 bytes), but in this case the 16-bit data is found on the lower/upper nibble of each of the four bytes. The pixel data is distributed as shown in the following table:

The NFLAG is not stored within the TLC34075. Therefore, it should remain at the same level during the entire active playback period and only change level during the active time of BLANK-. Refer to Figure 42, which is similar to Figure 34, except that the signal timing relationship from BLANK- to NFLAG is explained. The NFLAG must meet the settling time and hold the data long enough to ensure that no pixel data is missing.

As users can see, this special nibble mode will operate at the line rate when BLANK is active. However, the typical application of this mode would be dual frame buffers with 4-bit pixel-wide data. Thus, while one frame buffer is being rendered on the monitor, the other frame could be used to capture new image information. NFLAG is then used to indicate which frame buffer is rendering.

Note that SNM and SSRT are mutually exclusive in this example.

The MUX control register must be set as shown in Table 4 for the SCLK division ratio. However, the SNM takes precedence over other MUX selections. In other words, if the MUX control register is set for another mode, but the SMN in the general control register is still enabled, the input multiplexer circuit will take the SCLK division ratio specified by the MUX control register and perform the nibble operation.

During the SNM signal, the input MUX circuit will latch all 8 bit inputs, but only pass the specific nibble. The specified nibble is stored in the 4 LSBs of the next register line after the input latch, and the four MSBs are set in this register. This line register is then passed to the READ MASK BLOCK. With this structure, the palette page register will still function normally, providing good flexibility for the users.

If the general control register bit 3 = 0 and bit 2 = 0 both SSRT and SNM are disabled and the SFLAG/NFLAG input signal is then ignored. MUXOUT output connector

The MUXOUT- pin is a TTL compatible output, it is software programmable and is used to control external devices. The typical applications are to select the HSYNC- and VSYNC- input between VGA mode and normal mode. This input is set low at power-up or when VGA mode is entered for the MUX control register, and it can be set back high if desired. Therefore, this pin follows the status of bit 7 of the general control register and does not involve any other circuitry. It is sufficient to be programmed to anything after power-up or after setting VGA mode (2 D HEX in MUX control register) General control register

The general control register (or control register) is used to control the polarity of HSYNC and VSYNC, to enable partial register transfer, for the special nibble mode, for synchronization control, for the ones accumulation clock source, and for the VGA pass indicator. The bit field definitions are as follows: Table 6. General control register bit functionHSYNCOUT and VSYNCOUT (bit 0 and 1)

A polarity inversion of HSYNCOUT and VSYNCOUT is provided to allow an indication of the current screen resolution for the monitors. Since the polarities for VGA mode are provided on the auxiliary connector, the inputs on the TLC34975 will already have the correct polarities for the monitors. so the TLC34075 simply passes them through with a pipeline delay. These 2 bits only work in normal mode and the horizontal and vertical sync of the input are assumed to be active L input pulses. These 2 bits are active L by default but can be changed by software. Base Value Enable Control (bit 4)

This bit specifies whether a 0 or 7.5 IRE blanking base is generated on the video outputs. 0 IRE specifies that the black and white levels are the same.

0:0 IRE base value

1:7.5 IRE base value (default) Synchronization activation control (bit 5)

This bit specifies whether the SYNC information is to be output on IOG or not.

0: Disable synchronization (default)

1: Activation of synchronization MUXOUT (bit 7)

The MUXOUT bit is essentially an output bit that provides an indication to external circuitry that the device is operating in VGA pass-through mode. This bit does not affect the operation of the device. It is only an output bit. See 1.10

0: MUXOUT- is on L (default in VGA mode)

1: MUXOUT- is on H Test register

There are 3 test functions provided in the TLC34075 and they are all controlled and monitored by this test register: Data flow test, DAC analog test and Shield health test.

This register has 2 ports: one for a control word, which is accessed by writing to the register location, and one for a data word, which is accessed by reading from the register location. Depending on the channel written to the control word, the data read will provide the information for that channel.

The control register is 3 bits long and occupies bits 0, 1 and 2. These specify which of the 8 channels are to be inspected. The following table and state machines will show how each channel is addressed. See Figure 43: Frame Buffer Data Flow Test

For all data going into the DAC (but before the output MUX 8/6 shift), the TLC34075 provides a means to check it. When accessing these color channels, the data going into the DACs should be kept constant for the entire MPU read cycle. This can be done either by slowing down the dot clock or by ensuring that the data is constant for a sufficiently long series of pixels. This read value will be the one stored in the color palette, indicated by the MUX input signal. The read operation will cause a post-increment to show on the next color channel, and the post-increment will jump back from BLUE to RED as shown in the state diagram above. For example, if D2, D1 and D0 were written as 001 (binary), then after three consecutive readings, the values read will be GREEN, BLUE and then RED in that order.

Identification code

The ID code could be used for software identification for a different version or subroutine. The ID code on the TLC34075 is static and can be read without regard to the dot clock or video signals. To be user friendly, the read post increment also applies to the ID register, but once it falls into the color channel, it will not come back and point to ID unless the user writes 001 (binary) to D2, D1 and D0 again. Thus, if the test register is written to 011 (binary) first in D2, D1 and D0, after six consecutive reads, the first value read will be the ID and the last value read will be GREEN.

The ID value defined here is 75 (HEX). Ones accumulation

When 1s accumulation is selected for a specified color by D2, D1, and D0, the specified color value is monitored from the color palette (before the output MUX-8/6 shift operation) to the DAC. The number of 1s for the addressed color value is added to a temporary accumulator. For example, if 41 (HEX) has two 1s, then two will be added to the temporary accumulator if the color palette addressed by the frame buffer input contains the 41 (HEX) value. The falling edge of VSYNC after the internal pipeline delay will be used to transfer the final value to the 1s accumulation register, and the temporary accumulator will be reset for the next screen. The ones accumulation is calculated only when the specified color is selected, i.e. D2-D0 = 100, 101 or 100 (binary), and its operation is disabled when not selected to save power. Thus, the user must wait long enough for the complete screen to be displayed at least once before reading the value. To be user friendly, the post-increment after each read is also provided in the above state diagram: After the value is read, the TLC34075 will point to the next color and calculate the number of ones for the entire screen. The overflow after the 8-bit value is truncated. Due to the speed limitation, a ones accumulation is calculated at a DOTCLK/2 rate. As long as the display pattern for each screen is fixed, the ones accumulation value should remain the same. Otherwise, an error is detected. Since the 1s accumulation value is calculated before the output MUK, an 8-bit value is read and calculated. If the 6-bit mode is selected and the 2 MSBs in the color palette are not initialized with zeros, the 1s accumulation value is Accumulation value nor report for the 8-bit pattern. This provides an additional way to check the color palette.

Ones accumulation is a good test tool for system testing and field diagnostics.

The ones accumulation is refreshed at every VSYNC-, but not at the compound synchronization time, which is also active during HSYNC-. Analog test

This analog test is used to compare the analog RGB outputs to each other and to a 145 mV reference. This allows the MPU to determine whether or not the CRT monitor is connected to the analog RGB outputs and whether the DACs are working. When the analog test is performed, D7-D4 must be set to the desired comparison, while D2-D0 are set to 111 (binary). When the test register is read, D3 will reflect the result. The bit definition is shown below.

The table above lists the valid comparison combinations. A logic one allows this function to be compared: The result is D3. The comparison result is placed in D3 on the falling edge of the BLANK- input signal (before the pipeline delay). To have stable input signals for the comparator, the frame buffer inputs should be set to always point to the same location in color RAM.

For normal operation, D7-D4 in this analog register must be logical 0. Connection description (Figure 45)

The selector circuitry 4051 of Figures 31 and 32 is programmed by the entries in the register map 4013 to operate in any of several modes as defined by Table 4. Although the selector circuitry is shown as a network of multiplexers and some embodiments show the use of logic gate multiplexers, it is believed that a shift register selection circuitry, such as a block shifter, implementing the input latch 4011 and the selector 4051 is even more useful for use at frequencies up to the highest dot clock rates.

In some of the modes, selector 4051 operates as an example of color code transfer circuitry connected between input memory 4011 and lookup table memory 4021 for supplying lookup table memory 4021 from input memory 4011 in a sequential manner with color codes of selectable width spanning the entire bus width. Control register 4371, via decoder circuitry 4052 of Figure 31, configures block shifter to function as the set of multiplexers 4381, 4383, 4385 and 4387 in accordance with the details of selector 4051 of Figure 32.

The multiplexers have select inputs for receiving control signals which operate the multiplexers according to a respective mode established by the contents of the control register 4371. The multiplexers 4381 to 4387 have data inputs connected to the input memory 4011 for the entire bus width 136, and each of the multiplexers has a number 8, 4, 2 or 1 of outputs which are a different submultiple /4, /8, /16 or /32 the width of the 32-bit bus 136. When a given one of the multiplexers 4381-4387 is activated, the decoder and counter circuitry 4052 operates the multiplexer to cyclically and sequentially transfer the contents of the input memory 4011 for the entire width of the bus 136 in sets of parallel bits equal to the number of outputs 8, 4, 2 or 1 of the multiplexer or the multiplexing function of the block shifter to the lookup table memory 4021.

The decoder and counter 4052 may sequentially cycle over part or all of the input memory width, and the entire bus width of the bus 136 may be connected to only part of the memory width. Thus, the bus width to which the multiplexers respond may also be advantageously programmed. In this manner, the selector circuit 4051 and the decoder and counter circuit 4052 operate as an example of an externally programmable bus width coupling circuit connected between the input and the lookup table memory 4021 to pass color codes from the bus 145 according to the bus width programmed or internally/externally provided to the palette device 4000. In the preferred embodiment, the programmable bus widths are powers of 2, and a width of 24 in real color mode. Increasingly smaller bus width selections pass bits from portions of input memory 4011 which, in one example, are increasingly smaller subsets of each other at the end of the most significant bit of memory 4011.

In yet another feature, the decoder or counter 4052 in the special nibbling mode enables the multiplexers to transfer bits from the input memory 4011 by alternately transferring bits, skipping bits, transferring, skipping, etc. Skipping does not in itself result in delay. Although a few modes have been described, it should be clear from these examples that any selection or sequence of selections of bits from any part or all of either the memory or bus width or the VGA section can be selectively programmed under the control of decoder and counter 4052 and selector 4051. The 32-bit bus width is only illustrative, and narrower or wider 64-, 96-, 128-bit buses or any even or odd number of bits in buses may be used.

In real color mode, the output multiplexer 4038 of Figure 32 operates as a selection circuit having inputs connected to the input memory 4011 and to an output of the look-up table memory 4021 for supplying 3 color output signals to the digital-to-analog converters 4030 with either bytes of color data words provided by the look-up table memory or with a color data word consisting of 24 color codes from the input memory 4011. The selection circuitry includes a detector 4036 for a predetermined code, such as 0hex of minority bits in the input memory 4011 to make the selection. A delay circuit 4039 for the color data word consisting of color codes from the input memory has a first delay which is substantially the same as a second delay inherent in supplying a color data word from the look-up table memory 4021 in response to a color code from the input memory.

In real color mode, 24 bytes of data (eg, bytes A, B, C of Figure 31) are transferred directly from input memory 4011 to DACs 4031, 4033 and 4035 via pixel bus 4359 of Figure 32. In this mode, overlay is achieved by using the remaining 8 bits (such as bytes D or alpha shot or attribute input) from input memory 4011 as an overlay bus 4360 to address palette RAM 4021 via multiplexer 4389 and read mask circuit 4061. Such addressing results in a 24-bit output of the palette RAM 4021 which is then used as overlay information for the DACs 4031, 4033 and 4035. If all of the overlay inputs P7 - P0 (byte D of input register 4011) are at logic 0 or the read mask register 4353 of Figure 31 is cleared, no overlay information is displayed. Thus, the selector logic 4051 contains logic to detect the status of byte D and controls operation accordingly. Also, if a non-zero value is entered into byte D of input register 4011 and then the read mask register 4353 is not cleared, the color palette RAM 4021 is addressed and then the resulting data is passed to the DACs to take priority over the real color data on lines 4359 of Figure 32.

The overlay inputs in real color mode are those that go to the color palette RAM. Real color mode can also operate without overlay occurring. Advantageously, however, an overlay allows setting an artificial color data word in the palette RAM 4021 that is not available in the video RAM, or, for example, establishing a special set of colors for overlaid text or a cursor or both on a background. An overlay can also be used to set up graphics on a rolling video image in colors that are user controlled in addition to the colors in the video RAM. Some graphics applications can use an overlay to outline an object by overlaying the outline graphics over the object as the real color image. An overlay can provide an overset of the available colors.

The circuit 4000 of Figure 1 provides the shift clock signal SCLK which directly clocks the shift register 139 for each VRAM 130. The SCLK signals can support VRAMs with partial shift register transfer. Such VRAMs are in connection with Figures 3-21 above. Background information on VRAMs can be found in commonly assigned U.S. Patent Nos. 4,639,890, 4,330,852, 4,683,555, and 4,667,313.

As a next point in discussion, the preferred embodiment has a graphics processor 120 which has its own clock and thus does not necessarily rely on the clock according to the palette dot clock or a derivative of the dot clock. The processor 120 may (as in the case of the TMS340x0) include video counters which are driven by a derivative of the dot clock. It is this latter use of the dot clock in the processor 120 which will be discussed next.

Synchronization between the palette 4000 and the GSP 120 is mediated by both the VCLK and SCLK output signals from the palette 4000. In other words, the clocking that coordinates the frame counting of the GSP 120 with the palette 4000 does not come from the processor 120 in this embodiment, but from the palette 4000. The GSP 120 is connected to use the VCLK to determine where operations occur relative to a particular scan line of the image. VCLK is also used by the GSP 120 to determine when the GSP 120 should generate a blanking signal and when to generate the synchronization pulses HSYNC and VSYNC.

The GSP 120 in Figure 2 has counters in the video display controller 270. The counters count up in response to being clocked by the video clock VCLK. At a predetermined count, a blanking signal is output. At a subsequent predetermined count, a sync pulse is output. At yet another predetermined count, the sync pulse is cleared, and then the blanking signal is cleared, and then counting is restarted. The counter is incremented at the beginning of the sync pulse. reset. VSYNC and HSYNC from processor 120 are sent over bus 124 to the block video MUX and palette control 4000 in Figure 32 at the VSYNC and HSYNC terminals. Processor 120 may be dedicated to the graphics function and adjusts the signals to determine which monitor display standard is appropriate for display 170 and thus sets up the blanking and sync pulse timing.

In the computer graphics system 100 of Figure 1, palette 4000 provides the time base for preprocessor GSP 120. The front end effectively closes a loop using a time base to provide blanking and synchronization signals which are then sampled by the back end, here palette 4000. The loop is advantageously closed because there is a discontinuity between the read/write access side of the VRAM accessed by GSP 120 as opposed to the operations of palette 4000. In this way, the GSP elegantly counts pulses and can determine when the operations in VRAM 130 occur.

In another related feature, the blanking precession delay circuit logic 4384, 4322 and 4321 of Figure 31 has an input connected to a selected blanking signal BLANK- and VGABLANK- from the input memory 4011 selected by a multiplexer 4386. A second input of the logic 4322 is connected for clocking by the clock circuitry 4041. The delay circuit 4322 has a variable delay or programmable delay followed by a fixed delay 4321 which provides the DACs 4030 with blanking signals precisely coordinated with the last pixel in each row.

In Figure 31, the blanking precession is the delay that changes depending on what the bus width/pixel depth ratio N. For example, aside from a fixed delay F2 of circuit 4321 to compensate for the delay inherent in the architecture of the palette, the blanking precession delay circuit logic takes into account the number of dot clock cycles required to transfer the contents of input memory 4011 to RAM 4021. This number of cycles is directly proportional to the ratio of bus width to pixels per bus load in Table 4. This determines how much additional delay is necessary from the time the blanking signal on input terminal BLANK- becomes active until the circuit drives DACs 4031, 4033, and 4035 to the blanking level in Figure 31. When processor 120 counts a predetermined number of VCLK pulses, it activates its BLANK- terminal connected to the blanking input terminal of palette 4000. At this time, the palette 4000 has to consider how many pixels are left in the input selector 4051 that are left to display before it drives the DACs into blanking. The blanking precession delay circuit logic 4322, 4321 thus determines how many dot clock periods the palette 4000 should wait before it drives the DACs into blanking. If the blanking signal is generated to the DACs too soon, one or more pixels will be lost from the display. If the blanking signal is generated to the DACs too late, a meaningless "garbage pixel" is introduced into the delay. The blanking precession logic advantageously causes the blanking signal to occur at exactly the right time, regardless of what combination of data path width and number of pixels per bus load is selected in control register 4371 of Figure 31.

In Figure 31, a selector mode dependent variable delay plus a sufficient fixed delay is provided as a total delay by the circuit 4322, 4321 for each video control signal, not only BLANK, but also HSYNC and VSYNC. In a further embodiment, the variable delay is omitted for synchronization, since the timing is less critical for synchronization than for the blanking signal. Part of the delay is switchably bypassed in VGA pass-through mode to provide a fixed delay F1 in this mode.

Figure 31A shows why synchronization is less critical in timing than sampling. For example, in a raster scanned CRT monitor, the intensity of the pixels in the scan line is precisely terminated at the end of each scan line by the onset of the blanking signal. Blanking sampling circuit 4384 and blanking precession delay circuit logic 4322 and 4321 effect termination by a blanking input to DACs 4030. The synchronization pulse in the composite video signal in Figures 39 and 40 is roughly centered in the middle of the blanking signal. Consequently, as shown by dotted lines in Figure 31A, continued deflection of the erased scan line (dotted) until synchronization and during backtracking (diagonal) is invisible to the viewer. When the blanking signal ends (on the left), the length of the blanking signal is precisely established by the GSP 120 and delayed exactly in the 4000 range to allow the first pixel in the next scan line to be seen. A small error in the delay of the synchronization does not change the relative position of the scan lines or pinch off any pixels and can therefore be tolerated in another embodiment.

Generally, the palette device is provided with a mode circuit, such as a register 4371, for establishing one of a variety of different modes of operation. The color code processing circuitry (such as the selector 4051, the RAM 4021) is operable according to a mode established by the mode circuit and is responsive to the color codes by supplying color data words which are converted into a convertible into analog form, the color code processing circuitry establishing different time intervals between the input of the color codes to the color code processing circuitry and the supply of the color data words depending on the different modes. A variable delay circuit (such as the 4,322,4321) is responsive to the mode circuitry for delaying the video control signal (such as blanking, synchronization or some other display control signal) by a time interval dependent on the mode established by the mode circuitry. The variable delay circuit is connected to control the DAC with the video control signal so delayed. Since the selector 4051 sequentially supplies different sets of bits from the input memory to the lookup table memory in different modes in Figure 31, the sequential supply sets the time interval in the color code processing circuitry differently in different modes. Thus, the delay may vary from mode to mode in accordance with the value by which a time for sequential delivery in selector 4051 varies from mode to mode.

Generally, in various embodiments, one skilled in the art will determine the circuit delay of the DACs and the palette circuitry prior to the DACs and add the delays to obtain the delay value that should be incorporated into block 4321.

A propagation time elapses between the time the processor 120 counts up to and reaches the particular count value at which the blanking signal is generated and the time the blanking signal arrives at the palette 4000 from the GSP 120. Furthermore, there is a clock delay because the video counter circuitry of the processor 120 and the palette 4000 are synchronized but shifted in time. This clock delay is described more fully in connection with Figures 49-50. Thus, palette 4000 sends VCLK and SCLK with a propagation delay to processor 120 where the counters are running at a time offset from palette 4000. Processor 120 returns blanking and synchronization signals with a propagation delay to palette 4000. This provides a situation where blanking and synchronization are shifted relative to palette perspective by an indefinite delay which is a shift in the dot clock. This blanking or synchronization shift may vary over several pixels of the image at a dot period of 7-16 ns. However, for display correctness, blanking should desirably occur exactly on a correct dot edge with the image going into the blanking signal exactly at the display of the last pixel in each line.

Since the blanking can vary over 4-8 dot clock periods and must be resynchronized in the DAC and generated in just the right window, the timing is established by an ascending resolution sampling process as shown in Figures 49-50 in blocks 4384, 4322 and 4321. The resynchronization or sampling can and is mixed with the blanking precession delay in the circuitry, but these two concepts are different and both provide advantages for the preferred embodiment.

A transition edge A from the VCLK in Figure 49 triggers a blanking signal from the processor 120. The flip-flop 4384 uses the next transition edge in the same rising or falling sense in the VCLK to sample, catch or capture the newly arrived blanking value or signal. Thus, the maximum allowable shift is implicitly one VCLK period. If there is a shift greater than this, the frequency of the VCLK is adjusted by reprogramming the VCLK division ratio determined by the output clock. Select register OCS 4363 is decremented to allow processor 120 more time between edges to generate a blanking signal. The VCLK period should be significantly longer than the transition time of BLANK- (from GSP 120). BLANK- can be effectively sampled on a dot clock edge that occurs well after the VCLK edge (rising) that causes the transitions of BLANK-. This ensures that resynchronization can be accomplished.

Clocking the 8384 flip-flop through VCLKs samples a blanking signal from the GSP 120 to the resolution of the video clock to produce the blanking signal at that resolution. The VCLKs have a selectable period that is as short as the dot clock period or as long as 32 times the dot clock period. In an example of a 20 nanosecond dot clock period, the period of the VCLKs would be 20 nanoseconds or more. The multiple is suitably a power of 2, which ensures that one and only one blanking edge will occur between any 2 VCLK edges. The sampling has approximately a 2 nanosecond time between a clock transition and the occurrence of a valid Q output from a 4384 flip-flop that is clocked.

By sampling the signal, the variability of the blanking edge is reduced to the setting time of the flip-flop 4384.

In Figure 49, the VCLKs operate in nanoseconds, compared to BLANK in microseconds. Since the period of the VCLKs is programmable, the rising edge A can be made to see a high level of the BLANK- while the edge B will see a low level of the BLANK- period Pl later. Then the edge B triggers the flip-flop 4384 to cause its output to fall. The timing uncertainty B1 is on the order of 0-40 nanoseconds. Using the Flip-flop 4384 reduces the uncertainty in time when the output of flip-flop 4384 is d2, which means an uncertainty of perhaps 1-2 nanoseconds. Although edge B is delayed more than the amount dl by which BLANK is indefinitely delayed, edge B has a known timing relationship to the dot clock, which is the point for recovering a correct timing relationship to the blanking signal. When a relationship of a VCLK period P1, a multiple of the dot clock period, to the output Q is established, two additional stages of sampling increase the timing resolution of the sampling in Figures 50, 49 and 52.

In successive flip-flops in Figure 50, clock signals of increasing frequency clock flip-flops 4384, 4322 and 4321, thereby narrowing the blanking edge to an even higher time resolution. This arrangement of clocking flip-flops in order of increasing time resolution is referred to herein as acceleration. The acceleration reaches a dot clock resolution as the blanking signal enters pipeline 4321.

A selectable delay is advantageously introduced by clocking the flip-flops 4322 with a signal LOAD. LOAD has the same division ratio to the dot clock as the shift clock SCLK and runs continuously rather than being interrupted during the blanking signal like SCLK. Therefore, clocking the flip-flops 4322 with LOAD introduces a delay in dot clock periods that is firstly equal to the clocking of the input memory 4011 by LOAD and secondly equal to the number of dot clock periods used by the selector 4051 to transfer all pixels from the input memory 4011 to the RAM 4021. This is exactly the desired blanking precession delay. Thus, time resolution is increased and blanking precession also occurs.

The output of flip-flops 4322 is provided to pipeline 4321. The pipeline is clocked by the dot clock, which completes sampling at the highest time resolution and produces a fixed delay, and then generates an internal blanking signal BLBD for blanking for the DAOS. Since blanking signal BLBD has a known delay relationship relative to the dot clock edge that previously went to processor 120 to initiate a blanking signal, and a delay in the signal path in palette 4000 matches and compensates for this delay, the color signal output is precisely synchronized with the blanking signal.

Looking at Figures 51 and 52 more collectively, correspondingly labeled rows in the two figures of the drawing are to be connected together. The multiplexer control register bit 5 (Table 4) MCRB5 causes the multiplexer 4386 to select between the BLANKB and VGABLANK input signals in Figure 52. Figure 51 shows connections between the input clock selection register and the clock multiplexer circuitry connected to the CK (clock) input. Figure 51 also shows connections between the output clock selection register and the multiplexer circuitry for providing combinations of the frequency division output signals from a frequency divider chain. Some of these outputs are connected to the blanking and synchronization circuitry of Figure 52 by lines VCLKS, LOAD and DOT.

In Figure 50, the blanking signal BLANKB passes through gates X8, X33 and between the delay flip-flops X33 and gate X26. An output signal is a signal called BLANKB which turns off the shift clock signal SCLK in its precession function.

A block SSRT in Figure 52 reacts to the signal level at the terminal SSRT/NF (partial shift register transfer/nibble flag). Control register bits 2 and 3 determine whether the circuit is in SSRT mode or nibble flag mode. If it is in SSRT mode, then the SSRT signal is passed through NAND gate X1 and then the SSRT delay block generates a pulse of predetermined width on line SSRTP which is needed to trigger VRAM 130 via the circuitry of Figure 51 and the SCLOCK output.

One purpose of having the low pulse from SSRT on the memory cycle waveform line is to load the new tap point for complete transfer into the registers within VRAM 130. The tap point register transfers an address into the input memories of VRAM 130. There is a two step process in VRAM 130. Processor 120 provides a LAD code to invoke the shift register transfer. A tap point value is not transferred to tap point counter 94 until the next rising edge of shift clock SCLK. If no pulse were inserted between these two functions, the value that is in memory 91 could not be transferred to tap point counter 94. The second transfer would overwrite the current value in memory. Thus, the onset of the pulse SSRTP advantageously moves the tap point of the complete shift register transfer to the tap point counter 94, and overwriting is avoided.

Thus, as shown in Figure 14, memory 91 is clocked by the memcy- waveform, and the memcy- waveform moves data from the bus into input memory 91. SCLK subsequently causes a transfer of the data from tap point counter 94, as indicated by the notation SCLK in Figures 14 and 21.

During the blanking signal, SCLK is disabled (except for the SSRT pulse onset) in this circuit. This shift clock signal, which is applied to the chip bonding terminal is designated as SCLOCK in Figure 52, but corresponds to the identical output signal SCLK of Figure 31.

The clock control 4041 of Figure 31 is shown in more detail in the schematic diagram of Figure 51. A series of clock generation circuitry generates correction frequencies based on the control signals MCRB5, the input clock select ICS 0-3 and the 5 oscillator input signals CK0-CK5. Block 4040 shows circuitry for selecting which of 6 clock oscillators are allowed to drive the programmable palette 4000. The output of block 4040 goes to block 4041 which is a clock divider to determine the correct frequency for SCLK and VCLK based on the input signals OCS0-5.

The division ratio is equal to the pixel bus width divided by the pixel depth and divided by the dot clock selected by block 4040. If there is a 32-bit wide data path and a 4-bit pixel, the division ratio is 8. This is important because it enables the ability to use all of the pixels in input memory 4011 before loading the next set of 8 pixels into input memory 4011. The division ratio (e.g., "divide by 8" the dot clock) gives the frequency of the shift clock SCLK, which causes 8 pixels to be loaded on each rising edge. In this example, the palette chip sequentially accesses 4-bit portions of the bus, one at a time, immediately before the next SCLK cycle is generated by this division circuitry to load the input memory 4011 with a new set of 32-bits forming 8 pixels of 4-bits each.

In Figure 31, the clock control register ICS 4361 determines the clock oscillator selection and not the division ratio at This embodiment Thus, the clock control register 4361 is selected by RS0-RS3 and is directly accessed by the data bits D0-D7 for clock selection. The logic 4362, on the other hand, decodes a portion of the control register OCS 4363 and sets up the division ratio in the circuit 4041.

The output control bits OCS0 OCS5 are outputs of logic 4362, which is driven by control register bits 4363, and determine which clock division ratio is introduced. The input clock selects ICS0-3, on the other hand, are the bits from register 4361 and determine which clock oscillator is used. The circuitry 4044 SCLK_SELECT_NEW3 takes the inputs from the dividers and OCS0-2 and determines which frequency is distributed to the SCLK output to provide sufficient delays in block 4041 to generate LOAD as well as a VCLK and a SCLK (internal signal). In Figure 51, VCLOCK is the VCLK output to the bonding terminal of a buffer 4341, which is applied by logic 4042 in response to OCS3-5. SCLOCK is the SCLK output signal to the bonding pin of a buffer 4343 of the logic 4044.

Buffering is provided by buffers such as 4341 and 4343 to drive some inputs external to chip 4040 if necessary and to increase the current carrying capability of chip 4000 for external driving beyond what is required for internal circuits to drive each other on the chip.

In Figures 54 and 55, the test circuitry 4395 of Figure 31 accumulates a sum of individual bits in color-related bytes of the output signal from RAM 4021 in a time interval between vertical synchronization pulses. Each byte goes into a ones counter circuit 7001 of Figure 54 from a circuit 7061 of Figure 55 which selects the color to be counted. In Figure 54, the byte ACCUM [0-7] is input to a memory 7011. The memory 7011 has 8 bits including a high 4-bit nibble and a low 4-bit nibble. To advantageously make the logic fast, nibble decoders 7013 and 7015 count the number of ones in the respective high and low nibbles by decoding them. For example, 1111 is decoded to 100 (four ones decoded to binary 4), 0101 is decoded to 010 (two ones decoded to binary 2), etc. The binary number from decoder 7013 is output on lines B2, B1, and B0. The binary number from decoder 7015 is output on lines A2, A1, A0. These two binary numbers are then added together by an adder circuit 7021 having an input latch 7023 and an adder logic 7025. The output is a binary number on lines N3, N2, N1, N0. For example, if ACCUM [0-7] is 01101100 (has four ones), the output of adder 7021 is accordingly 0100 (binary 4). A total or accumulation of the ones thus counted is produced by accumulator 7027. Accumulator 7027 has an input latch 7029 and accumulation logic 7031. The total is refreshed in a set of latches 7033 clocked by the dot clock and then placed in test register latch 7041 upon the occurrence of the next vertical synchronization pulse VSYNC0. Circuit 7045 provides dot clocks to circuits 7011, 7021 and 7027 when an enable line ACKEN is active. Circuit 7051 provides vertical synchronization to test register 7041 when activated by bit 1 of general control register 4398 (GCRB1).

In Figure 55, an accumulator multiplexer circuit 7061 has a set of 3-input multiplexers 7063.1-.8 which produce a one-piece line output signal for the 8 lines ACCUM [0-7]. The inputs are connected to the 24 lines of the output of the RAM 4021, RED [0-7], GREEN [0-7] and BLUE [0-7]. The 3-way selection of color bits to be counted is controlled by a set of lines BSB, GSB, RSB. The activation circuitry 7065 has inputs connected to the 3 lines as well as to a blanking line BLB to produce the ACKEN signal as an output signal.

As described, the circuitry 7061 and 7001 performs a one-bit accumulation analysis from the input memory 4011 through the output of the color palette RAM 4021. The palette test register and one accumulation register 7041 counts the ones that appear at the output of the color palette RAM during a period of time. The period of time is suitably the period between successive vertical synchronization signals, or 16.7 milliseconds. Since this period may be long enough to cause overflow in the memory 7033, the accumulation consists of the least significant bits of a binary total thus accumulated. The accumulation allows a host computer to run test software to determine whether the correct data from the input memory 4011 is passing through the output of the RAM 4021. The software performs a comparison between what is received and a value that should be received for verification purposes. The ones accumulation value is accessed via terminals D0-D7 and is selected by RS0-3.

The accumulation of ones facilitates system testing. When a predetermined test pattern is provided by the host 110 and reproduced by operations of the GSP 120, VRAM 130 and palette device 4000, a known value of the accumulation value should be counted. If If this value does not occur, the system test detects a condition that may require system replacement or repair.

The color palette RAM 4021 produces three 8-bit outputs. At first glance, the 8-bit outputs could be any sequence of ones and zeros. When a test regime is introduced, a restriction is introduced. In a test scheme, all zeros are written to the VRAM, and all ones are written to the RAM 4021. Then, on each access, each byte should contain only ones, and if this does not occur, the test has failed. However, this will only address zero in the palette RAM 4021. In a second phase of the test, the VRAM is filled with only 00000001 values, and the address in the RAM is accessed. For a number of phases equal to the number of addresses in RAM 4021, the test is run with values in VRAM all equal to the last address in RAM 4021 to be accessed. In this way, all bits across the width of bus 145, all multiplexers, and all addresses in RAM 4021 are tested.

In a further test, all locations in RAM 4021 are loaded with ones, except for the location to be accessed, which is loaded with zeros. Accordingly, if all zeros are not produced as an output, a defect is detected somewhere in the system, including the processor, VRAM, and pallet 4000. This defect can be isolated to the pallet by running a test routine from the processor on the VRAM to determine if it is producing the output that would be expected based on what is loaded into the VRAM, and if the VRAM passes the test, pallet 4000 has the defect.

Other tests can also be performed. Another test principle is counting the number of ones in the data to be transmitted, and that number is appended to the transmitted data. When received, the number of ones is again counted and compared to the number appended to the transmission. If the number is the same, then the data passes the test. In this way, the number of bits required to test the RAM only increases logarithmically with RAM size.

In yet another test, the entire RAM 4021 is unloaded and all the 1's stored in it are counted by color type and compared to numbers expected for the contents of the RAM. Three registers for R, G, B shots hold data unloaded from memory and a sum is obtained over each set of 8 bits and then an accumulation takes place when all locations in memory are unloaded. The 1's accumulator register can also hold totals for RED, GREEN, BLUE sums and can be accessed sequentially by an RS0-3 address followed by three increments of a RED signal to read the 1's accumulation registers. In multiplexing the present embodiment, a color is selected and then accumulated between moments of vertical synchronization, and then another color and another.

These analog comparison bits in the test register provide a test for the palette device 4000 individually, in addition to the system test provided by the ones accumulation register. Identical bytes can be loaded into the RAM 4021 for each color. If they do not produce approximately the same analog output signals, then a possible problem condition is detected. A given byte of a value that should be equal to a reference level can be provided to any DAC 4031, 4033 or 4035 and the DAC output compared to that reference level as an analog level. If there is a discrepancy, a defective DAC or a defective connection to the monitor is indicated. The The reason that the connection to the monitor could affect the DAO output is that the input impedance of the monitor causes the DAC to drop, so unwanted decoupling of the monitor changes the DAC output signal.

The 256x24 RAM 4021 is an SRAM based on fast, static RAM technology.

Turning now to another aspect, the OR gate 4036 of Figure 32 is just one example of circuitry that can be used to detect the presence of the real color mode. Any of two or more values could alternatively be detected to control the output multiplexer 4038 on the real color mode, and any value then passed to the attribute or intensity circuitry. Also, the selection can be established by on-chip control circuitry, freeing up all values of the 8 remaining bits of byte D in Figure 31 for controlling attributes or intensity.

The 8 bits are referred to here as minority bits, and the 24 bits are called majority bits. Generally speaking, the majority bits are equal to or greater in number than the minority bits, and in the present embodiment, the majority bits are in a ratio of 3:1 to the minority bits. As used herein, majority bits and minority bits include a concept of a preponderance of mere number, regardless of location, which is a different concept from that of the most significant bits and the least significant bits, which is a concept of a location relationship or significance.

In another embodiment, the 16-bit bus shown in Figure 56 inputs the minority bits to the palette RAM 4021 and the majority bits are input to a 0 detector 6836 (analogous to the OR gate 4036 of Figure 32). The 0 detector 6836 controls the select line of a MUX 6838 which provides 12 lines in three groups of 4 lines to DACs 4031, 4033, 4035. Palette RAM 4021 is provided with minority bits on 4 lines and then provides a 12-bit output for selection by MUX 6838. 12 majority bits are provided on 12 parallel lines as an alternate selection by MUX 6838. This embodiment advantageously uses only a value zero of 4096 (212) values representable by the majority bits to perform the selection. This circuit is easily implemented to protect the color repeat functions in GSP 120. A majority bit embodiment for RAM 4021 would provide a highly detailed color selection for a graphics background and fewer color selections for a foreground (one of which would be the code for a reactive color or transparent). In contrast, the embodiment of Figure 56 would provide a foreground of 4095 colors (4096 less 1) provided by bypassing the true color and activating the null capture 6836 and causing the MUX 6838 to select any of 16 colors as background colors from RAM 4021. In other words, there are (4095+16) different colors that can be displayed simultaneously.

Referring to Figure 57, another embodiment of an improved palette circuitry is shown. With 8-bit palettes, the 8-bit pixel data is used to select one of 256 (28) entries from a look-up table (LUT) 4021 which contains raw data to drive the DACs 4031, 4033, 4035 which then output analog RGB signals. One problem with moving to pixel sizes larger than 8 bits is that decoding becomes more complex and thus slower. This tends to cause the pixel data bandwidth to drop.

In Figure 57, the incoming 16-bit pixel data is divided by a division circuit 6901 (eg in the selector circuit 4051 of Figure 31) into components, e.g., RED, GREEN, and BLUE sets of bits or shots. The divider is a logic circuit that inputs pixel data simultaneously with further predetermined levels as desired to three 8-bit buses RLD, GLD, and BLD (RED, GREEN, BLUE load). By dividing the incoming pixel data, the size and depth of decoding is minimized at each of the three 1-of-256 decoders 6903, 6905, and 6907, respectively connected to the RLD, GLD, and BLD buses.

For example, consider a 16-bit palette. The data is randomly split into RED, GREEN, BLUE components of 8 bits, 4 bits, and 4 bits a piece. Each of these components is used to drive decoding in component lookup tables 6911, 6013, and 6915 for input to DACs 4031, 4033, and 4035. Note that in the worst case, decoding in this example is still only 1-of-256, the RED component.

For flexibility, the palette can be designed to allow the user to select the split by entering a code to set up the split into control register 4371. For example, splits of 7/6/3, 1/14/1, 8/4/4, and 5/7/4 can be selected by any of 4 permutations of the two split control bits. Decoders 6903, 6905, and 6907 and LUTs 6911, 6913, 6915 are designed to handle the maximum number of decodes and lookup table entries that could invoke the split control bits.

When dividing the data, the unused signals that drive the decoders should be automatically set to a known value so that there is no ambiguity in the result. Zeros (0) are a simple selection of a known value for this purpose. In one example, control register 4371 is loaded with a division code to establish a 5/7/4 division for RED, GREEN and BLUE. Division logic 6901 supplies pixel bits S so that 5 bits go to bus RLD with three zero bits, 7 bits go to bus GLD with one zero bit, and four bits go to bus BLD with four zero bits. Thus, the RLD bus has bits 000SSSSS (where S is source data from the incoming data stream). Similarly, the GLD bus is 0SSSSSSS, and the BLD bus is 0000SSSS.

With respect to a different improvement, a direct connection of the VRAM and the programmable palette 4000 is possible when the VRAM bus width is less than or equal to the width of the data input of the palette 4000. When wider buses are used, an additional multiplexer may be provided between the bus 145 and the input memory 4011. The multiplexer has inputs connected to portions of the bus 136 that are less than or equal in width compared to the input memory 4011, and the output of the multiplexer is connected to part or all of the full width of the input memory 4011.

Figures 58A-C illustrate the present work from a process or method perspective. In Figure 58A, the process operation begins with a START 8001 and proceeds to an initialization step 8003 including initializing a color code index to 1. Then, a step 8005 inputs clock control information from a source, such as the GSB 120, external to the palette integrated circuit 4000 to a register ICS and OCS in the integrated circuit. The subsequent step 8007 operates the clock control circuitry 4040 and 4041 in response to the clock control information so that clock pulses for the function performing circuitry (e.g., 4011, 4051, 4021 and 4030 of Figure 31) are provided by the clock control circuitry in accordance with the clock control information. thus entered into registers ICS and OCS. In this manner, a particular clock oscillator is selected and a combination of frequency division ratios is established. The frequency divider block 4041 provides clock pulses in a first combination of ratios to the clock outputs VCLK and SCLK in response to a first set of bits in register OCS, and provides clock pulses to the same clock outputs VCLK and SCLK at a second combination of ratios in response to a second set of bits substituted for the first set in register OCS, see Table 3b.

At step 8009, GSP 120 inputs mode bits to MUX control register 4371. The mode bits are decoded to select a total bus width and a pixel width for transfer by selector circuit 4051 at step 8011. The ratio of the total bus width and the pixel width is a division ratio used for circuit 4041 to divide the dot clock to generate shift clock SCLK. This ratio may be calculated or decoded from the mode in register 4371 or provided independently via OCS register 4363 as in Table 3b.

A test step 8013 determines whether index 1 has its first value as 1. If so, multi-bit color codes with a number N equal to the division ratio (e.g., 32-bit bus width divided by 8 bits per pixel equals an N value of 4 in one mode) are simultaneously input from video memory to multi-bit input memory 4041 in palette device 4000 via bus 136 in step 8015. Also appearing is a second set of bits, such as VGA bits, if any are input via another bus, such as from auxiliary connector 6521 of Figure 26.

If a division mode is present in the next step 8017, then multiple LUTs are accessed simultaneously in step 8019 with reduced decoding time by color code bits and other predetermined bits established by dividing bits caused by the division mode. The operation proceeds from step 8019 through point A. Otherwise, the operation proceeds from step 8017 through point B.

Referring to Figure 58B, the operation proceeding from step 8017 through point B reaches a step 8021 in which a blanking signal is sampled with progressive resolution as shown in Figure 49. Next, there is a decision step 8023 regarding the VGA pass. If the VGA pass is enabled, then a step 8024 delays VGABLANK- by a delay number F1 of dot clocks. Then a step 8025 transfers the VGA color code to the LUT 4021. In this manner, color data words are selectively provided by the LUT in response to color codes from the input register 4011 by selecting color codes from a first or second graphics bus, and also a video control signal is selected for output depending on the selected first or second graphics bus.

If the VGA pass is not selected in step 8023, operation proceeds to a test step 8027. If the SSRT pin is active and a blanking signal is active, then an extra SCLK pulse is output in step 8029, for example, as shown in Figures 24, 35 and 37. This provides a method of operating a computer graphics system having a video memory with a shift register configured for partial shift register transfers and a digital computer for controlling the video memory and having a tap point counter clocked by a shift clock signal and also having a blanking circuit for supplying a blanking signal. Step 8029 initiates an extra- Shift clock pulse for the tap point counter during a blanking interval defined by the blanking signal. If the test of step 8027 is not passed, then step 8029 is bypassed.

The blanking precession step 8031 delays a blanking signal by a variable delay equal to the sum of a fixed delay F2 plus a variable delay equal to or proportional to the number N of cycles necessary to transfer the N pixels in the input memory to the LUT. The fixed delay F2 compensates for the circuit delays of the LUT, other logic, and the digital-to-analog converter 4030. The variable delay of 2N dot clocks recognizes that the selector circuit 4051 cooperates with the LUT and the DACs to process color codes according to various modes to provide color data words, the processing establishing various time intervals between the input of the color codes for processing and the delivery of the color data words. In this manner, the blanking signal as an example of a video control signal is variably delayed along with the processing by time intervals correlated with the time intervals of the processing in at least two of the different selector modes, thereby providing the video control signal so delayed.

The nibble mode test step 8033 determines if the nibble mode is invoked. If so, a step 8035 provides a high or low nibble (depending on the high or low state of the nibble input), identified by an index 1, from the input buffer 4011 to the LUT 4021. If not, operation proceeds to step 8037. Here, a bus width coupling circuit configured by the selector 4051 connected between the input buffer 4011 and the LUT 4021 is programmed to pass the last color code 1 from the bus according to the programmed bus width.

Advantageously, the bus width coupling circuit transfers color codes of selectable width in a sequential manner across the bus and utilizing the entire bus width. The sequence or cycle from the process standpoint of Figures 58A-C is a series of loops through the flow chart N number of times to transfer all of the color codes loaded into the input memory 4011 for the bus width established by the mode in register 4371.

After step 8037, a test step 8039 detects whether a real color or an overlay is required. This detection is mediated by a circuit such as the OR gate 4036 of Figure 32 or, for example, the detector 6836 of Figure 56. If so, enough bits to form a color data word (e.g., 24) are transferred to the DACs 4030 at a time and the LUT 4021 is bypassed in a step 8041. Point A is reached after any of steps 8025, 8035, 8041, if no in step 8039, and after step 8019 of Figure 58A.

Referring to Figure 580, operation proceeds from point A to a conversion step 8043 performed by the DACs 4030 to produce analog color signals such as R, G, B. It should be understood that in various embodiments, the analog signals may be matrix color signals or display signals for color display devices that do not produce a raster scanned image, or any type used by one of ordinary skill in the art in practicing the invention.

The following step 8045 tests whether the delayed blanking signal is L-active. If so, the DACs are blanked in a step 8047. Otherwise, the operation goes directly to a step 8049. If the index I has reached the number N, then the index I is incremented in a step 8051 is set to zero. Otherwise, operation proceeds from step 8049 to accumulation step 8053 to update a current number of bits of a particular state (e.g., 1) provided at a predetermined set of outputs of LUT 4021 over a period of time between, for example, vertical sync pulses. In the test circuit of Figure 32, current counts of the bits of the word bytes for RED, GREEN, BLUE color data are maintained.

A next step 8055 makes a check to determine if a test mode access is required. If so, a step 8047 externally accesses the count or counts from the total value of the bits at the accumulator outputs. Also at this time, analog tests of DACs 4031, 4033 and 4035 are performed and bits for representing the analog comparisons are accessed from the DAC test register. If there is no test mode in step 8055 or step 8057 is completed, operation proceeds to step 8059 to increment the index 1 and return via point C to Figure 58B and Figure 58A to step 8061 to check for a reset condition. If there is no reset condition, the operation completes the loop to step 8013 and continues execution. If there is a reset, the operation proceeds to step 8003, whereupon, if the reset is performed, the operation reestablishes the operating parameters of the pallet device 4000.

In a present embodiment, the clock control circuit 4041 has various combinations of clock division ratios established through the OCS register. In other embodiments, the clock division ratios may be established by decoding from the MUX control register 4371 to ensure that the configurations of the selector 4051 match the established clock division ratios. In such an embodiment, non-zero values in certain bits of the OCS register may override clock decoding from MUX control register 4371, while zero values default to decoding from register 4371. Other changes in the control plan for consistency, simplification, flexibility, and reliability may also be made.

In another aspect shown in Figure 59, internal palette control of alternative first and second data streams is provided by still further refinements as represented by control logic 9001. In Figures 31 and 32, a selection between the VRAM 130 input signal or the VGA input signal is controlled externally by an entry of bit 5 (MCRB5) in control register 4371. A selection circuit such as 4389 of Figure 32 selects between the two data streams and passes color codes to RAM 4021. RAM 4021 provides color data word bytes to DACs 4030 for generating color output signals IOR, IOG and IOB.

In the embodiment of Figure 59, bit 5 of control register 4371 does not immediately select the VGA pass, but instead activates an insert over a rectangular portion 9011 of an image 9013 in an image shown in Figure 60. The insert 9011 or secondary graphics window is displayed by one data stream and the remainder 9015 of the image is displayed by another data stream. Which data stream provides the insert 9011 is determined by an inversion bit in control register 4371. The size and position of the insert is defined by coordinates of the upper left corner (X1,Y1) and the lower right corner (X2,Y2). These coordinates are set up by GSP 120 to write an array into a register set 9003 in control block 9001. If the coordinates cause the insert to cover the entire screen, an unconditional selection is equivalent to the VGA pass of Figures 31 and 32.

Thus, the data stream for the palette can be automatically switched at the appropriate time on a line/line basis. A counter arrangement including an X counter and a Y counter counts dot clock pulses from the clock control 4041 to determine when to switch from one data stream to another. The counter control and output logic 9005 sends a select signal to the control selector 4389. The select signal is inverted or not inverted in the logic 9005 depending on the inversion bit in the control register 4371. The register select input RS [0-L] has sufficient lines in the number L to provide all register accesses for palette control.

It should be apparent that the geometric shape of the insert 9011 is rectangular for illustrative purposes and other geometric functions are defined by the registers in the register set 9003 and control bits in the MUX controller 4371 and appropriate circuitry in the logic 9005. Trapezoidal, polygonal, triangular, circular, oval, curved, closed bands and other figures are suitably implemented with significantly reduced processing load on the GSP 120.

Additional data streams other than the two shown may be established. One or more data streams may be generated internally, such as by a hardware cursor circuit 9019. The cursor circuit may be self-controlled or may be controlled externally by external signals for providing data to the register set 9003. An input/output cursor control register 9021 in the register set 9003 mediates information transfer regarding the cursor. The cursor generator 9019 in one embodiment shares X and Y counters in the circuit 9001 for positioning the cursor and in an alternative embodiment has dedicated counters (not shown). The circuit 9001 and cursor generator 9019 in Another complex embodiment is implemented as a secondary graphics coprocessor on the chip integrated in the Palette 4000 itself.

An alternative and increased control of the selection of data streams of the selector 4389 is provided by decoding one or more of the data streams in a decoder 9031 to capture predetermined value(s) for superimposition and other purposes. The decoding result is input to a register 9033, the output of which is connected to the counter control and output logic 9005. For example, the logic 9005 suitably includes a mode controlled switch for selectively connecting the control lines to the selector 4389, to the memory 9033, or to the logic 9005 for internal dynamic control. In a more complex arrangement, the decoding result is processed together with the counter control information to control the selector 4389 and to use sophisticated graphics features.

Integrated data streams for different buses, such as VGA, are also enhanced by recognizing that the different images represented by the data have different resolutions. If the parts of an entire image 9013 must have a controlled resolution relationship, such as equal resolutions, the VGA board 9505 is connected to power VGA control circuitry 9051, which buffers low speed VGA data and provides the second data stream at a data rate equal to or related to the data rate of the first data stream. If the first data stream has a higher resolution, then the second data stream (e.g. VGA) is most likely to be displayed at a reduced scale as received by a viewer, since a lower resolution image has fewer pixels than a higher resolution image and these fewer pixels are advantageously placed in one insert in the insert 9011. can be displayed. A control memory 9041 in the palette 4011 is suitably included for mediating a transfer of control information from the logic 9005 to the VGA control circuit 9051 for controlling the data rate and timing of start and stop of the VGA data stream by starting and stopping transfer operations of a buffer in the circuit 9051. The circuit 9041 has a first mode through which VGA is easily passed by the controller 9051 when it is desired to view a full size VGA image at a VGA resolution. In one or more of modes established by bits in the memory 9041, the entirety or a selected portion of a VGA image is notably displayed as a window or inset 9011 with controllable XY positioning.

Improved shifting capabilities are provided in the palette 4000 to accommodate applications where shifting is desired. The VRAM 130 is suitably controlled to perform shifting in units of the number of pixels accommodated by the width of the bus and the input memory 4011. If this number M exceeds 1, a degree of roughness in the display may occur since shifting by the control of the VRAM 130 may involve laterally shifting an image by several pixel numbers M in successive images. Smoother shifting is provided by improved palette circuitry, described next, which provides for shifting in one-pixel increments.

A shifting process is shown with reference to Figures 61A, 61B and 61C. The VRAM 130 is arranged to hold image information that can be shifted. When displaying a first image, the VRAM 130 supplies groups of M (eg 4) pixels (color codes) to the input memory 4011 at each bus load. The number M is the number of pixels on the bus that into the input memory 4011 by each active transition edge of the shift clock SCLK. The pixels are transferred to the RAM 4021 by block shift circuitry designed to implement the memory 4011 and the selector 4051. The pixels are transferred to the palette RAM 4021 in an order 1, 2, 3, 4 as shown in Figure 62. Returning to Figure 61A, each line in the image is completed by a transfer of a final group of pixels (n-3), (n-2), (n-1), (n), where n is the number of pixels per line. (If the line length n is not evenly divisible by M, the final group has a remainder number of pixels 9490.)

In Figure 618, a right shift begins one frame after the frame of Figure 61A. Of pixels 1, 2, 3, 4, the first pixel is ignored by selector 4051 and is not transferred to RAM 4021. Instead, pixels 2, 3, 4 are transferred when the next group of M pixels is loaded and all are transferred: 5, 6, 7, 8. All subsequent groups including group (n-3), (n-2), (n-1), (n) are loaded and transferred. Then another loading occurs, whereupon only pixel (n+1) is transferred to RAM 4021 before the onset of the blanking signal.

If a one-pixel increment shift is desired, then the first right shift frame is as shown in Figure 61B. The next right shift frame (not shown) transfers pixels 3, 4, followed by complete groups across an entire scan line and ending with pixels (n+1) and (n+2). A third right shift frame (not shown) transfers pixel 4, followed by complete groups of N across that scan line and ending with pixels (n+1), (n+2), (n+3). A fourth right shift frame is the same as Figure 61A, except that the GSP 120 performs the shift operation to access the VRAM 130 by incrementing the first group on to be accessed is coordinated to start with 5, 6, 7, 8. Following pictures of the right shift loop through the process are shown in detail in Figure 63.

When shifting left at one pixel resolution, the first shift to the left is shown in Figure 610. Here, the GSP 120 has decremented the first group to be accessed. The first group to be transferred contains pixels on each line of the image arbitrarily designated as (-1, (-3), (-2), (-1). One pixel (-1) in this group of M pixels to the left is transferred to RAM 4021. Then group 1, 2, 3, 4 follows with all pixels transferred to RAM 4021, group by group until the last group 9490 is reached. In the last group, only pixels (n-3), (n- 2), and (n-1) reach RAM 4021 before the blanking signal.

In a second left shift frame (not shown), pixels (-2) and (-1) are followed by 1, 2, 3, 4, etc., and the scan line of the display is completed by pixels (n-3) and (n-2). In a third left shift frame (not shown), pixels (-3), (-2), and (-1) are followed by 1, 2, 3, 4, etc., with the scan line being completed by pixel (n-3). A fourth left shift frame is transferred to RAM 4021 like that of Figure 61A with all pixels (-4), (-3), (-2), (-1) omitted from group 9490. Subsequent left shift frames loop through the process just described, as detailed in Figure 63.

In Figure 62, one or more shift mode bits 9501 are included in the MUX control register 4371 for invoking a right or left shift and for designating any other parameters and for containing the least significant bit LSB of the VRAM address bits as described in detail below. The shift mode bits are connected to a shift control circuit 9503 including a Shift counter 9507 for handling frame-by-frame incrementation in the control of the input memory 4011 by the counter and the decoding circuitry 4052 of Figures 62 and 31. The circuitry 4052 is arranged to include logic responsive to the shift counter 9507 in the shift control 9503 to transfer, for example, a number of x pixels from the first group 1, 2, 3, 4 and a number of Mx pixels from the group (n+1), (n+2, (n+3, (n+4) in the right shift. Analogous or symmetric control occurs for the left shift. The number x is incremented (decremented) frame-by-frame by the shift counter 9507 in the shift control 9503.

The VRAM 130 is appropriately controlled for shifting purposes based on the most significant bits (MSBs) of the address value generated for the VRAM 130 corresponding to the X coordinates of the pixel groups. The palette 4000 appropriately controls the shifting by the LSBs of this address value. For example, with 8 pixels in the memory 4011 of the palette 4000, a number 3 of the LSBs controls a shift in the palette, and the MSBs or the remainder of the VRAM address bits controls the shifting in the VRAM 130.

Thus, shifting circuit 4052 is improved so that it can not only transfer pixels using an entire bus width with selectable pixel widths as previously described, but also transfer first and second subsets of the pixels using the entire bus width, with the first subset being transferred at the beginning of each line of a shifted image and the second complementary subset being transferred at the end of each line in a shifted image. The subsets vary in their number of pixels as determined by the number x in shift counter 9507.

The clock control circuitry 4041 of Figures 62 and 31 is also arranged to supply the video clock pulses VCLK to the GSP 120 and the shift clock pulses SCLK to the VRAM 130 so that the groups of M pixels are supplied to the input memory 4011 as needed for shifting and a continuous transfer of pixels to the RAM 4021 is ensured in each scan line.

Figure 63 shows a column 9601 of first subset sizes, each value of which controls respective frames for shifting. Shifting right across the entire capacity of input memory 4011 (such as 32 bits) is shown by downward pointing arrows in loop 9611R. First, all M pixels in Figures 63 and 61A are transferred. The M-1 pixels are transferred in the first subset in Figures 63 and 61B for the next frame of shifting right, followed later by M-x in the x-th frame of shifting right, until the last (1) pixel (as the first subset) is reached and the loop returns to the beginning to transfer all M pixels.

In Figure 63, shifting is integrated with the feature of the selectable bus widths of the 4000 range as shown by loops 9613R for a 16-bit bus, 9615R for a 4-bit bus, and 9617R for a 1-bit bus (examples are not exhaustive for all bus widths). Loop 9617R is a limiting case where shift counter 9507 is clocked but does not change in value since M = 1 and shifting is conveniently performed by VRAM control.

A left shift in Figure 63 is conceptually symmetrical to a right shift. In loop 9611L, all M bits in the first group in Figure 61A are transferred to RAM 4021. Then in Figure 63, a pixel (-1) of Figure 610 is transferred from the first subset in memory 4011 of Figure 62 at the beginning of each line of the image. Then 2 pixels (-2), (-1) in next frame, and so on, frame by frame until M-1 pixels at the beginning of each line of a frame are transferred, whereupon loop 9611L loops back to transfer all M pixels in the following frame, as shown in Figure 61A. Similarly, loops 9613L, 9615L, and 9617L demonstrate operation for smaller bus widths when shifting left.

In Figure 64, circuit 4041 is configured to supply an additional SCLK pulse 9711 advanced by a number A of dot clock periods relative to the termination 9713 of the L active blanking signal BLMK-. The advance a is variable as a function of the frame number x and is equal to x when shifting right (see Figure 61B), where (M-x) pixels are transferred after the termination 9713 at the beginning of a line. The advance a is equal to M-x when shifting left (see Figure 61C), where x pixels are transferred after the termination 9713 at the beginning of a line. The shift pulse 9711 thus transfers an initial group of pixels, only a subset of which is actually transferred to RAM 4021. A first complete SCLK pulse after 9713 the blanking signal is terminated is delayed by a number of dot clock periods to input a group of M pixels which are transferred to the RAM every 4021 consecutively after the initial group.

Fig. 65 shows another shift embodiment using two memories 4011A and 4011B, where the lead is fixed and does not vary as a function of the frame number x. For the embodiment of Fig. 65, the timing is represented by a waveform SCLK (2-memory) in Fig. 64. There, a cycle of SCLK is inserted in a time interval 9721 equal to the period of SCLK, and this time interval 9721 ends at the same instant 9713 when the blanking signal ends.

In Figure 65, bus 136 is connected to a plurality of memories, here 2, as represented by input memories 4011A and 4011B. A timing control circuit 4041"- provides a shift clock signal SCLK (2-memory) as shown in Figure 64. Also, clock control circuit 4041"- responds to shift controller 9503 and 9507 by supplying load signals LOADA and LOADB having the same period as SCLK to memories 4011A and 4011B. LOADB is used as a single pulse in this embodiment when a frame number x is not zero and the initial group of pixels at the beginning of a line is to be shifted. LOADB may be active for other purposes, but otherwise LOADB is inactive for shifting purposes in this embodiment of Figure 65. LOADA is a series of pulses for storing in all previous groups of pixels in each row of Figures 61A, 61B, 61C. Transfers from either of memories 4011A and 4011B via selector 4051 to RAM 4021 occur at a dot clock rate. Blanking transition 9731 at the end of each row clears any remaining transferred pixels. Selection of memory 4011A or 4011B by selector 4051 and the number of pixels transferred from each group to RAM 4021 is coordinated by shift control 9503 as discussed in connection with Figures 61A, 61B, 61C. On the other hand, the circuit arrangement of Figure 65 operates in the same way and is constructed analogously to the circuit arrangement of Figure 62 with corresponding reference numerals already described.

Some preferred embodiments have been described in detail above. It should be understood that the scope of the invention includes embodiments that are significantly different from those described within the scope. For a few examples, the color display devices used in combination may be raster-scanned cathode ray tube monitors, other raster-scanned devices, non-raster-scanned Parallel line or image drive devices, color printers, image formatters or other hard copy displays, liquid crystals, plasma devices, holographic devices, deformable micromirrors and other non-CRT displays, and three-dimensional and other non-planar image forming technologies. Microprocessors and microcomputers are used in some contexts to mean that a microcomputer requires a memory; the usage here is that these terms may also be synonymous and refer to equivalent things. The term processing circuitry includes ASIC circuits, PALs, PLAs, decoders, memories, non-software based processors or other circuitry, digital computers including microprocessors, and microcomputers of any architecture, or combinations thereof. Palette in some contexts means a special look-up table device, and in the present work means an alternate color data word generation combined with one or more associated circuits such as digital-to-analog converters, selectors, timing controllers, and functional circuits and test circuits and interfaces. Internal and external connections may be made resistive, capacitive, direct or indirect through intervening circuits, or otherwise as desired. Implementation is contemplated in discrete components or fully integrated in silicon, gallium arsenide, or other families of electronic materials, as well as in optical-based or other forms and embodiments of technologies. It should be understood that many embodiments of the invention may utilize hardware, software, or microcoded firmware. Process diagrams are also provided herein to illustrate flowcharts for microcoded and software-based embodiments.

1. Image display device (100) with a video memory (130) in which a plurality of multi-bit color codes are stored, each representing pixels representing an image, a display means (170), a palette device (4000) with a look-up table memory (4021) for supplying color data words for supply to the display means depending on the color codes, and a multi-bit bus (136) in which a predetermined number of bits are connected to the video memory in order to transfer color codes stored in the video memory in bus cycles,

characterized in that the multi-bit bus is designed in such a way that in each bus cycle several color codes are transmitted covering the entire width of the multi-bit bus; and that the palette device further comprises:

an input memory (4011) connected to the multi-bit bus for simultaneously receiving the plurality of color codes therefrom and for latching the plurality of color codes in each bus cycle; a color code transmission circuit (4051) having an externally loadable control register (4371) storing a representation of the number of bits associated with each color code and a representation of the number of color codes transmitted in each bus cycle;

and a first multiplexer (4381) controlled by the control register and connected between the input memory and the look-up table memory, the first multiplexer supplying to the look-up table memory a sequence of bit blocks from data stored in the input memory, each of the bit blocks being equal in number to the number of bits associated with each color code stored in the control register, so that individual ones of the plurality of color codes are transferred from the input memory, the sequence continuing for a number of bit blocks equal to the number of color codes transferred from the multi-bit bus in each bus cycle for each load of the input memory.

2. Palette device according to claim 1, wherein inputs of the first multiplexer are connected to the input memory for the entire width of the bus, the first multiplexer having a number of outputs that is a partial multiple of the width of the bus.

3. A pallet device according to claim 2, wherein the transmission circuit includes a second multiplexer (4383, 4385, 4387) having inputs connected to the input memory for the entire width of the bus, the second multiplexer having a number of outputs which is a different sub-multiple of the width of the bus from that of the first multiplexer (4381).