DE69107432D1 - Einstellbare Verzögerungsanordnung. - Google Patents

Einstellbare Verzögerungsanordnung.

Info

Publication number: DE69107432D1
Authority: DE; Germany
Prior art keywords: adjustable delay; delay arrangement; arrangement; adjustable; delay
Prior art date: 1990-12-27
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Fee Related

Application number

DE69107432T

Other languages

English (en)

Other versions

DE69107432T2 (de

Inventor

Roland Marbot

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Bull SAS

Original Assignee

Bull SAS

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1990-12-27

Filing date

1991-11-27

Publication date

1995-03-23

1991-11-27 Application filed by Bull SAS filed Critical Bull SAS

1995-03-23 Publication of DE69107432D1 publication Critical patent/DE69107432D1/de

1995-06-14 Application granted granted Critical

1995-06-14 Publication of DE69107432T2 publication Critical patent/DE69107432T2/de

2011-11-28 Anticipated expiration legal-status Critical

Status Expired - Fee Related legal-status Critical Current

Classifications

- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/26—Time-delay networks
- H03H11/265—Time-delay networks with adjustable delay

DE69107432T 1990-12-27 1991-11-27 Einstellbare Verzögerungsanordnung. Expired - Fee Related DE69107432T2 (de)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
FR9016339A FR2671245B1 (fr)	1990-12-27	1990-12-27	Dispositif de retard reglable.

Publications (2)

Publication Number	Publication Date
DE69107432D1 true DE69107432D1 (de)	1995-03-23
DE69107432T2 DE69107432T2 (de)	1995-06-14

Family

ID=9403720

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE69107432T Expired - Fee Related DE69107432T2 (de)	1990-12-27	1991-11-27	Einstellbare Verzögerungsanordnung.

Country Status (7)

Country	Link
US (1)	US5463343A (de)
EP (1)	EP0493150B1 (de)
JP (1)	JP2688552B2 (de)
CA (1)	CA2057824C (de)
DE (1)	DE69107432T2 (de)
ES (1)	ES2071263T3 (de)
FR (1)	FR2671245B1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
DE4227282C1 (de) *	1992-08-18	1993-11-25	Siemens Ag	Digitaler Stromschalter
FR2731570B1 (fr) *	1995-03-07	1997-05-23	Sgs Thomson Microelectronics	Circuit logique a etage differentiel
CA2170666A1 (en) *	1995-03-17	1996-09-18	Taewon Jung	Complementary multiplexer with low disabled-output capacitance, and method
US5872477A (en) *	1997-06-13	1999-02-16	Vtc Inc.	Multiplexer with CMOS break-before-make circuit
US5945863A (en) *	1997-06-18	1999-08-31	Applied Micro Circuits Corporation	Analog delay circuit
JP3795733B2 (ja) *	2000-01-31	2006-07-12	富士通株式会社	半導体集積回路
US7287429B2 (en) *	2004-03-25	2007-10-30	Denso Corporation	Capacitive acceleration sensor system
WO2008023624A1 (fr) *	2006-08-24	2008-02-28	Advantest Corporation	Circuit à retard variable, générateur de synchronisation, et appareil pour tester des semi-conducteurs

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4422052A (en) *	1981-05-29	1983-12-20	Rca Corporation	Delay circuit employing active bandpass filter
US4709170A (en) *	1984-08-20	1987-11-24	National Semiconductor Corp.	Subnanosecond programmable phase shifter for a high frequency digital PLL
US4766559A (en) *	1986-03-31	1988-08-23	Tektronix Inc.	Linearity correcting control circuit for tunable delay line
US4866314A (en) *	1986-07-18	1989-09-12	Tektronix, Inc.	Programmable high-speed digital delay circuit
JPH01119114A (ja) *	1987-10-31	1989-05-11	Sony Corp	ディレイ回路
US4797586A (en) *	1987-11-25	1989-01-10	Tektronix, Inc.	Controllable delay circuit
JPH01175407A (ja) *	1987-12-29	1989-07-11	Matsushita Electric Ind Co Ltd	半導体集積回路
US4862020A (en) *	1988-06-20	1989-08-29	Tektronix, Inc.	Electronic delay control circuit having pulse width maintenance
US4893036A (en) *	1988-08-15	1990-01-09	Vtc Incorporated	Differential signal delay circuit
JP2788746B2 (ja) *	1989-02-14	1998-08-20	日本電気アイシーマイコンシステム株式会社	デューティ可変回路

1990
- 1990-12-27 FR FR9016339A patent/FR2671245B1/fr not_active Expired - Fee Related
1991
- 1991-11-27 EP EP91403222A patent/EP0493150B1/de not_active Expired - Lifetime
- 1991-11-27 DE DE69107432T patent/DE69107432T2/de not_active Expired - Fee Related
- 1991-11-27 ES ES91403222T patent/ES2071263T3/es not_active Expired - Lifetime
- 1991-12-17 CA CA002057824A patent/CA2057824C/fr not_active Expired - Fee Related
- 1991-12-18 US US07/809,181 patent/US5463343A/en not_active Expired - Lifetime
- 1991-12-25 JP JP3343186A patent/JP2688552B2/ja not_active Expired - Fee Related

Also Published As

Publication number	Publication date
ES2071263T3 (es)	1995-06-16
FR2671245A1 (fr)	1992-07-03
DE69107432T2 (de)	1995-06-14
EP0493150B1 (de)	1995-02-15
JP2688552B2 (ja)	1997-12-10
CA2057824A1 (fr)	1992-06-28
CA2057824C (fr)	1997-02-11
FR2671245B1 (fr)	1993-03-05
JPH04294631A (ja)	1992-10-19
EP0493150A1 (de)	1992-07-01
US5463343A (en)	1995-10-31

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Legal Events

Date	Code	Title	Description
1996-03-21	8364	No opposition during term of opposition
2008-09-11	8339	Ceased/non-payment of the annual fee