DE69029065T2 - Logical circuitry and method for reordering for a graphic video display memory - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION

This invention relates to block write graphics control data storage writing systems and more particularly to an arrangement that enables economical reordering of data prior to controlling the block write function.

In European Patent Application 0 071 744 a method is disclosed in which a software controlled microprocessor writes a character into a color graphics frame buffer. A bitwise map of each possible character is held in memory, each bit representing the presence or absence of a pixel at a point on a grid. A line of the bitwise map is read and a word is formed in which each bit of the line occurs twice in succession. Another word is formed in which the two-bit code for the desired color for the character is repeated. The two words are then logically ANDed and the result is written into the frame buffer at the location for that line. The process is repeated for each line for the character.

International Patent Application WO88/07235 discloses a bit-wise organized graphics system in which the pixels making up an image frame are stored in a memory in an arrangement suitable for driving sets of pixels making up a frame several pixels high and several pixels wide in the displayed image frame, which is useful for drawing vectors and characters on the display. The specific arrangement of the pixels in the memory is determined by permuting the bits of the (X, Y) addresses of the pixels, where X and Y are the coordinates of the pixels in the displayed image frame, and by applying the permuted addresses to the memory. For some operations on the pixels, data is read from the memory and permuted into an arrangement suitable for that operation before the operation is performed, and is then permuted and read back into the memory.

In U.S. Patent 4,807,189, a bit-wise organized graphics system is disclosed that includes a multiplexer connected to select the value to be stored in the frame buffer for a selected pixel between the value on the data bus and the value stored in a color register. Storing a value in the color register allows that value to be conveniently written in sequence to a number of locations in the addressed frame buffer.

BACKGROUND OF THE INVENTION

Microprocessors intended for graphics applications must be able to move pixel information between frame buffers as quickly as possible. In situations where numerous pixels must be transferred to a frame buffer, the transfer can be accelerated by using a block write feature. Typically, a block write is created by associating a color register with each VRAM component, filling the color register with bits to determine the desired color value of selected portions of the VRAM component, and then using both the VRAM component's address bits and the data bus input to the VRAM component to determine the location within the VRAM component where the color represented by the color register's value appears. With this technique, the data bus is not burdened by multiple copies of the same pixel value and the available memory bandwidth is increased, which in turn speeds up data transfers.

The simplest application where block writing can be used to advantage is padding, where the same pixel value is transferred to a fixed memory area. Furthermore, some forms of data expansion are well suited to the application of block writing techniques. Therefore, if a bit-organized image is stored in compressed form, the ones and zeros can represent the presence or absence of a pixel, and block writes can be used to decompress the bit-organized image. This type of expansion is typically applied to fonts, which are often stored in compressed form to save memory.

Problems arise because memory accesses in regular mode and block write mode must be performed over the same bus, and they must be compatible so that data written (or read) in one mode can be read (or written) in the other mode. This is a problem because the bit order of the compressed representation of the data must be changed or shuffled relative to the regular mode access before the data can be written to the VRAM component in block write mode. This change in bit order is necessary because the compressed data is typically stored with one bit representing each multi-bit display pixel in a specific order. The storage of these bits is serial, with each bit representing a corresponding display point. For example, the first bit (bit 0) represents pixel position one. The second bit (bit 1) represents pixel position two, and the third bit (bit 2) represents pixel position three. Thus, in this example, the bits on the bus uniquely represent the pixel positions, so that bus bit position zero has the data for the first pixel, while bus bit position three has the data for the fourth pixel. Because of the physical arrangement of the VRAM components, where consecutive pixels are in different VRAM chips (or - units), the data must be reordered before being passed to the VRAM components. Consider the case where the VRAM components are four bits wide (four levels) on a 32-bit wide data bus. Positions 0 - 3 of the data bus would be connected to the first VRAM component, which in turn can control bits 0 - 3 of the first pixel in a normal write situation. Without shuffling, the compressed data at bus bit position 1 (the second position), which should be intended to control the second pixel, will eventually be transferred to the second input of the first VRAM component, which in a normal access is associated with the ninth pixel, rather than the required second pixel. Thus, when operating in block write mode, a change in bit ordering is required.

Another problem arises because the type of data shuffling depends on the size of the pixel. Different shuffles must be done to cover a wide range of pixel sizes and VRAM arrangements. It is fair to say that the block write mode of the video RAM components can only be reasonably used to fill areas in exact multiples of the block size. The nature of the block write function of the VRAM components leads to a shuffled writing of the pixels within a block if no data shuffling is done.

Accordingly, there is a need in the art for a hybrid arrangement that enables efficient handling of data so that block writes can be performed economically.

There is a further need in the art for a mixed logic that can be used for any pixel size or VRAM arrangement.

There is a further need in the art to design a system using the block write mode that can still properly and economically control the writing of each pixel within the block. There is also a need for a system which can be used for different numbers of color levels.

SUMMARY OF THE INVENTION

The present invention provides a video graphics circuit comprising:

several first data input ports;

a memory for storing data representing pixels of an image, each pixel being represented by a plurality of bits, the memory having a plurality of second data input terminals;

a rearrangement circuit for connecting the plurality of first data input terminals to the plurality of second data input terminals in different arrangements, depending on whether the video graphics circuit is either

in a first operating mode in which data present at the plurality of first data input terminals are stored as pixel values in the memory, or

operating in a second block write mode in which individual bits of the data present at the plurality of first data input terminals determine whether a value held in a register is applied to corresponding pixels in the memory; and

an expansion circuit connected between the plurality of first data input terminals and the reordering circuit for reproducing bits present at the first data input terminals and applying the reproduced bits in parallel form to the reordering circuit.

The reordering circuit may be a mixer circuit having a plurality of inputs and an equal number of outputs, the mixer circuit including: an equal number of latches, each of which controls one input and one or more outputs, and circuitry for controlling which output is connected to which input at any one time.

The reordering circuit can be a multiplexing circuit.

The reordering circuit may include a memory with a look-up table.

The video graphics circuit may include a circuit for shifting bits present at the first data input terminals before they are applied to the expansion circuit.

The memory can be organized into layers, and bits of a pixel are stored in respective layers.

The memory may contain one or more VRAM components.

The video graphics circuit may include circuitry for determining the number of VRAM components containing the same pixel information and for controlling the expansion circuit according to that determination.

The expansion circuit may be arranged to control the expansion when the graphics memory is configured with a number of VRAM components that control the pixels.

A graphics processing system may include the video graphics circuitry.

In an example using four-bit VRAM components and pixels, assuming that each VRAM component has four data input paths (one for each bit of the pixel), there is a separation or reordering of four bit positions between the compressed data and the actual input to the VRAM components. This reordering is performed by a shuffling circuit.

A bus bit 0 compressed in this way is transferred to a position 0 after mixing, while a bus bit 1 is transferred to a position 4 after mixing. Similarly, a compressed bus bit 2 is transferred to a position 8 after mixing, and a compressed bus bit 3 is transferred to a position 12 after mixing. This continues for 7 compressed bit positions, with a compressed bit 7 being transferred to a position 28 after mixing. The next compressed bit 8 is transferred to position 1 after mixing, while a compressed bit 9 is transferred to a position 5 after mixing. This disjointed sequence continues across the entire width of the bus.

In an example where the pixel size is 8 bits, two four-bit wide VRAM components would be required, each comprising one half of the 8-bit pixel. In this situation, the extension then requires a different algorithm, namely, rearranging the ordinate position of the compressed bit by 8 positions. It is recognized that all VRAM components comprising the same pixel are preferably provided with an identical control signal. In this way, for a 2-VRAM pixel (say 8 bits), two positions on the bus preferably reflect the same compressed bit value.

There are two ways to accomplish the shuffling operation. One is to make a larger bus, for example 64 lines. This requires additional or larger VRAM components and more circuitry to control the bus. The other is for the shuffling circuit to have a different shuffling pattern. In both cases, if the pixel is contained in more than one VRAM component, the compressed data must control more than one VRAM component.

The memory addressing is arranged to correspond to the larger amount of data written to the VRAM component when a series of block write accesses (e.g., filling a large screen area) is performed. In fact, the 4 bits of data transferred to a VRAM component are expanded internally by a factor of 4 in the block write mode. In this way, a 32-bit wide data bus within the VRAM components is expanded to 128 bits in the block write mode. Therefore, in order to efficiently advance from one addressable location to the next adjacent one, it is necessary to advance the address by 128 (in terms of bit address) instead of 32 as is done in regular addressing. would increment or decrement (depending on the direction).

The merge operation is implemented in one example by properly connecting a multiplexer function for any given bit position. Multiplexing selects between the normal mode (or run through mode) and one or more merge functions as needed.

It is a technical advantage associated with this invention that a mechanism is provided for writing pixels to a memory array in a compatible manner in the normal mode and in the block write mode.

SHORT DESCRIPTION OF THE DRAWING

For a more complete understanding of the present invention and further advantages thereof, reference is now made to the following detailed description, which should be read in conjunction with the accompanying drawings, in which

FIGURE 1 shows a stylized view of a VRAM memory;

FIGURE 2 shows a VRAM memory connection to a data bus;

FIGURE 3 shows a mixing circuit connected to the data bus;

FIGURES 4 and 5 show partial connections for other mixed circuits;

in FIGURE 6 a four-position extension is shown;

FIGURE 7 shows the cross connections of the mixed circuits for all situations;

FIGURE 8 shows an embodiment of a mixed circuit

and

FIGURE 9 shows an embodiment of a mixing circuit used for several different memory devices.

DETAILED DESCRIPTION OF THE INVENTION

Referring to FIGURE 1, a brief discussion of the memory structure of a typical graphics memory system is given before the actual detailed description of the operation of the embodiment of this invention is given. While there are numerous memory arrangements and systems that could be used, in the preferred embodiment it is typical to use a structure as shown in FIGURE 1, in which eight VRAM memories 200, 201, etc. are used in an array. Each VRAM memory or VRAM unit has a 4-bit wide data port that can be treated as having levels 11, 12, 13, and 14. The structure of each level is such that a single data line is used to write information to that level. These lines are labeled 0, 1, 2, and 3 for each level. In a system using a 32-bit wide data bus, such as data bus 20, there would be 8 VRAM memories (two of which are shown in FIGURE 1), each with four data lines connected to the data bus.

For a VRAM 200 with a 32-bit wide data bus, its four data lines would be connected to data bus lines 0, 1, 2, and 3, respectively. Similarly, the four lines 0, 1, 2, and 3 of VRAM 201 would be connected to data bus lines 4, 5, 6, and 7, respectively. This continues for the remaining six VRAM components, so that the lines of the last VRAM component are connected to lines 28, 29, 30, and 31 of bus 20. The entire connection set is shown in FIGURE 2.

Continuing with FIGURE 1, the memories are arranged so that the pixel information for the graphics display is stored serially in the same row across the planes. Assuming a four bits per pixel system, successive pixels are then stored in successive VRAM components. In this situation, pixel 0 is stored in VRAM component 200 and pixel 1 is stored in VRAM component 201. Pixel storage for pixels 2 through 7 is shown in FIGURE 2, but not in FIGURE 1. The pixel information for pixel 8 is then still stored in row 1, but in column 2 of the VRAM component 200. The reason for this arrangement of the pixel information will become more apparent when we understand how the information is read from memory.

Continuing with FIGURE 1, each VRAM level has a serial register 16 for shifting information out of a memory row. The outputs of these registers are connected to the data output bus 15 in the same way that the data input lines are connected to the data input bus. In this way, data from a memory row, say row 1, is moved into the register 16. This is done for each level of the eight memory arrays.

Looking at the data output bus 15 at a time, it can be seen that the first bit in each shift register is on the bus. Assuming that row 1 has been output to the bus, on line 0 of the bus there is a bit A1 of row 1 of the memory 200. On line 1 of the output bus 15 there is a bit B1 of row 1; on line 2 there is a bit C1 of row 1; and on line 3 is a bit D1 of row 1. These bits are followed by bits A1, B1, C1, D1 of row 1 of memory 201 on lines 4, 5, 6, and 7 respectively. At a first instant, therefore, on data output bus 15 are the four bits that make up the pixel, followed by the four bits that make up pixel 1, followed by the four bits that make up pixel 2. This continues until the 32 bits that make up the 8 pixels 0 - 7 are on the successive lines of data output bus 15. These bits are transferred to the graphics display and all shift registers are shifted by one position, thus providing the bus with the pixel information for the next 8 pixels, namely pixels 8 - 15. This shifting then continues until the entire row has been shifted out, and then a new row is selected for loading into the output register.

Up to this point, it has been assumed that the bit information per pixel is 4 bits. For example, if the pixel information is 8 bits, two 4-bit wide VRAM components would need to be used for each pixel. This would change the bit patterns somewhat. This aspect of the invention is discussed in more detail below. It should be further noted that memory sizes and structures continue to vary and that the size and structure shown is for illustrative purposes only and that this invention can be used with many different memory arrangements and with different pixel sizes.

It should be noted that the memory representation shown in FIGURES 2 through 5 is a one-dimensional mapping of what is conceptually a three-dimensional matrix as shown in FIGURE 1. From here on, therefore, the term "row" refers to the set of pixels addressed by the bus at any given time.

FIGURE 2 shows a complete memory array with eight VRAM components, where the information to control pixels 0-7 is in the top row of VRAM components 200 through 207, while pixels 8 through 15 are in row 2, while pixels 16 through 23 are in row 3, and while pixels 24 through 31 are in row 4. This arrangement continues for each subsequent memory row.

For normal writes to the VRAM memory, data bits are received over the data bus 20. The location of the information on the bus determines where the data is to be stored in the VRAM components. In this way, a bit on line 0 of the bus 20 is transferred to line 0 of the VRAM component 200. Assuming that the address location of the first row of the VRAM component 200 has also been selected, this bit information is assigned to bit 0 of the pixel. This is the well-known conventional operation of graphics systems and no details of this operation are given here. It is sufficient for an understanding of this invention to note that a given data word, for example data word 21, has bits on the ordinate position which are directly transferred to the correct bit positions as a result of the physical connections and associations between the data bus and the VRAM components. It should also be noted that the information at ordinate positions 0-3 of the data word 21 can be transferred via the bus 20 to any of the numerous pixels 0, 8, 16, 24, 32, etc. The actual storage location depends on other simultaneous addressing of the VRAM components, not all of which is shown here, but which is well known in the art.

The previously described method of writing out data requires 32 bits of data and a complete memory write cycle for each line (8 pixels). In some situations, such as when drawing a background color on a screen, many pixels have the same information associated with them. The block write method of loading a VRAM component was devised to handle this situation. This method, well known in the art, uses a special register on each VRAM component, such as register 210 shown in connection with VRAM component 200, which has bits for transfer to selected pixel locations within the memory. These bits are loaded prior to starting a block write operation.

During the block write operation, the memory is loaded in a different manner than during normal loading. The four data input lines are used, but this time each bit controls the transfer of the specific register bits to a specific memory row in that VRAM component. For example, suppose that in VRAM component 200 it is desired to load pixels 0, 8 and 24 with the bits from register 210, while leaving pixel 16 unchanged. In this case, lines 0, 1, 3 are at logic level 1, while line 2 is at logic level 0. The same situation would exist for the entire 32-bit wide bus in that the ordinate position of the bits would determine whether information is to be to a corresponding pixel in a corresponding VRAM memory row. It can be seen that this is different from normal data loading, where the data itself comes from the data bus. For block writes, the data comes from the special registers associated with each VRAM component, and the bits on the data bus merely provide on-off or load/not load control, depending on their position on the various lines of the bus.

The data word that controls this process is then said to be in compressed format, so that the ordinate position of each bit, which is 1 or 0, controls a function. It should also be noted that representing on and off as 1 and 0 is for illustrative purposes only and that the reverse can also be true.

From FIGURE 3, it can be seen that a compressed data word 39 has ordinate positions 0 - 31 that must be transferred to the VRAM components to control different pixels according to the ordinate position of the word's data. Therefore, pixel 0 is to be controlled by compressed data bit 0, while pixel 1 is to be controlled by compressed data bit 1. In this way, compressed data bit 31 should then control pixel 31. This is easier said than done.

For pixel 0, this is easy because it is controlled by line 0 of VRAM component 200, which is connected to compressed bit 0. However, the problem begins with the bit at position 1 of compressed data word 39. As shown in FIGURE 2, this uncompressed bit is connected to pin 1 of VRAM component 200. However, as previously discussed, the bit at ordinate position 1 of the compressed data is used to control the transfer of information from the special register to pixel 1. Pixel 1, in turn, is controlled by a 1 or applied to line 1 of a VRAM component 201. This line is in turn connected to line 4 of bus 20. A comparison of FIGURES 2 and 3 shows that bit position 1 of the input data word in a situation is transmitted to line 1 of bus 20, while in the other situation it is transmitted to line 4. It is therefore clear that bit reordering is required when compressed words are used to control data transfer in the block write mode.

This reordering is accomplished by a shuffling circuit 32 located between the compressed data input and the actual data bus. The shuffling circuit 32 is controlled by the processor to allow data to flow directly through, which is the situation in FIGURE 2, or to shuffle the lines in some pattern, as is required for FIGURE 3. This arrangement does not require processing time to shuffle the information, but rather establishes a pattern based on the physical design of the memory bus arrangement and refers to that design each time a block write is invoked.

The mixing circuit could be hard-wired or controlled by software inside or outside the processor.

Now assume that it is desirable to use eight bits per pixel instead of four bits per pixel and to maintain a 32-bit wide data bus. Assume further that VRAM components with four levels per unit are still used, as discussed with respect to FIGURE 1. In such a situation, the reordering of the bits of the compressed word would be different than if only four bits per pixel were used. This is readily apparent from FIGURE 4, where VRAM components 200 and 201 now both have pixel 0 information, while VRAM components 202 and 203 have pixel 1 information.

It then follows that all other ordinate positions of the compressed word are assigned to different lines of the bus, while the compressed data bit is still assigned to line 0 of the VRAM component 200. For example, let us take ordinate position 2 of the compressed word. In FIGURE 3, ordinate position 2 of the compressed data word is assigned to pixel 2 and to bus line 8. However, in FIGURE 4, the mapping is made to bus line 16. This then suggests separate blending circuits for systems where different pixel arrangements occur. Furthermore, since half of each pixel is contained in a separate VRAM element, both halves are controlled by the same compressed data control bit. In this way, each compressed data control bit must be duplicated once for each additional VRAM element containing part of a given pixel. This also suggests different blending circuits for each pixel arrangement.

It is clear from FIGURE 4 that only 16 bits of the compressed word control all the VRAM components in a 32 bit wide bus arrangement, since each bit of the compressed word is connected to two VRAM inputs. The first system for solving this problem is to maintain the 32 bit wide bus and use two bus cycles to use both halves of the 32 bit compressed word. The other option is to use all 32 bits of the compressed word, thus expanding the data bus to 64 bits.

FIGURE 9 is a schematic diagram to explain how a simple multiplexer achieves the required mixing of output bits 0, 1 and 2 to support the 4-level and 8-level modes of operation of the preferred embodiment. In the normal mode of operation, the multiplexer function simply transfers the appropriate bit position from input to output (i.e., 0 to 0, 1 to 1, and 2 to 2). For the 4-level mode selection, the connections from input to output are made as shown in FIGURE 4 (0 to 0, 8 to 1, 16 to 2). For the 8-level selection, the connections are made as shown in FIGURE 5 (0 to 0, 0 to 4, 8 to 2). Of course, other multiplexer functions could be set up to support different numbers of levels and different bus organizations.

While the mixing function in the preferred embodiment is performed by a multiplexer hardware function another means, such as a method using a software-based lookup table, could be used to perform the mixing.

It can be seen from FIGURE 5 that extending the compressed word by duplicating each bit corresponding to the number of VRAM components used for a pixel results in the same blending circuit being able to be used for different memory/pixel arrangements. This solution, implemented by the duplication/extension circuit 52, also enables the two VRAM components of a given pixel since the color information must be passed to all pixel bits even if those bits are located within two VRAM components.

The essence of this operation is that the duplication and expansion occurs before the merging operation, thus allowing the same merging arrangement for both operations. In typical operations the same arrangement would be used for any given system and therefore only one determination of duplication/expansion needs needs to be made. However, situations may arise where more than one VRAM system arrangement is controlled by the same processor and so dynamic control may be required. This can be easily accomplished by arranging the duplication/expansion circuit 52 to operate on a case-by-case basis under the control of the system processor.

The duplication/expansion circuit 52 may take any type of register circuit or processor capable of rearranging and adding numbers. This may be operated by microcode under the control of the main processor or by a dedicated processor or may be performed by a host computer if desired. The function performed by the circuit 52 is mathematical in nature and one skilled in the art can therefore easily devise numerous arrangements to perform the desired function.

The circuit 52 may be adaptable to a system to change the duplication and extension function on a dynamic basis in response to received data or in response to a flag in a register to allow changing of the pixel/memory arrangements. Thus, for a pixel size of 16 bits and a VRAM component of the size shown in FIGURE 1, namely four bits, four VRAM components would be used for each pixel and the extension would be four bits. As shown in FIGURE 6, in this situation the data of an extended word 61 would comprise the data of compressed bit ordinate position 0 after being expanded to the ordinate positions 0, 1, 2, 3 of the extended word. In this situation, the data would be expanded from the compressed ordinate position 1 to ordinate bit positions 4, 5, 6, 7, etc.

It can be seen from the table shown in FIGURE 7 that the duplicated data at inputs 0, 1, 2, 3 of the mixer circuit is transferred to outputs 0, 4, 8, 12. It can be seen from FIGURE 4 that these outputs are transferred to VRAM components 200, 201, 202, 203, which are the four VRAM components that hold pixel 0 if that pixel is 16 bits long.

The compressed word is provided in a register so that it can be rotated through all 32 bits for any given memory clock cycle, regardless of how many bits are extended. This allows the system to operate uninterruptedly, regardless of pixel size. This also allows complete flexibility in storage to allow starting and stopping at any given pixel boundary.

FIGURE 7 shows the input/output correspondence for the mixer circuit 32 when it is in the mixer mode. Note that each input has two possible outputs: the mixer output shown and the pass-through output not shown. Of course, in the pass-through output, input 0 is connected to output 0, input 1 is connected to Output 1 is connected, input 2 is connected to output 2, and so on. A switching circuit is used to switch between the continuous mode of the mixer circuit and the mixer mode of operation of the mixer circuit. FIGURE 8 shows an embodiment of the mixer circuit 32, with registers 0 and 1 being shown for positions 0 and 1.

As shown in FIGURE 8, the input bus has 32 lines and the output bus also has 32 lines. Between these lines are a number of latches, two of which, 800 and 801, are shown. A single input of each latch is connected to a respective input bus line and two outputs are connected to the passthrough and the merge circuits of FIGURE 7. The latches load information directly onto the input bus after the signal is applied to the load line. For passthrough operation, a signal is applied to the REGULAR line and outputs of the latches are clocked with a passthrough directly through the merge circuit as previously mentioned. However, when the mixer circuit is used in the mixer mode, the MIX line is pulsed to switch the outputs. For example, in the run through mode, latch 801 is connected to line 1 of the output bus. However, it will be seen that in the mixer mode, another output of latch 1 is connected to line 4 of the output bus. All of the latches of mixer circuit 32 are wired to their counterparts so that the mixer output line of each latch is connected to the output bus line as shown in FIGURE 7. This arrangement allows the mixer circuit 32 to be selectively controlled in the run through mode or the mixer mode under the control of the system processor.

The circuit shown in FIGURE 8 can be extended to include the multiple inputs required for the mixing circuit 42 required mixers. In this situation, an additional controlled output line would extend from each latch to another output. In this mode, a second mixer control signal would propagate to control multiple outputs of each latch, the number of multiples being a function of the number of VRAM components having the same pixel information.

While the circuit and method presented here have been described in terms of the block-write operation of a graphics processing system, they can be used in numerous other situations where ordinate coordination is required to control the adjustments under consideration. It should be noted that the circuit, including the mixer circuit and the processor, could be integrated on a single chip.

While the discussion referred to block write mode with respect to VRAM components, it is to be understood that the same type of memory operations could be used for memories not specifically designed to support video applications.

Although the present invention has been described with respect to a specific preferred embodiment, various changes and modifications may be suggested by one skilled in the art, and it is intended that the present invention include such changes and modifications provided they come within the scope of the appended claims.

Claims (10)

1. Video graphics circuit with: a plurality of first data input ports; a memory (200, 201, 207) for storing data representing pixels of an image, each pixel being represented by a plurality of bits and the memory having a plurality of second data input terminals; a rearrangement circuit (32) for connecting the plurality of first data input terminals to the plurality of second data input terminals in different arrangements depending on whether the video graphics circuit is either in a first operating mode in which data present at the multiple first data input terminals are stored as pixel values in the memory, or in a second, block write mode, in which individual bits of the data present at the plurality of first data input terminals determine whether a value held in a register is applied to corresponding pixels in the memory, operated; and an expansion circuit (52) connected between the plurality of first data input terminals and the reordering circuit for reproducing bits present at the first data input terminals and for applying the reproduced bits in parallel form to the reordering circuit. 2. Video graphics circuit according to claim 1, wherein the rearranging circuit is a mixer circuit with multiple inputs and an equal number of outputs, the mixer circuit comprising: an equal number of latches, each of which controls one input and one or more outputs; and a circuit to control which output is connected to which input at any given time. 3. A video graphics circuit according to claim 1, wherein the reordering circuit is a multiplexing circuit. 4. The video graphics circuit of claim 1, wherein the reordering circuit includes a memory with a look-up table. 5. Video graphics circuit according to one of claims 1 to 4, with a circuit arrangement for shifting bits which are present at the first data input terminals before they are applied to the expansion circuit. 6. A video graphics circuit according to any preceding claim, wherein the memory is organized into layers and bits of a pixel are stored in respective layers. 7. The video graphics circuit of claim 6, wherein the memory includes one or more VRAM components. 8. Video graphics circuit according to claim 7, further comprising circuitry for determining the number of VRAM components containing the same pixel information and for controlling the expansion circuit according to this determination. 9. A video graphics circuit as claimed in claim 7, wherein the expansion circuit is arranged to control the expansion when the graphics memory is configured with a number of VRAM components that control the pixels. 10. A graphics processing system comprising a video graphics circuit according to one of claims 1 to 9.